* Library of 74AS Family Digital Models * * Copyright OrCAD, Inc. 1998 All Rights Reserved. * * * $Revision: 1.3 $ * $Author: RPEREZ $ * $Date: 16 Apr 1998 14:23:28 $ * * *$ *--------- * 74AS00 Quadruple 2-input Positive-Nand Gates * * The ALS/AS Data Book, 1986, TI * tdn 06/23/89 Update interface and model names * .subckt 74AS00 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(2) DPWR DGND + A B Y + D_AS00 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_AS00 ugate ( + tplhmn=1ns tplhmx=4.5ns + tphlmn=1ns tphlmx=4ns + ) *$ *--------- * 74AS02 Quadruple 2-input Positive-Nor Gates * * The ALS/AS Data Book, 1986, TI * tdn 06/23/89 Update interface and model names * .subckt 74AS02 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nor(2) DPWR DGND + A B Y + D_02AS IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_02AS ugate ( + tplhmn=1ns tplhmx=4.5ns + tphlmn=1ns tphlmx=4.5ns + ) *$ *--------- * 74AS04 Hex Inverters * * The ALS/AS Data Book, 1986, TI * tdn 06/23/89 Update interface and model names * .subckt 74AS04 A Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 inv DPWR DGND + A Y + D_AS04 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_AS04 ugate ( + tplhmn=1ns tplhmx=5ns + tphlmn=1ns tphlmx=4ns + ) *$ *--------- * 74AS08 Quadruple 2-input Positive-And Gates * * The ALS/AS Data Book, 1986, TI * tdn 06/23/89 Update interface and model names * .subckt 74AS08 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 and(2) DPWR DGND + A B Y + D_AS08 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_AS08 ugate ( + tplhmn=1ns tplhmx=5.5ns + tphlmn=1ns tphlmx=5.5ns + ) *$ *--------- * 74AS10 Triple 3-input Positive-Nand Gates * * The ALS/AS Data Book, 1986, TI * tdn 06/23/89 Update interface and model names * .subckt 74AS10 A B C Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(3) DPWR DGND + A B C Y + D_AS10 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_AS10 ugate ( + tplhmn=1ns tplhmx=4.5ns + tphlmn=1ns tphlmx=4.5ns + ) *$ *--------- * 74AS11 Triple 3-input Positive-And Gates * * The ALS/AS Data Book, 1986, TI * tdn 06/23/89 Update interface and model names * .subckt 74AS11 A B C Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 and(3) DPWR DGND + A B C Y + D_AS11 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_AS11 ugate ( + tplhmn=1ns tplhmx=6ns + tphlmn=1ns tphlmx=5.5ns + ) *$ *--------- * 74AS20 Dual 4-input Positive-Nand Gates * * The ALS/AS Data Book, 1986, TI * tdn 06/26/89 Update interface and model names * .subckt 74AS20 A B C D Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(4) DPWR DGND + A B C D Y + D_AS20 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_AS20 ugate ( + tplhmn=1ns tplhmx=5ns + tphlmn=1ns tphlmx=4.5ns + ) *$ *--------- * 74AS21 Dual 4-input Positive-And Gates * * The ALS/AS Data Book, 1986, TI * tdn 06/26/89 Update interface and model names * .subckt 74AS21 A B C D Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 and(4) DPWR DGND + A B C D Y + D_AS21 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_AS21 ugate ( + tplhmn=1ns tplhmx=6ns + tphlmn=1ns tphlmx=6ns + ) *$ *--------- * 74AS27 Triple 3-input Positive-Nor Gates * * The ALS/AS Data Book, 1986, TI * tdn 06/26/89 Update interface and model names * .subckt 74AS27 A B C Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nor(3) DPWR DGND + A B C Y + D_AS27 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_AS27 ugate ( + tplhmn=1ns tplhmx=5.5ns + tphlmn=1ns tphlmx=4.5ns + ) *$ *--------- * 74AS30 8-input Positive-Nand Gates * * The ALS/AS Data Book, 1986, TI * tdn 06/26/89 Update interface and model names * .subckt 74AS30 A B C D E F G H Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(8) DPWR DGND + A B C D E F G H Y + D_AS30 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_AS30 ugate ( + tplhmn=1ns tplhmx=5ns + tphlmn=1ns tphlmx=4.5ns + ) *$ *--------- * 74AS32 Quadruple 2-input Positive-Or Gates * * The ALS/AS Data Book, 1986, TI * tdn 06/26/89 Update interface and model names * .subckt 74AS32 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 or(2) DPWR DGND + A B Y + D_AS32 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_AS32 ugate ( + tplhmn=1ns tplhmx=5.8ns + tphlmn=1ns tphlmx=5.8ns + ) *$ *--------- * 74AS34 Hex Noninverters * * The ALS/AS Data Book, 1986, TI * tdn 06/26/89 Update interface and model names * .subckt 74AS34 A Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 buf DPWR DGND + A Y + D_AS34 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_AS34 ugate ( + tplhmn=1ns tplhmx=5.5ns + tphlmn=1ns tphlmx=6ns + ) *$ *--------- * 74AS74 Dual D-Type Positive-Edge-Triggered Flip-Flops w/ Preset & Clear * * The ALS/AS Data Book, 1986, TI * tdn 06/28/89 Update interface and model names * .subckt 74AS74 1CLRBAR 1D 1CLK 1PREBAR 1Q 1QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UFF1 dff(1) DPWR DGND + 1PREBAR 1CLRBAR 1CLK 1D 1Q 1QBAR + D_AS74 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_AS74 ueff ( + twpclmn=4ns twclklmn=5.5ns + twclkhmn=4ns tsudclkmn=4.5ns + tsupcclkhmn=2ns tppcqlhmn=3.00ns + tppcqlhmx=7.5ns tppcqhlmn=3.50ns + tppcqhlmx=10.5ns tpclkqlhmn=3.5ns + tpclkqlhmx=8ns tpclkqhlmn=4.5ns + tpclkqhlmx=9ns + ) *$ *--------- * 74AS86 Quadruple 2-input Exclusive-Or Gates * * The ALS/AS Data Book, 1986, TI * tdn 06/29/89 Update interface and model names * .subckt 74AS86 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 xor DPWR DGND + A B Y + D_AS86 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_AS86 ugate ( + tplhty=3.6ns tphlty=3.5ns + ) *$ *-------- * 74AS95 4-BIT PARALLEL SHIFT REGISTERS * * ALS/AS LOGIC CIRCUITS DATA BOOK, 1988, TI * KN 7-3-92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74AS95 MODE_I CLK1_I CLK2_I SER_I + A_I B_I C_I D_I QA_O QB_O QC_O QD_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UAS95LOG LOGICEXP(11,13) DPWR DGND + MODE_I CLK1_I CLK2_I SER_I A_I B_I C_I D_I QA QB QC + MODE CLK1 CLK2 SER A B C D CLK DA DB DC DD + D0_GATE IO_AS00 + IO_LEVEL={IO_LEVEL} + LOGIC: + MODE = { MODE_I } + CLK1 = { CLK1_I } + CLK2 = { CLK2_I } + SER = { SER_I } + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + * INTERMEDIATE TERM + MODEBAR = { ~MODE } + + CLK = { ~((MODEBAR & CLK1) | (MODE & CLK2)) } + DA = { (MODEBAR & SER) | (MODE & A) } + DB = { (MODEBAR & QA) | (MODE & B) } + DC = { (MODEBAR & QB) | (MODE & C) } + DD = { (MODEBAR & QC) | (MODE & D) } * U1 DFF(4) DPWR DGND $D_HI $D_HI CLK + DA DB DC DD QA QB QC QD + $D_NC $D_NC $D_NC $D_NC + D0_EFF IO_AS00 * UAS95DLY PINDLY (4,0,8) DPWR DGND + QA QB QC QD + CLK1 CLK2 MODE SER A B C D + QA_O QB_O QC_O QD_O + IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + CLK = { CHANGED_HL(CLK1,0) | CHANGED_HL(CLK2,0) } + + PINDLY: + QA_O QB_O QC_O QD_O = { + CASE( + CLK & TRN_LH, DELAY(2NS,-1,10NS), + CLK & TRN_HL, DELAY(2NS,-1,9.5NS), + DELAY(3NS,-1,11NS) ;DEFAULT + ) + } + + FREQ: + NODE = CLK1 + MAXFREQ = 100MEG + + FREQ: + NODE = CLK2 + MAXFREQ = 100MEG + + WIDTH: + NODE = CLK1 + MIN_HI = 5NS + MIN_LO = 5NS + + WIDTH: + NODE = CLK2 + MIN_HI = 5NS + MIN_LO = 5NS + + SETUP_HOLD: + DATA(4) A B C D + CLOCK HL = CLK2 + SETUPTIME = 2NS + HOLDTIME = 2.5NS + WHEN = { (MODE != '0 ^ CHANGED(MODE,0)) } + + SETUP_HOLD: + DATA(1) SER + CLOCK HL = CLK1 + SETUPTIME = 2NS + HOLDTIME = 2.5NS + WHEN = { (MODE != '1 ^ CHANGED(MODE,0)) } + + SETUP_HOLD: ; MODE HOLD TIME FOR CLK1 + DATA(1) MODE + CLOCK HL = CLK1 + HOLDTIME_LO = 3NS + + SETUP_HOLD: ; T_ENABLE1 + DATA(1) MODE + CLOCK HL = CLK1 + SETUPTIME_LO = 12NS + MESSAGE = "TENABLE1 IS NOT MET" + + SETUP_HOLD: ; T_ENABLE2 + DATA(1) MODE + CLOCK HL = CLK2 + SETUPTIME_HI = 12NS + MESSAGE = "TENABLE2 IS NOT MET" + + SETUP_HOLD: ; T_INHIBIT1 + DATA(1) MODE + CLOCK LH = CLK1 + SETUPTIME_HI = 2.5NS + MESSAGE = "TINHIBIT1 IS NOT MET" * .ENDS * * *$ *--------- * 74AS109 Dual J-KBar Positive-Edge-Triggered Flip-Flops w/ PreSet & Clear * * National Semiconductor, 1987 * cv 08/20/90 Created from LS * .subckt 74AS109 CLK PRBAR CLRBAR J KBAR Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 jkff(1) DPWR DGND + PRBAR CLRBAR CLKBAR J K Q QBAR + D_AS109 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 inva(2) DPWR DGND + KBAR CLK K CLKBAR + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} .ends * .model D_AS109 ueff ( + tppcqlhmn=3ns tppcqlhmx=8ns + tppcqhlmn=3.5ns tppcqhlmx=10.5ns + tpclkqlhmn=3.5ns tpclkqlhmx=9ns + tpclkqhlmn=4.5ns tpclkqhlmx=9ns + twclkhmn=4ns twclklmn=5.5ns + twpclmn=4ns tsudclkmn=5.5ns + tsupcclkhmn=2ns thdclkmn=0ns + ) *$ *--------- * 74AS136 Quadruple 2-input Exclusive-Or Gates with Open-Collector Outputs * * The ALS/AS Data Book, 1986, TI * tdn 07/05/89 Update interface and model names * .subckt 74AS136 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 xor DPWR DGND + A B Y + D_AS136 IO_AS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends 74AS136 * .model D_AS136 ugate ( + tplhty=10.5ns tphlty=4.3ns + ) *$ *--------- * 74AS137 DECODER/DEMULTIPLEXER 3-8 LINE WITH ADDRESS LATCHES * * ALS/AS LOGIC CIRCUITS DATA BOOK, TI, 1986 * JLS 8-4-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES * .SUBCKT 74AS137 G1_I G2BAR_I GLBAR_I A_I B_I C_I + Y0_O Y1_O Y2_O Y3_O Y4_O Y5_O Y6_O Y7_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 DLTCH(3) DPWR DGND + $D_HI $D_HI LATCHEN + A B C + QA QB QC + QABAR QBBAR QCBAR + D0_GFF IO_AS00 * UAS137LOG LOGICEXP (12,16) DPWR DGND + G1_I G2BAR_I GLBAR_I A_I B_I C_I QA QB QC QABAR QBBAR QCBAR + G1 G2BAR GLBAR A B C LATCHEN ENABLE + Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 + D0_GATE IO_AS00 + IO_LEVEL={IO_LEVEL} + + LOGIC: + G1 = { G1_I } + G2BAR = { G2BAR_I } + GLBAR = { GLBAR_I } + A = { A_I } + B = { B_I } + C = { C_I } + LATCHEN = { ~GLBAR } + ENABLE = { G1 & ~G2BAR } + Y0 = { ~(ENABLE & QCBAR & QBBAR & QABAR) } + Y1 = { ~(ENABLE & QCBAR & QBBAR & QA ) } + Y2 = { ~(ENABLE & QCBAR & QB & QABAR) } + Y3 = { ~(ENABLE & QCBAR & QB & QA ) } + Y4 = { ~(ENABLE & QC & QBBAR & QABAR) } + Y5 = { ~(ENABLE & QC & QBBAR & QA ) } + Y6 = { ~(ENABLE & QC & QB & QABAR) } + Y7 = { ~(ENABLE & QC & QB & QA ) } * UAS137DLY PINDLY (8,0,7) DPWR DGND + Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 + G1 G2BAR GLBAR A B C ENABLE + Y0_O Y1_O Y2_O Y3_O Y4_O Y5_O Y6_O Y7_O + IO_AS00 + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + ABLE1 = { CHANGED(ENABLE,0) & CHANGED(G1,0) } + ABLE2 = { CHANGED(ENABLE,0) & CHANGED(G2BAR,0) } + ABLEL = { CHANGED(GLBAR,0) } + ADDR = { CHANGED(A,0) | CHANGED(B,0) | CHANGED(C,0) } + + PINDLY: + Y0_O Y1_O Y2_O Y3_O Y4_O Y5_O Y6_O Y7_O = { + CASE ( + ABLE2 & TRN_LH, DELAY(2NS,-1, 8.0NS), + ABLE2 & TRN_HL, DELAY(2NS,-1, 8.5NS), + ABLE1 & TRN_HL, DELAY(2NS,-1, 9.0NS), + ABLE1 & TRN_LH, DELAY(2NS,-1,10.0NS), + ADDR , DELAY(2NS,-1,12.5NS), + ABLEL & TRN_LH, DELAY(3NS,-1,13.5NS), + ABLEL & TRN_HL, DELAY(3NS,-1,14.0NS), + DELAY(3NS,-1,14.0NS) + ) + } + + WIDTH: + NODE = GLBAR + MIN_LO = 4.5NS + SETUP_HOLD: + DATA(3) = A B C + CLOCK LH = GLBAR + SETUPTIME = 4NS + HOLDTIME = 1NS * .ENDS * *$ *--------- * 74AS138 DECODER/DEMULTIPLEXER 3-8 LINE * * ALS/AS LOGIC CIRCUITS DATA BOOK, 1986, TI * JLS 8-4-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES * .SUBCKT 74AS138 G1_I G2ABAR_I G2BBAR_I A_I B_I C_I + Y0_O Y1_O Y2_O Y3_O Y4_O Y5_O Y6_O Y7_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UAS138LOG LOGICEXP (6,15) DPWR DGND + G1_I G2ABAR_I G2BBAR_I A_I B_I C_I + G1 G2ABAR G2BBAR A B C ENABLE + Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 + D0_GATE IO_AS00 + IO_LEVEL={IO_LEVEL} + + LOGIC: + G1 = { G1_I } + G2ABAR = { G2ABAR_I } + G2BBAR = { G2BBAR_I } + A = { A_I } + B = { B_I } + C = { C_I } + ABAR = { ~A } + BBAR = { ~B } + CBAR = { ~C } + ENABLE = { ~G2ABAR & ~G2BBAR & G1 } + Y0 = { ~(ENABLE & CBAR & BBAR & ABAR) } + Y1 = { ~(ENABLE & CBAR & BBAR & A ) } + Y2 = { ~(ENABLE & CBAR & B & ABAR) } + Y3 = { ~(ENABLE & CBAR & B & A ) } + Y4 = { ~(ENABLE & C & BBAR & ABAR) } + Y5 = { ~(ENABLE & C & BBAR & A ) } + Y6 = { ~(ENABLE & C & B & ABAR) } + Y7 = { ~(ENABLE & C & B & A ) } * UAS138DLY PINDLY (8,0,7) DPWR DGND + Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 + ENABLE G1 G2ABAR G2BBAR A B C + Y0_O Y1_O Y2_O Y3_O Y4_O Y5_O Y6_O Y7_O + IO_AS00 + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + ABLE1 = { CHANGED(ENABLE,0) & CHANGED(G1,0) } + ABLE2 = { CHANGED(ENABLE,0) & (CHANGED(G2ABAR,0) | CHANGED(G2BBAR,0)) } + ADDR = { CHANGED(A,0) | CHANGED(B,0) | CHANGED(C,0) } + + PINDLY: + Y0_O Y1_O Y2_O Y3_O Y4_O Y5_O Y6_O Y7_O = { + CASE ( + ABLE2 & TRN_LH, DELAY(2NS,-1, 7.5NS), + ABLE2 & TRN_HL, DELAY(2NS,-1, 8.5NS), + ADDR & TRN_LH, DELAY(2NS,-1,10.0NS), + ADDR & TRN_HL, DELAY(2NS,-1, 9.5NS), + ABLE1 , DELAY(2NS,-1,10.0NS), + DELAY(2NS,-1,10.0NS) + ) + } * .ENDS * *$ *-------- * 74AS139 DECODER/DEMULTIPLEXER 2-4 LINE * * ALS/AS LOGIC CIRCUITS DATA BOOK, 1986, TI * JLS 8-1-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES * .SUBCKT 74AS139 GBAR_I A_I B_I Y0_O Y1_O Y2_O Y3_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UAS139LOG LOGICEXP (3,7) DPWR DGND + GBAR_I A_I B_I + GBAR A B + Y0 Y1 Y2 Y3 + D0_GATE IO_AS00 + IO_LEVEL={IO_LEVEL} + + LOGIC: + GBAR = { GBAR_I } + A = { A_I } + B = { B_I } + ABAR = { ~A } + BBAR = { ~B } + ENABLE = { ~GBAR } + Y0 = { ~(ENABLE & BBAR & ABAR ) } + Y1 = { ~(ENABLE & BBAR & A ) } + Y2 = { ~(ENABLE & B & ABAR ) } + Y3 = { ~(ENABLE & B & A ) } * UAS139DLY PINDLY (4,0,3) DPWR DGND + Y0 Y1 Y2 Y3 + GBAR A B + Y0_O Y1_O Y2_O Y3_O + IO_AS00 + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + ABLE = { CHANGED(GBAR,0) } + ADDR = { CHANGED(A,0) | CHANGED(B,0) } + + PINDLY: + Y0_O Y1_O Y2_O Y3_O = { + CASE ( + TRN_LH, DELAY(-1,5.5NS,-1), + ABLE & TRN_HL, DELAY(-1,5.0NS,-1), + ADDR & TRN_HL, DELAY(-1,6.0NS,-1), + DELAY(-1,6.0NS,-1) + ) + } * .ENDS * *$ *--------- * 74AS151 MULTIPLEXER/DATA SELECTOR 8-1 LINE * * ALS/AS LOGIC CIRCUITS DATA BOOK, 1986, TI * TC 08/21/92 REMODELED USING LOGICEXP, PINDLY, & CONSTRAINT DEVICES * .SUBCKT 74AS151 GBAR_I A_I B_I C_I D0_I D1_I D2_I D3_I D4_I D5_I D6_I D7_I + Y_O W_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UAS151LOG LOGICEXP(12,14) DPWR DGND + GBAR_I A_I B_I C_I D0_I D1_I D2_I D3_I D4_I D5_I D6_I D7_I + GBAR A B C D0 D1 D2 D3 D4 D5 D6 D7 W Y + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} + LOGIC: + GBAR = { GBAR_I } + A = { A_I } + B = { B_I } + C = { C_I } + D0 = { D0_I } + D1 = { D1_I } + D2 = { D2_I } + D3 = { D3_I } + D4 = { D4_I } + D5 = { D5_I } + D6 = { D6_I } + D7 = { D7_I } + IA = { ~A } + IB = { ~B } + IC = { ~C } + IG = { ~GBAR } + ID0 = { D0 & IA & IB & IC & IG } + ID1 = { D1 & A & IB & IC & IG } + ID2 = { D2 & IA & B & IC & IG } + ID3 = { D3 & A & B & IC & IG } + ID4 = { D4 & IA & IB & C & IG } + ID5 = { D5 & A & IB & C & IG } + ID6 = { D6 & IA & B & C & IG } + ID7 = { D7 & A & B & C & IG } + W = { ~(ID0 | ID1 | ID2 | ID3 | ID4 | ID5 | ID6 | ID7) } + Y = { ~W } * UAS151DLY PINDLY (2,0,12) DPWR DGND + W Y + GBAR A B C D0 D1 D2 D3 D4 D5 D6 D7 + W_O Y_O + IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + DATA = { CHANGED(D0,0) | CHANGED(D1,0) | CHANGED(D2,0) | CHANGED(D3,0) | + CHANGED(D4,0) | CHANGED(D5,0) | CHANGED(D6,0) | CHANGED(D7,0) } + SELECT = { CHANGED(A,0) | CHANGED(B,0) | CHANGED(C,0) } + ENABLE = { CHANGED(GBAR,0) } + PINDLY: + Y_O = { + CASE( + SELECT & TRN_HL, DELAY(4.5NS,-1,15NS), + SELECT & TRN_LH, DELAY(4.5NS,-1,14.5NS), + ENABLE & TRN_LH, DELAY(4.5NS,-1,14NS), + ENABLE & TRN_HL, DELAY(3NS,-1,11NS), + DATA & TRN_HL, DELAY(3NS,-1,11NS), + DATA & TRN_LH, DELAY(3NS,-1,10.5NS), + DELAY(5NS,-1,16NS) + ) + } + W_O = { + CASE( + SELECT, DELAY(4NS,-1,12NS), + ENABLE & TRN_HL, DELAY(3NS,-1,10NS), + DATA & TRN_LH, DELAY(2NS,-1,6.5NS), + ENABLE & TRN_LH, DELAY(1.5NS,-1,6NS), + DATA & TRN_HL, DELAY(1NS,-1,4.5NS), + DELAY(5NS,-1,13NS) + ) + } * .ENDS * *$ *--------- * 74AS153 DUAL 4-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS * * The ALS/AS Data Book, 1986, TI * JSW 8/12/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74AS153 G1BAR_I G2BAR_I A_I B_I 1C0_I 1C1_I 1C2_I 1C3_I + 2C0_I 2C1_I 2C2_I 2C3_I Y1_O Y2_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UAS153LOG LOGICEXP(12,14) DPWR DGND + G1BAR_I G2BAR_I A_I B_I 1C0_I 1C1_I 1C2_I 1C3_I 2C0_I 2C1_I 2C2_I 2C3_I + G1BAR G2BAR A B 1C0 1C1 1C2 1C3 2C0 2C1 2C2 2C3 Y1 Y2 + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} + LOGIC: + G1BAR = { G1BAR_I } + G2BAR = { G2BAR_I } + A = { A_I } + B = { B_I } + 1C0 = { 1C0_I } + 1C1 = { 1C1_I } + 1C2 = { 1C2_I } + 1C3 = { 1C3_I } + 2C0 = { 2C0_I } + 2C1 = { 2C1_I } + 2C2 = { 2C2_I } + 2C3 = { 2C3_I } + G1 = { ~G1BAR } + G2 = { ~G2BAR } + ABAR = { ~A } + BBAR = { ~B } + I0 = { G1 & BBAR & ABAR & 1C0 } + I1 = { G1 & BBAR & A & 1C1 } + I2 = { G1 & B & ABAR & 1C2 } + I3 = { G1 & B & A & 1C3 } + I4 = { G2 & BBAR & ABAR & 2C0 } + I5 = { G2 & BBAR & A & 2C1 } + I6 = { G2 & B & ABAR & 2C2 } + I7 = { G2 & B & A & 2C3 } + Y1 = { I0 | I1 | I2 | I3 } + Y2 = { I4 | I5 | I6 | I7 } * UAS153DLY PINDLY (2,0,12) DPWR DGND + Y1 Y2 + G1BAR G2BAR A B 1C0 1C1 1C2 1C3 2C0 2C1 2C2 2C3 + Y1_O Y2_O + IO_AS00 + MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + BOOLEAN: + DATA1 = { (CHANGED(1C0,0) | CHANGED(1C1,0) | CHANGED(1C2,0) | + CHANGED(1C3,0)) } + DATA2 = { (CHANGED(2C0,0) | CHANGED(2C1,0) | CHANGED(2C2,0) | + CHANGED(2C3,0)) } + SELECT = { CHANGED(A,0) | CHANGED(B,0) } + PINDLY: + Y1_O = { + CASE( + SELECT & TRN_LH, DELAY(3NS,-1,12.5NS), + CHANGED(G1BAR,0) & TRN_LH, DELAY(3NS,-1,11.5NS), + SELECT & TRN_HL, DELAY(3NS,-1,11NS), + CHANGED(G1BAR,0) & TRN_HL, DELAY(2NS,-1,9NS), + DATA1 & TRN_HL, DELAY(2NS,-1,8NS), + DATA1 & TRN_LH, DELAY(2NS,-1,7NS), + DELAY(4NS,-1,13NS) + ) + } + Y2_O = { + CASE( + SELECT & TRN_LH, DELAY(3NS,-1,12.5NS), + CHANGED(G2BAR,0) & TRN_LH, DELAY(3NS,-1,11.5NS), + SELECT & TRN_HL, DELAY(3NS,-1,11NS), + CHANGED(G2BAR,0) & TRN_HL, DELAY(2NS,-1,9NS), + DATA2 & TRN_HL, DELAY(2NS,-1,8NS), + DATA2 & TRN_LH, DELAY(2NS,-1,7NS), + DELAY(4NS,-1,13NS) + ) + } * .ENDS * *$ *--------- * 74AS157 QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS * * The ALS/AS Data Book, 1986, TI * JSW 8/25/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74AS157 GBAR_I 1A_I 1B_I 2A_I 2B_I 3A_I 3B_I 4A_I 4B_I SEL_I + Y1_O Y2_O Y3_O Y4_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UAS157LOG LOGICEXP(10,14) DPWR DGND + GBAR_I 1A_I 1B_I 2A_I 2B_I 3A_I 3B_I 4A_I 4B_I SEL_I + GBAR 1A 1B 2A 2B 3A 3B 4A 4B SEL Y1 Y2 Y3 Y4 + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} + LOGIC: + GBAR = { GBAR_I } + 1A = { 1A_I } + 1B = { 1B_I } + 2A = { 2A_I } + 2B = { 2B_I } + 3A = { 3A_I } + 3B = { 3B_I } + 4A = { 4A_I } + 4B = { 4B_I } + SEL = { SEL_I } + SELBAR = { ~SEL } + G = { ~GBAR } + Y1 = { (1A & SELBAR & G) | (1B & SEL & G) } + Y2 = { (2A & SELBAR & G) | (2B & SEL & G) } + Y3 = { (3A & SELBAR & G) | (3B & SEL & G) } + Y4 = { (4A & SELBAR & G) | (4B & SEL & G) } * UAS157DLY PINDLY (4,0,10) DPWR DGND + Y1 Y2 Y3 Y4 + GBAR 1A 1B 2A 2B 3A 3B 4A 4B SEL + Y1_O Y2_O Y3_O Y4_O + IO_AS00 + MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + BOOLEAN: + DATA = { CHANGED(1A,0) | CHANGED(1B,0) | CHANGED(2A,0) | CHANGED(2B,0) | + CHANGED(3A,0) | CHANGED(3B,0) | CHANGED(4A,0) | CHANGED(4B,0) } + SELECT = { CHANGED(SEL,0) } + ENABLE = { CHANGED(GBAR,0) } + PINDLY: + Y1_O Y2_O Y3_O Y4_O = { + CASE( + SELECT & TRN_LH, DELAY(2NS,-1,11NS), + ENABLE & TRN_LH, DELAY(2NS,-1,10.5NS), + SELECT & TRN_HL, DELAY(2NS,-1,10NS), + ENABLE & TRN_HL, DELAY(2NS,-1,7.5NS), + DATA & TRN_LH, DELAY(1NS,-1,6NS), + DATA & TRN_HL, DELAY(1NS,-1,5.5NS), + DELAY(3NS,-1,12NS) + ) + } * .ENDS * *$ *--------- * 74AS158 DUAL 4-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS * * The ALS/AS Data Book, 1986, TI * JSW 8/25/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74AS158 GBAR_I 1A_I 1B_I 2A_I 2B_I 3A_I 3B_I 4A_I 4B_I SEL_I + Y1_O Y2_O Y3_O Y4_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UAS158LOG LOGICEXP(10,14) DPWR DGND + GBAR_I 1A_I 1B_I 2A_I 2B_I 3A_I 3B_I 4A_I 4B_I SEL_I + GBAR 1A 1B 2A 2B 3A 3B 4A 4B SEL Y1 Y2 Y3 Y4 + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} + LOGIC: + GBAR = { GBAR_I } + 1A = { 1A_I } + 1B = { 1B_I } + 2A = { 2A_I } + 2B = { 2B_I } + 3A = { 3A_I } + 3B = { 3B_I } + 4A = { 4A_I } + 4B = { 4B_I } + SEL = { SEL_I } + SELBAR = { ~SEL } + G = { ~GBAR } + Y1 = { ~((1A & SELBAR & G) | (1B & SEL & G)) } + Y2 = { ~((2A & SELBAR & G) | (2B & SEL & G)) } + Y3 = { ~((3A & SELBAR & G) | (3B & SEL & G)) } + Y4 = { ~((4A & SELBAR & G) | (4B & SEL & G)) } * UAS158DLY PINDLY (4,0,10) DPWR DGND + Y1 Y2 Y3 Y4 + GBAR 1A 1B 2A 2B 3A 3B 4A 4B SEL + Y1_O Y2_O Y3_O Y4_O + IO_AS00 + MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + BOOLEAN: + DATA = { CHANGED(1A,0) | CHANGED(1B,0) | CHANGED(2A,0) | CHANGED(2B,0) | + CHANGED(3A,0) | CHANGED(3B,0) | CHANGED(4A,0) | CHANGED(4B,0) } + SELECT = { CHANGED(SEL,0) } + ENABLE = { CHANGED(GBAR,0) } + PINDLY: + Y1_O Y2_O Y3_O Y4_O = { + CASE( + SELECT & TRN_HL, DELAY(2NS,-1,10.5NS), + ENABLE & TRN_HL, DELAY(2NS,-1,10NS), + SELECT & TRN_LH, DELAY(2NS,-1,9.5NS), + ENABLE & TRN_LH, DELAY(2NS,-1,6.5NS), + DATA & TRN_LH, DELAY(1NS,-1,5NS), + DATA & TRN_HL, DELAY(1NS,-1,4.5NS), + DELAY(3NS,-1,11NS) + ) + } * .ENDS * *$ *--------- * 74AS160 Synchronous 4-bit Decade Counters with asynchronous clear * * ALS/AS LOGIC DATA BOOK, 1986, TI * JSW 7/1/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74AS160 CLK_I ENP_I ENT_I CLRBAR_I LOADBAR_I A_I B_I C_I D_I + QA_O QB_O QC_O QD_O RCO_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UAS160LOG LOGICEXP(13,15) DPWR DGND + CLK_I ENP_I ENT_I CLRBAR_I LOADBAR_I A_I B_I C_I D_I QA QB QC QD + CLK ENP ENT CLRBAR LOADBAR A B C D RCO DA DB DC DD EN + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} + LOGIC: + CLK = { CLK_I } ;Buffering + ENP = { ENP_I } + ENT = { ENT_I } + CLRBAR = { CLRBAR_I } + LOADBAR = { LOADBAR_I } + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + LOAD = { ~LOADBAR } ;Logic expressions + EN = { ENP & ENT & LOADBAR } + DA = { ((LOADBAR & QA) ^ EN) | (A & LOAD) } + DB = { (~(EN & QA) & LOADBAR & QB) | (~(LOADBAR & QB) & EN & QA + & ~QD) | (B & LOAD) } + DC = { ((LOADBAR & QC) ^ (EN & QA & QB)) | (C & LOAD) } + DD = { (~(EN & QA) & LOADBAR & QD) | (~(LOADBAR & QD) & EN & QC + & QB & QA) | (D & LOAD) } + RCO = { ENT & QA & QD } * UDFF DFF(4) DPWR DGND $D_HI CLRBAR CLK DA DB DC DD + QA QB QC QD QABAR QBBAR QCBAR QDBAR D0_EFF IO_AS00 * UAS160DLY PINDLY (5,0,10) DPWR DGND + RCO QA QB QC QD + CLK LOADBAR ENT CLRBAR ENP A B C D EN + RCO_O QA_O QB_O QC_O QD_O + IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + CLOCK = { CHANGED_LH(CLK,0) } + CNTENT = { CHANGED(ENT,0) } + CLEAR = { CHANGED_HL(CLRBAR,0) } + PINDLY: + QA_O QB_O QC_O QD_O = { + CASE( + CLOCK & TRN_LH, DELAY(1NS,-1,7NS), + CLOCK & TRN_HL, DELAY(2NS,-1,13NS), + CLEAR, DELAY(2NS,-1,13NS), + DELAY(2NS,-1,13NS) + ) + } + RCO_O = { + CASE( + CLOCK & TRN_HL, DELAY(2NS,-1,12.5NS), + CLOCK & LOADBAR=='1, DELAY(1NS,-1,8NS), + CLOCK & LOADBAR=='0, DELAY(3NS,-1,16.5NS), + CNTENT & TRN_HL, DELAY(1NS,-1,8.5NS), + CNTENT & TRN_LH, DELAY(1.5NS,-1,9NS), + CLEAR, DELAY(2NS,-1,12.5NS), + DELAY(2NS,-1,12.5NS) + ) + } + FREQ: + NODE = CLK + MAXFREQ = 75MEG + WIDTH: + NODE = CLK + MIN_LO = 6.7NS + MIN_HI = 6.7NS + WIDTH: + NODE = CLRBAR + MIN_LO = 8NS + SETUP_HOLD: + DATA(1) = LOADBAR + CLOCK LH = CLK + SETUPTIME = 8NS + WHEN = { CLRBAR!='0 } + SETUP_HOLD: + DATA(2) = ENP ENT + CLOCK LH = CLK + SETUPTIME = 8NS + WHEN = { CLRBAR!='0 & (LOADBAR!='0 ^ CHANGED(LOADBAR,0)) + & CHANGED(EN,8NS) } + SETUP_HOLD: + DATA(4) = A B C D + CLOCK LH = CLK + SETUPTIME = 8NS + WHEN = { (LOADBAR!='1 ^ CHANGED(LOADBAR,0)) & CLRBAR!='0 } + SETUP_HOLD: + DATA(1) = CLRBAR + CLOCK LH = CLK + RELEASETIME_LH = 8NS * .ENDS * *$ *--------- * 74AS161 Synchronous 4-bit Binary Counter with Direct Clear * * THE ALS/AS DATA BOOK, 1986, TI * tc 07/01/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74AS161 CLK_I ENP_I ENT_I CLRBAR_I LOADBAR_I A_I B_I C_I D_I + QA_O QB_O QC_O QD_O RCO_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 DFF(4) DPWR DGND $D_HI CLRBAR CLK + DA DB DC DD QA QB QC QD $D_NC $D_NC $D_NC $D_NC + D0_EFF IO_AS00 * UAS161LOG LOGICEXP(13,15) DPWR DGND + CLK_I ENP_I ENT_I CLRBAR_I LOADBAR_I A_I B_I C_I D_I QA QB QC QD + CLK ENP ENT CLRBAR LOADBAR A B C D RCO DA DB DC DD IEN + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} + LOGIC: + CLK = { CLK_I } + ENP = { ENP_I } + ENT = { ENT_I } + CLRBAR = { CLRBAR_I } + LOADBAR = { LOADBAR_I } + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + ILD = { ~LOADBAR } + IEN = { ENP & ENT & LOADBAR } + IA = { (LOADBAR & QA) ^ IEN } + IB = { (LOADBAR & QB) ^ (IEN & QA) } + IC = { (LOADBAR & QC) ^ (IEN & QA & QB) } + ID = { (LOADBAR & QD) ^ (IEN & QA & QB & QC) } + RCO = { ENT & QA & QB & QC & QD } + DA = { IA | (ILD & A) } + DB = { IB | (ILD & B) } + DC = { IC | (ILD & C) } + DD = { ID | (ILD & D) } * UAS161DLY PINDLY (5,0,10) DPWR DGND + RCO QA QB QC QD + CLK ENT CLRBAR LOADBAR ENP A B C D IEN + RCO_O QA_O QB_O QC_O QD_O + IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + CLOCK = { CHANGED_LH(CLK,0) } + CLEAR = { CHANGED_HL(CLRBAR,0) } + PINDLY: + QA_O QB_O QC_O QD_O = { + CASE( + CLOCK & TRN_LH, DELAY(1NS,-1,7NS), + CLOCK & TRN_HL, DELAY(2NS,-1,13NS), + DELAY(2NS,-1,13NS) + ) + } + RCO_O = { + CASE( + CLOCK & TRN_LH & LOADBAR=='1, DELAY(1NS,-1,8NS), + CHANGED(ENT,0) & TRN_HL, DELAY(1NS,-1,8.5NS), + CHANGED(ENT,0) & TRN_LH, DELAY(1.5NS,-1,9NS), + CLEAR, DELAY(2NS,-1,12.5NS), + CLOCK & TRN_HL, DELAY(2NS,-1,12.5NS), + CLOCK & TRN_LH & LOADBAR=='0, DELAY(3NS,-1,16.5NS), + DELAY(3NS,-1,16.5NS) + ) + } + FREQ: + NODE = CLK + MAXFREQ = 75MEG + WIDTH: + NODE = CLK + MIN_LO = 6.7NS + MIN_HI = 6.7NS + WIDTH: + NODE = CLRBAR + MIN_LO = 8NS + SETUP_HOLD: + DATA(4) = A B C D + CLOCK LH = CLK + SETUPTIME = 8NS + WHEN = { (LOADBAR!='1 ^ CHANGED(LOADBAR,0)) & CLRBAR!='0 } + SETUP_HOLD: + DATA(2) = ENP ENT + CLOCK LH = CLK + SETUPTIME = 8NS + WHEN = { (LOADBAR!='0 ^ CHANGED(LOADBAR,0)) & CLRBAR!='0 & + CHANGED(IEN,8NS) } + SETUP_HOLD: + DATA(1) = LOADBAR + CLOCK LH = CLK + SETUPTIME = 8NS + WHEN = { CLRBAR!='0 } + SETUP_HOLD: + DATA(1) = CLRBAR + CLOCK LH = CLK + RELEASETIME_LH = 8NS * .ENDS * *$ *--------- * 74AS162 Synchronous 4-bit Decade Counters with asynchronous clear * * ALS/AS LOGIC CIRCUITS DATA BOOK, 1986, TI * JSW 7/1/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74AS162 CLK_I ENP_I ENT_I CLRBAR_I LOADBAR_I A_I B_I C_I D_I + QA_O QB_O QC_O QD_O RCO_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UAS162LOG LOGICEXP(13,15) DPWR DGND + CLK_I ENP_I ENT_I CLRBAR_I LOADBAR_I A_I B_I C_I D_I QA QB QC QD + CLK ENP ENT CLRBAR LOADBAR A B C D RCO DA DB DC DD EN + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} + LOGIC: + CLK = { CLK_I } ;Buffering + ENP = { ENP_I } + ENT = { ENT_I } + CLRBAR = { CLRBAR_I } + LOADBAR = { LOADBAR_I } + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + LOADB = { LOADBAR & CLRBAR } ;Logic expressions + LOAD = { ~LOADBAR & CLRBAR } + EN = { ENP & ENT & LOADBAR & CLRBAR } + DA = { ((LOADB & QA) ^ EN) | (A & LOAD) } + DB = { (~(EN & QA) & LOADB & QB) | (~(LOADB & QB) & EN & QA + & ~QD) | (B & LOAD) } + DC = { ((LOADB & QC) ^ (EN & QA & QB)) | (C & LOAD) } + DD = { (~(EN & QA) & LOADB & QD) | (~(LOADB & QD) & EN & QC + & QB & QA) | (D & LOAD) } + RCO = { ENT & QA & QD } * UDFF DFF(4) DPWR DGND $D_HI $D_HI CLK DA DB DC DD + QA QB QC QD QABAR QBBAR QCBAR QDBAR D0_EFF IO_AS00 * UAS162DLY PINDLY (5,0,10) DPWR DGND + RCO QA QB QC QD + CLK LOADBAR ENT ENP CLRBAR A B C D EN + RCO_O QA_O QB_O QC_O QD_O + IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + CLOCK = { CHANGED_LH(CLK,0) } + CNTENT = { CHANGED(ENT,0) } + PINDLY: + QA_O QB_O QC_O QD_O = { + CASE( + CLOCK & TRN_LH, DELAY(1NS,-1,7NS), + CLOCK & TRN_HL, DELAY(2NS,-1,13NS), + DELAY(2NS,-1,13NS) + ) + } + RCO_O = { + CASE( + CLOCK & TRN_LH & LOADBAR=='1, DELAY(1NS,-1,8NS), + CNTENT & TRN_HL, DELAY(1NS,-1,8.5NS), + CNTENT & TRN_LH, DELAY(1.5NS,-1,9NS), + CLOCK & TRN_HL, DELAY(2NS,-1,12.5NS), + CLOCK & TRN_LH & LOADBAR=='0, DELAY(3NS,-1,16.5NS), + DELAY(3NS,-1,16.5NS) + ) + } + BOOLEAN: + NOTCLEAR = { CLRBAR!='0 ^ CHANGED(CLRBAR,0) } + FREQ: + NODE = CLK + MAXFREQ = 75MEG + WIDTH: + NODE = CLK + MIN_LO = 6.7NS + MIN_HI = 6.7NS + WIDTH: + NODE = CLRBAR + MIN_LO = 8NS + SETUP_HOLD: + DATA(2) = ENP ENT + CLOCK LH = CLK + SETUPTIME = 8NS + WHEN = { CHANGED(EN,8NS) & (LOADBAR!='0 ^ CHANGED(LOADBAR,0)) & NOTCLEAR } + SETUP_HOLD: + DATA(1) = LOADBAR + CLOCK LH = CLK + SETUPTIME = 8NS + WHEN = { NOTCLEAR } + SETUP_HOLD: + DATA(4) = A B C D + CLOCK LH = CLK + SETUPTIME = 8NS + WHEN = { (LOADBAR!='1 ^ CHANGED(LOADBAR,0)) & NOTCLEAR } + SETUP_HOLD: + DATA(1) = CLRBAR + CLOCK LH = CLK + SETUPTIME_HI = 9NS + SETUPTIME_LO = 12NS * .ENDS * *$ *--------- * 74AS163 Synchronous 4-bit Binary Counter with Direct Clear * * THE ALS/AS DATA BOOK, 1986, TI * tc 07/08/92 Remodeled using LOGICEXP, PINDLY & CONSTRAINT Devices * .SUBCKT 74AS163 CLK_I ENP_I ENT_I CLRBAR_I LOADBAR_I A_I B_I C_I D_I + QA_O QB_O QC_O QD_O RCO_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 DFF(4) DPWR DGND $D_HI $D_HI CLK + DA DB DC DD QA QB QC QD $D_NC $D_NC $D_NC $D_NC + D0_EFF IO_AS00 * UAS163LOG LOGICEXP(13,15) DPWR DGND + CLK_I ENP_I ENT_I CLRBAR_I LOADBAR_I A_I B_I C_I D_I QA QB QC QD + CLK ENP ENT CLRBAR LOADBAR A B C D RCO DA DB DC DD IEN + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} + LOGIC: + CLK = { CLK_I } + ENP = { ENP_I } + ENT = { ENT_I } + CLRBAR = { CLRBAR_I } + LOADBAR = { LOADBAR_I } + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + ILD = { ~LOADBAR & CLRBAR } + IEN = { (ENP & ENT & LOADBAR) & CLRBAR } + ILC = { LOADBAR & CLRBAR } + IA = { (ILC & QA) ^ IEN } + IB = { (ILC & QB) ^ (IEN & QA) } + IC = { (ILC & QC) ^ (IEN & QA & QB) } + ID = { (ILC & QD) ^ (IEN & QA & QB & QC) } + RCO = { ENT & QA & QB & QC & QD } + DA = { IA | (ILD & A) } + DB = { IB | (ILD & B) } + DC = { IC | (ILD & C) } + DD = { ID | (ILD & D) } * UAS163DLY PINDLY (5,0,10) DPWR DGND + RCO QA QB QC QD + CLK ENT LOADBAR ENP CLRBAR A B C D IEN + RCO_O QA_O QB_O QC_O QD_O + IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + CLOCK = { CHANGED_LH(CLK,0) } + PINDLY: + QA_O QB_O QC_O QD_O = { + CASE( + CLOCK & TRN_LH, DELAY(1NS,-1,7NS), + CLOCK & TRN_HL, DELAY(2NS,-1,13NS), + DELAY(2NS,-1,13NS) + ) + } + RCO_O = { + CASE( + CLOCK & TRN_LH & LOADBAR=='1, DELAY(1NS,-1,8NS), + CHANGED(ENT,0) & TRN_HL, DELAY(1NS,-1,8.5NS), + CHANGED(ENT,0) & TRN_LH, DELAY(1.5NS,-1,9NS), + CLOCK & TRN_HL, DELAY(2NS,-1,12.5NS), + CLOCK & TRN_LH & LOADBAR=='0, DELAY(3NS,-1,16.5NS), + DELAY(3NS,-1,16.5NS) + ) + } + BOOLEAN: + NOTCLEAR = { CLRBAR!='0 ^ CHANGED(CLRBAR,0) } + FREQ: + NODE = CLK + MAXFREQ = 75MEG + WIDTH: + NODE = CLK + MIN_LO = 6.7NS + MIN_HI = 6.7NS + SETUP_HOLD: + DATA(4) = A B C D + CLOCK LH = CLK + SETUPTIME = 8NS + WHEN = { (LOADBAR!='1 ^ CHANGED(LOADBAR,0)) & NOTCLEAR } + SETUP_HOLD: + DATA(2) = ENP ENT + CLOCK LH = CLK + SETUPTIME = 8NS + WHEN = { (LOADBAR!='0 ^ CHANGED(LOADBAR,0)) & NOTCLEAR & CHANGED(IEN,8NS) } + SETUP_HOLD: + DATA(1) = LOADBAR + CLOCK LH = CLK + SETUPTIME = 8NS + WHEN = { NOTCLEAR } + SETUP_HOLD: + DATA(1) = CLRBAR + CLOCK LH = CLK + SETUPTIME_LO = 12NS + SETUPTIME_HI = 9NS * .ENDS * *$ *--------- * 74AS168 Synchronous 4-bit Up/Down Decade Counters * * The ALS/AS Data Book, 1986, TI * JSW 7/27/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74AS168 CLK_I U/DBAR_I ENPBAR_I ENTBAR_I LOADBAR_I + A_I B_I C_I D_I QA_O QB_O QC_O QD_O RCOBAR_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UAS168LOG LOGICEXP(17,15) DPWR DGND + CLK_I U/DBAR_I ENPBAR_I ENTBAR_I LOADBAR_I A_I B_I C_I D_I + QA QB QC QD QABAR QBBAR QCBAR QDBAR + CLK U/DBAR ENPBAR ENTBAR LOADBAR A B C D RCOBAR DA DB DC DD EN + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} + LOGIC: + CLK = { CLK_I } + ENPBAR = { ENPBAR_I } + ENTBAR = { ENTBAR_I } + U/DBAR = { U/DBAR_I } + LOADBAR = { LOADBAR_I } + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + UD = { ~U/DBAR } + LOAD = { ~LOADBAR } + EN = { ~ENTBAR & ~ENPBAR & LOADBAR } + IA4 = { ~((QABAR & U/DBAR) | (QA & UD)) } + IB4 = { ~((QBBAR & U/DBAR) | (QB & UD)) } + IC4 = { ~((QCBAR & U/DBAR) | (QC & UD)) } + ID4 = { ~((QDBAR & U/DBAR) | (QD & UD)) } + IB5 = { ~(U/DBAR & ID4) } + IC5 = { ~(QCBAR & UD & QDBAR) } + IA1 = { A & LOAD } + IA2 = { EN ^ ( LOADBAR & QA) } + IB1 = { B & LOAD } + IB2 = { ~(EN & IA4) & LOADBAR & QB } + IB3 = { IA4 & EN & IC5 & IB5 & QBBAR } + IC1 = { C & LOAD } + IC2 = { ~(EN & IA4 & IB4) & LOADBAR & QC } + IC3 = { ~(QC & LOADBAR) & EN & IA4 & IB4 & IC5 } + ID1 = { D & LOAD } + ID2 = { ~(EN & IA4) & LOADBAR & QD } + ID3 = { ~(QD & LOADBAR) & EN & IA4 & IB4 & IC4 } + DA = { IA1 | IA2 } + DB = { IB1 | IB2 | IB3 } + DC = { IC1 | IC2 | IC3 } + DD = { ID1 | ID2 | ID3 } + RCOBAR = { ~((U/DBAR & IA4 & ID4 & ~ENTBAR) | (~ENTBAR & UD & + IA4 & IB4 & IC4 & ID4)) } * UDFF DFF(4) DPWR DGND $D_HI $D_HI CLK DA DB DC DD + QA QB QC QD QABAR QBBAR QCBAR QDBAR D0_EFF IO_AS00 * UAS168DLY PINDLY (5,0,10) DPWR DGND + RCOBAR QA QB QC QD + CLK ENPBAR ENTBAR U/DBAR LOADBAR A B C D EN + RCOBAR_O QA_O QB_O QC_O QD_O + IO_AS00 + MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + BOOLEAN: + CLOCK = { CHANGED_LH(CLK,0) } + CNTENT = { CHANGED(ENTBAR,0) } + PINDLY: + RCOBAR_O = { + CASE( + CNTENT, DELAY(1.5NS,-1,9NS), + CHANGED(U/DBAR,0) & TRN_LH, DELAY(2NS,-1,12NS), + CHANGED(U/DBAR,0) & TRN_HL, DELAY(2NS,-1,13NS), + CLOCK & TRN_HL, DELAY(2NS,-1,13NS), + CLOCK & TRN_LH, DELAY(3NS,-1,16.5NS), + DELAY(3NS,-1,16NS) + ) + } + QA_O QB_O QC_O QD_O = { + CASE( + CLOCK & TRN_LH, DELAY(1NS,-1,7NS), + CLOCK & TRN_HL, DELAY(2NS,-1,13NS), + DELAY(2NS,-1,13NS) + ) + } + FREQ: + NODE = CLK + MAXFREQ = 75MEG + WIDTH: + NODE = CLK + MIN_LOW = 6.7NS + MIN_HIGH = 6.7NS + SETUP_HOLD: + DATA(4) = A B C D + CLOCK LH = CLK + SETUPTIME = 8NS + WHEN = { LOADBAR!='1 ^ CHANGED(LOADBAR,0) } + SETUP_HOLD: + DATA(2) = ENPBAR ENTBAR + CLOCK LH = CLK + SETUPTIME = 8NS + WHEN = { CHANGED(EN,8NS) & (LOADBAR!='0 ^ CHANGED(LOADBAR,0)) } + SETUP_HOLD: + DATA(1) = U/DBAR + CLOCK LH = CLK + SETUPTIME = 8NS + WHEN = { EN!='0 ^ CHANGED(EN,0) } + SETUP_HOLD: + DATA(1) = LOADBAR + CLOCK LH = CLK + SETUPTIME = 8NS * .ENDS * *$ *--------- * 74AS169 Synchronous 4-Bit Up/Down Binary Counter * * ALS/AS LOGIC DATA BOOK, 1986, TI * tc 07/21/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74AS169 CLK_I U/DBAR_I ENPBAR_I ENTBAR_I LOADBAR_I A_I B_I C_I D_I + QA_O QB_O QC_O QD_O RCOBAR_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 DFF(4) DPWR DGND $D_HI $D_HI CLK + DA DB DC DD QA QB QC QD QABAR QBBAR QCBAR QDBAR + D0_EFF IO_AS00 * UAS169LOG LOGICEXP(17,15) DPWR DGND + CLK_I U/DBAR_I ENPBAR_I ENTBAR_I LOADBAR_I A_I B_I C_I D_I QA QB QC QD + QABAR QBBAR QCBAR QDBAR + CLK U/DBAR ENPBAR ENTBAR LOADBAR A B C D DA DB DC DD RCOBAR IEN + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} + LOGIC: + CLK = { CLK_I } + U/DBAR = { U/DBAR_I } + ENPBAR = { ENPBAR_I } + ENTBAR = { ENTBAR_I } + LOADBAR = { LOADBAR_I } + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + ILD = { ~LOADBAR } + IEN = { ~(ENPBAR | ENTBAR | ILD) } + UP = { U/DBAR } + DN = { ~U/DBAR } + IA1 = { (QA & LOADBAR) ^ IEN } + IA2 = { ~((UP & QABAR) | (DN & QA)) } + IB1 = { (QB & LOADBAR) ^ (IEN & IA2) } + IB2 = { ~((UP & QBBAR) | (DN & QB)) } + IC1 = { (QC & LOADBAR) ^ (IEN & IA2 & IB2) } + IC2 = { ~((UP & QCBAR) | (DN & QC)) } + ID1 = { (QD & LOADBAR) ^ (IEN & IA2 & IB2 & IC2) } + ID2 = { ~((UP & QDBAR) | (DN & QD)) } + DA = { IA1 | (ILD & A) } + DB = { IB1 | (ILD & B) } + DC = { IC1 | (ILD & C) } + DD = { ID1 | (ILD & D) } + IR1 = { UP & ~ENTBAR & IA2 & IB2 & IC2 & ID2 } + IR2 = { DN & ~ENTBAR & IA2 & IB2 & IC2 & ID2 } + RCOBAR = { ~(IR1 | IR2) } * UAS169DLY PINDLY (5,0,10) DPWR DGND + QA QB QC QD RCOBAR + CLK ENTBAR U/DBAR ENPBAR LOADBAR A B C D IEN + QA_O QB_O QC_O QD_O RCOBAR_O + IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + CLOCK = { CHANGED_LH(CLK,0) } + PINDLY: + QA_O QB_O QC_O QD_O = { + CASE( + CLOCK & TRN_LH, DELAY(1NS,-1,7NS), + DELAY(2NS,-1,13NS) + ) + } + RCOBAR_O = { + CASE( + CHANGED(ENTBAR,0), DELAY(1.5NS,-1,9NS), + CHANGED(U/DBAR,0) & TRN_LH, DELAY(2NS,-1,12NS), + CHANGED(U/DBAR,0) & TRN_HL, DELAY(2NS,-1,13NS), + CLOCK & TRN_HL, DELAY(2NS,-1,13NS), + CLOCK & TRN_LH, DELAY(3NS,-1,16.5NS), + DELAY(3NS,-1,16.5NS) + ) + } + BOOLEAN: + NOTLOADING = { LOADBAR!='0 ^ CHANGED(LOADBAR,0) } + ENABLE = { (ENPBAR!='1 ^ CHANGED(ENPBAR,0)) & + (ENTBAR!='1 ^ CHANGED(ENTBAR,0)) } + FREQ: + NODE = CLK + MAXFREQ = 75MEG + WIDTH: + NODE = CLK + MIN_LO = 6.7NS + MIN_HI = 6.7NS + SETUP_HOLD: + DATA(4) = A B C D + CLOCK LH = CLK + SETUPTIME = 8NS + WHEN = { LOADBAR!='1 | CHANGED_LH(LOADBAR,0) } + SETUP_HOLD: + DATA(2) = ENPBAR ENTBAR + CLOCK LH = CLK + SETUPTIME = 8NS + WHEN = { NOTLOADING & CHANGED(IEN,8NS) } + SETUP_HOLD: + DATA(1) = LOADBAR + CLOCK LH = CLK + SETUPTIME = 8NS + SETUP_HOLD: + DATA(1) = U/DBAR + CLOCK LH = CLK + SETUPTIME = 8NS + WHEN = { NOTLOADING & ENABLE } * .ENDS * *$ *---------- * 74AS174 HEX D-TYPE FLIP-FLOPS WITH CLEAR * * The ALS/AS Logic Data Book, 1986, TI * tvh 06/27/89 Update interface and model names * .subckt 74AS174 CLRBAR CLK D1 D2 D3 D4 D5 D6 Q1 Q2 Q3 Q4 Q5 Q6 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UD dff(6) DPWR DGND + $D_HI CLRBAR CLK + D1 D2 D3 D4 D5 D6 + Q1 Q2 Q3 Q4 Q5 Q6 + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D_AS174 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_AS174 ueff ( + TWCLKLMN=6NS TWCLKHMN=4NS + TWPCLMN=5NS TSUDCLKMN=4NS + TSUPCCLKHMN=6NS THDCLKMN=1NS + TPPCQHLMN=5NS TPPCQHLMX=14NS + TPCLKQLHMN=3.5NS TPCLKQLHMX=8NS + TPCLKQHLMN=4.5NS TPCLKQHLMX=10NS + ) *$ *---------- * 74AS175A QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR * * The ALS/AS Logic Data Book, 1986, TI * tvh 06/27/89 Update interface and model names * .subckt 74AS175A CLRBAR CLK D1 D2 D3 D4 Q1 Q2 Q3 Q4 Q1BAR Q2BAR Q3BAR Q4BAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UD dff(4) DPWR DGND + $D_HI CLRBAR CLK + D1 D2 D3 D4 + Q1 Q2 Q3 Q4 Q1BAR Q2BAR Q3BAR Q4BAR + D_AS175A IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_AS175A ueff ( + TWCLKLMN=5NS TWCLKHMN=4NS + TWPCLMN=5NS TSUDCLKMN=3NS + TSUPCCLKHMN=6NS THDCLKMN=1NS + TPPCQLHMN=4NS TPPCQLHMX=9NS + TPPCQHLMN=4.5NS TPPCQHLMX=13NS + TPCLKQLHMN=4NS TPCLKQLHMX=7.5NS + TPCLKQHLMN=4NS TPCLKQHLMX=10NS + ) *$ *--------- * 74AS181A ALU / FUNCTION GENERATOR * * ALS/AS LOGIC CIRCUITS DATA BOOK, 1986, TI * JLS 9-4-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES .SUBCKT 74AS181A A0BAR_I A1BAR_I A2BAR_I A3BAR_I B0BAR_I B1BAR_I B2BAR_I + B3BAR_I S0_I S1_I S2_I S3_I M_I CN_I F0BAR_O F1BAR_O F2BAR_O F3BAR_O + AEQUALB_O PBAR_O GBAR_O CN+4_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 UAS181ALOG LOGICEXP (14,22) DPWR DGND + A0BAR_I A1BAR_I A2BAR_I A3BAR_I B0BAR_I B1BAR_I B2BAR_I B3BAR_I + S0_I S1_I S2_I S3_I M_I CN_I + A0BAR A1BAR A2BAR A3BAR B0BAR B1BAR B2BAR B3BAR + S0 S1 S2 S3 M CN + F0BAR F1BAR F2BAR F3BAR AEQUALB PBAR GBAR CN+4 + D0_GATE IO_AS00 + IO_LEVEL={IO_LEVEL} + + LOGIC: + A0BAR = { A0BAR_I } + A1BAR = { A1BAR_I } + A2BAR = { A2BAR_I } + A3BAR = { A3BAR_I } + B0BAR = { B0BAR_I } + B1BAR = { B1BAR_I } + B2BAR = { B2BAR_I } + B3BAR = { B3BAR_I } + S0 = { S0_I } + S1 = { S1_I } + S2 = { S2_I } + S3 = { S3_I } + M = { M_I } + CN = { CN_I } + + TOP3 = { ~( (A3BAR & B3BAR & S3) | (A3BAR & ~B3BAR & S2) ) } + BOT3 = { ~( (~B3BAR & S1) | A3BAR | (B3BAR & S0) ) } + TOP2 = { ~( (A2BAR & B2BAR & S3) | (A2BAR & ~B2BAR & S2) ) } + BOT2 = { ~( (~B2BAR & S1) | A2BAR | (B2BAR & S0) ) } + TOP1 = { ~( (A1BAR & B1BAR & S3) | (A1BAR & ~B1BAR & S2) ) } + BOT1 = { ~( (~B1BAR & S1) | A1BAR | (B1BAR & S0) ) } + TOP0 = { ~( (A0BAR & B0BAR & S3) | (A0BAR & ~B0BAR & S2) ) } + BOT0 = { ~( (~B0BAR & S1) | A0BAR | (B0BAR & S0) ) } + MBAR = { ~M } + + F3BAR = { (TOP3 ^ BOT3) ^ ~( ( CN & MBAR & TOP2 & TOP1 & TOP0) | + (BOT0 & MBAR & TOP2 & TOP1) | + (BOT1 & MBAR & TOP2) | + (BOT2 & MBAR) ) } + F2BAR = { (TOP2 ^ BOT2) ^ ~( ( CN & MBAR & TOP1 & TOP0) | + (BOT0 & MBAR & TOP1) | + (BOT1 & MBAR) ) } + F1BAR = { (TOP1 ^ BOT1) ^ ~( ( CN & MBAR & TOP0) | + (BOT0 & MBAR) ) } + F0BAR = { (TOP0 ^ BOT0) ^ ~( CN & MBAR) } + AEQUALB = { F3BAR & F2BAR & F1BAR & F0BAR } + PBAR = { ~( TOP3 & TOP2 & TOP1 & TOP0) } + GBAR = { ~( (BOT0 & TOP3 & TOP2 & TOP1) | + (BOT1 & TOP3 & TOP2) | + (BOT2 & TOP3) | + BOT3 ) } + CN+4 = { ~GBAR | (~PBAR & CN) } UAS181ADLY PINDLY (7,0,14) DPWR DGND + F0BAR F1BAR F2BAR F3BAR PBAR GBAR CN+4 + A0BAR A1BAR A2BAR A3BAR B0BAR B1BAR B2BAR B3BAR S0 S1 S2 S3 M CN + F0BAR_O F1BAR_O F2BAR_O F3BAR_O PBAR_O GBAR_O CN+4_O + IO_AS00 + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + CARRY = { CHANGED(CN,0) } + OPER = { CHANGED(A3BAR,0) | CHANGED(B3BAR,0) | + CHANGED(A2BAR,0) | CHANGED(B2BAR,0) | + CHANGED(A1BAR,0) | CHANGED(B1BAR,0) | + CHANGED(A0BAR,0) | CHANGED(B0BAR,0) } + NOTM = { M=='0 } + SUM = { OPER & NOTM & S0=='1 & S1=='0 & S2=='0 & S3=='1 } + DIF = { OPER & NOTM & S0=='0 & S1=='1 & S2=='1 & S3=='0 } + + PINDLY: + F0BAR_O F1BAR_O F2BAR_O F3BAR_O = { + CASE ( + NOTM & CARRY, DELAY(3NS,6NS, 9NS), + SUM , DELAY(2NS,5NS, 8NS), + DIF , DELAY(2NS,6NS,10NS), + DELAY(2NS,6NS,11NS) + ) + } + PBAR_O = { + CASE ( + SUM, DELAY(2NS,6NS, 8NS), + DELAY(2NS,6NS,10NS) + ) + } + GBAR_O = { + CASE ( + SUM, DELAY(2NS,5NS,7NS), + DELAY(2NS,6NS,9NS) + ) + } + CN+4_O = { + CASE ( + CARRY, DELAY(2NS,7NS, 9NS), + SUM , DELAY(2NS,8NS,12NS), + DELAY(2NS,8NS,16NS) + ) + } UAS181ADLY_OC PINDLY (1,0,13) DPWR DGND + AEQUALB + A0BAR A1BAR A2BAR A3BAR B0BAR B1BAR B2BAR B3BAR S0 S1 S2 S3 M + AEQUALB_O + IO_AS00_OC + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + PINDLY: + AEQUALB_O = { DELAY(4NS,14NS,21NS) } .ENDS *$ *--------- * 74AS181B ALU / FUNCTION GENERATOR * * ALS/AS LOGIC CIRCUITS DATA BOOK, 1986, TI * JLS 9-4-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES .SUBCKT 74AS181B A0BAR_I A1BAR_I A2BAR_I A3BAR_I B0BAR_I B1BAR_I B2BAR_I + B3BAR_I S0_I S1_I S2_I S3_I M_I CN_I F0BAR_O F1BAR_O F2BAR_O F3BAR_O + AEQUALB_O PBAR_O GBAR_O CN+4_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 UAS181BLOG LOGICEXP (14,22) DPWR DGND + A0BAR_I A1BAR_I A2BAR_I A3BAR_I B0BAR_I B1BAR_I B2BAR_I B3BAR_I + S0_I S1_I S2_I S3_I M_I CN_I + A0BAR A1BAR A2BAR A3BAR B0BAR B1BAR B2BAR B3BAR + S0 S1 S2 S3 M CN + F0BAR F1BAR F2BAR F3BAR AEQUALB PBAR GBAR CN+4 + D0_GATE IO_AS00 + IO_LEVEL={IO_LEVEL} + + LOGIC: + A0BAR = { A0BAR_I } + A1BAR = { A1BAR_I } + A2BAR = { A2BAR_I } + A3BAR = { A3BAR_I } + B0BAR = { B0BAR_I } + B1BAR = { B1BAR_I } + B2BAR = { B2BAR_I } + B3BAR = { B3BAR_I } + S0 = { S0_I } + S1 = { S1_I } + S2 = { S2_I } + S3 = { S3_I } + M = { M_I } + CN = { CN_I } + + TOP3 = { ~( (A3BAR & B3BAR & S3) | (A3BAR & ~B3BAR & S2) ) } + BOT3 = { ~( (~B3BAR & S1) | A3BAR | (B3BAR & S0) ) } + TOP2 = { ~( (A2BAR & B2BAR & S3) | (A2BAR & ~B2BAR & S2) ) } + BOT2 = { ~( (~B2BAR & S1) | A2BAR | (B2BAR & S0) ) } + TOP1 = { ~( (A1BAR & B1BAR & S3) | (A1BAR & ~B1BAR & S2) ) } + BOT1 = { ~( (~B1BAR & S1) | A1BAR | (B1BAR & S0) ) } + TOP0 = { ~( (A0BAR & B0BAR & S3) | (A0BAR & ~B0BAR & S2) ) } + BOT0 = { ~( (~B0BAR & S1) | A0BAR | (B0BAR & S0) ) } + MBAR = { ~M } + + F3BAR = { (TOP3 ^ BOT3) ^ ~( ( CN & MBAR & TOP2 & TOP1 & TOP0) | + (BOT0 & MBAR & TOP2 & TOP1) | + (BOT1 & MBAR & TOP2) | + (BOT2 & MBAR) ) } + F2BAR = { (TOP2 ^ BOT2) ^ ~( ( CN & MBAR & TOP1 & TOP0) | + (BOT0 & MBAR & TOP1) | + (BOT1 & MBAR) ) } + F1BAR = { (TOP1 ^ BOT1) ^ ~( ( CN & MBAR & TOP0) | + (BOT0 & MBAR) ) } + F0BAR = { (TOP0 ^ BOT0) ^ ~( CN & MBAR) } + AEQUALB = { F3BAR & F2BAR & F1BAR & F0BAR } + PBAR = { ~( TOP3 & TOP2 & TOP1 & TOP0) } + GBAR = { ~( (BOT0 & TOP3 & TOP2 & TOP1) | + (BOT1 & TOP3 & TOP2) | + (BOT2 & TOP3) | + BOT3 ) } + CN+4 = { ~GBAR | (~PBAR & CN) } UAS181BDLY PINDLY (7,0,14) DPWR DGND + F0BAR F1BAR F2BAR F3BAR PBAR GBAR CN+4 + A0BAR A1BAR A2BAR A3BAR B0BAR B1BAR B2BAR B3BAR S0 S1 S2 S3 M CN + F0BAR_O F1BAR_O F2BAR_O F3BAR_O PBAR_O GBAR_O CN+4_O + IO_AS00 + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + CARRY = { CHANGED(CN,0) } + OPER3 = { CHANGED(A3BAR,0) | CHANGED(B3BAR,0) } + OPER2 = { CHANGED(A2BAR,0) | CHANGED(B2BAR,0) } + OPER1 = { CHANGED(A1BAR,0) | CHANGED(B1BAR,0) } + OPER0 = { CHANGED(A0BAR,0) | CHANGED(B0BAR,0) } + OPER = { OPER3 | OPER2 | OPER1 | OPER0 } + NOTM = { M=='0 } + SUM = { NOTM & S0=='1 & S1=='0 & S2=='0 & S3=='1 } + DIF = { NOTM & S0=='0 & S1=='1 & S2=='1 & S3=='0 } + + PINDLY: + F3BAR_O = { + CASE ( + NOTM & CARRY & TRN_LH, DELAY(3.0NS,-1, 9.0NS), + NOTM & CARRY & TRN_HL, DELAY(3.0NS,-1, 7.5NS), + SUM & OPER3 & TRN_LH, DELAY(3.0NS,-1, 9.5NS), + SUM & OPER3 & TRN_HL, DELAY(3.0NS,-1, 7.5NS), + DIF & OPER3 & TRN_LH, DELAY(3.0NS,-1,10.5NS), + DIF & OPER3 & TRN_HL, DELAY(3.0NS,-1, 9.5NS), + SUM & OPER & TRN_LH, DELAY(3.0NS,-1,12.0NS), + SUM & OPER & TRN_HL, DELAY(3.0NS,-1,11.5NS), + DIF & OPER & TRN_LH, DELAY(3.0NS,-1,14.5NS), + DIF & OPER & TRN_HL, DELAY(3.0NS,-1,12.5NS), + OPER & M=='1 & TRN_LH, DELAY(3.0NS,-1,11.0NS), + OPER & M=='1 & TRN_HL, DELAY(3.0NS,-1, 9.5NS), + DELAY(3.0NS,-1,14.5NS) + ) + } + F2BAR_O = { + CASE ( + NOTM & CARRY & TRN_LH, DELAY(3.0NS,-1, 9.0NS), + NOTM & CARRY & TRN_HL, DELAY(3.0NS,-1, 7.5NS), + SUM & OPER2 & TRN_LH, DELAY(3.0NS,-1, 9.5NS), + SUM & OPER2 & TRN_HL, DELAY(3.0NS,-1, 7.5NS), + DIF & OPER2 & TRN_LH, DELAY(3.0NS,-1,10.5NS), + DIF & OPER2 & TRN_HL, DELAY(3.0NS,-1, 9.5NS), + SUM & OPER & TRN_LH, DELAY(3.0NS,-1,12.0NS), + SUM & OPER & TRN_HL, DELAY(3.0NS,-1,11.5NS), + DIF & OPER & TRN_LH, DELAY(3.0NS,-1,14.5NS), + DIF & OPER & TRN_HL, DELAY(3.0NS,-1,12.5NS), + OPER & M=='1 & TRN_LH, DELAY(3.0NS,-1,11.0NS), + OPER & M=='1 & TRN_HL, DELAY(3.0NS,-1, 9.5NS), + DELAY(3.0NS,-1,14.5NS) + ) + } + F1BAR_O = { + CASE ( + NOTM & CARRY & TRN_LH, DELAY(3.0NS,-1, 9.0NS), + NOTM & CARRY & TRN_HL, DELAY(3.0NS,-1, 7.5NS), + SUM & OPER1 & TRN_LH, DELAY(3.0NS,-1, 9.5NS), + SUM & OPER1 & TRN_HL, DELAY(3.0NS,-1, 7.5NS), + DIF & OPER1 & TRN_LH, DELAY(3.0NS,-1,10.5NS), + DIF & OPER1 & TRN_HL, DELAY(3.0NS,-1, 9.5NS), + SUM & OPER & TRN_LH, DELAY(3.0NS,-1,12.0NS), + SUM & OPER & TRN_HL, DELAY(3.0NS,-1,11.5NS), + DIF & OPER & TRN_LH, DELAY(3.0NS,-1,14.5NS), + DIF & OPER & TRN_HL, DELAY(3.0NS,-1,12.5NS), + OPER & M=='1 & TRN_LH, DELAY(3.0NS,-1,11.0NS), + OPER & M=='1 & TRN_HL, DELAY(3.0NS,-1, 9.5NS), + DELAY(3.0NS,-1,14.5NS) + ) + } + F0BAR_O = { + CASE ( + NOTM & CARRY & TRN_LH, DELAY(3.0NS,-1, 9.0NS), + NOTM & CARRY & TRN_HL, DELAY(3.0NS,-1, 7.5NS), + SUM & OPER0 & TRN_LH, DELAY(3.0NS,-1, 9.5NS), + SUM & OPER0 & TRN_HL, DELAY(3.0NS,-1, 7.5NS), + DIF & OPER0 & TRN_LH, DELAY(3.0NS,-1,10.5NS), + DIF & OPER0 & TRN_HL, DELAY(3.0NS,-1, 9.5NS), + SUM & OPER & TRN_LH, DELAY(3.0NS,-1,12.0NS), + SUM & OPER & TRN_HL, DELAY(3.0NS,-1,11.5NS), + DIF & OPER & TRN_LH, DELAY(3.0NS,-1,14.5NS), + DIF & OPER & TRN_HL, DELAY(3.0NS,-1,12.5NS), + OPER & M=='1 & TRN_LH, DELAY(3.0NS,-1,11.0NS), + OPER & M=='1 & TRN_HL, DELAY(3.0NS,-1, 9.5NS), + DELAY(3.0NS,-1,14.5NS) + ) + } + PBAR_O = { + CASE ( + SUM & TRN_LH, DELAY(3.0NS,-1,7.5NS), + SUM & TRN_HL, DELAY(2.0NS,-1,6.0NS), + TRN_LH, DELAY(3.0NS,-1,9.0NS), + TRN_HL, DELAY(3.0NS,-1,8.0NS), + DELAY(3.0NS,-1,9.0NS) + ) + } + GBAR_O = { + CASE ( + SUM & TRN_LH, DELAY(3.0NS,-1,8.0NS), + SUM & TRN_HL, DELAY(2.0NS,-1,6.0NS), + TRN_LH, DELAY(3.0NS,-1,9.5NS), + TRN_HL, DELAY(2.0NS,-1,7.0NS), + DELAY(3.0NS,-1,9.5NS) + ) + } + CN+4_O = { + CASE ( + CARRY & TRN_LH, DELAY(3.0NS,-1, 8.5NS), + CARRY & TRN_HL, DELAY(2.0NS,-1, 6.5NS), + SUM , DELAY(5.0NS,-1,12.0NS), + DIF & TRN_LH, DELAY(5.0NS,-1,13.0NS), + DIF & TRN_HL, DELAY(5.0NS,-1,12.5NS), + DELAY(5.0NS,-1,13.0NS) + ) + } UAS181BDLY_OC PINDLY (1,0,13) DPWR DGND + AEQUALB + A0BAR A1BAR A2BAR A3BAR B0BAR B1BAR B2BAR B3BAR S0 S1 S2 S3 M + AEQUALB_O + IO_AS00_OC + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + OPER = { CHANGED(A3BAR,0) | CHANGED(B3BAR,0) | + CHANGED(A2BAR,0) | CHANGED(B2BAR,0) | + CHANGED(A1BAR,0) | CHANGED(B1BAR,0) | + CHANGED(A0BAR,0) | CHANGED(B0BAR,0) } + NOTM = { M=='0 } + DIF = { OPER & NOTM & S0=='0 & S1=='1 & S2=='1 & S3=='0 } + + PINDLY: + AEQUALB_O = { + CASE ( + DIF & TRN_LH, DELAY(4NS,-1,17NS), + DIF & TRN_HL, DELAY(5NS,-1,15NS), + DELAY(5NS,-1,17NS) + ) + } .ENDS *$ *--------- * 74AS182 LOOK-AHEAD CARRY GENERATOR * * ALS/AS LOGIC CIRCUITS DATA BOOK, 1986, TI * JLS 9-17-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES * .SUBCKT 74AS182 G3BAR_I G2BAR_I G1BAR_I G0BAR_I + P3BAR_I P2BAR_I P1BAR_I P0BAR_I CN_I GBAR_O PBAR_O CN+X_O CN+Y_O CN+Z_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UAS182LOG LOGICEXP (9,13) DPWR DGND + G3BAR_I G2BAR_I G1BAR_I G0BAR_I P3BAR_I P2BAR_I P1BAR_I P0BAR_I CN_I + G3BAR G2BAR G1BAR G0BAR P3BAR P2BAR P1BAR P0BAR + GBAR PBAR CN+X CN+Y CN+Z + D0_GATE IO_AS00 + IO_LEVEL={IO_LEVEL} + + LOGIC: + G3BAR = { G3BAR_I } + G2BAR = { G2BAR_I } + G1BAR = { G1BAR_I } + G0BAR = { G0BAR_I } + P3BAR = { P3BAR_I } + P2BAR = { P2BAR_I } + P1BAR = { P1BAR_I } + P0BAR = { P0BAR_I } + CN = { CN_I } + CNBAR = { ~CN } + PBAR = { P0BAR | P1BAR | P2BAR | P3BAR } + GBAR = { ( G0BAR & G1BAR & G2BAR & G3BAR) | + (P1BAR & G1BAR & G2BAR & G3BAR) | + (P2BAR & G2BAR & G3BAR) | + (P3BAR & G3BAR) } + CN+Z = { ~((CNBAR & G0BAR & G1BAR & G2BAR) | + (P0BAR & G0BAR & G1BAR & G2BAR) | + (P1BAR & G1BAR & G2BAR) | + (P2BAR & G2BAR)) } + CN+Y = { ~((CNBAR & G0BAR & G1BAR) | + (P0BAR & G0BAR & G1BAR) | + (P1BAR & G1BAR)) } + CN+X = { ~((CNBAR & G0BAR) | + (P0BAR & G0BAR)) } * UAS182DLY PINDLY (5,0,8) DPWR DGND + GBAR PBAR CN+X CN+Y CN+Z + G3BAR G2BAR G1BAR G0BAR P3BAR P2BAR P1BAR P0BAR + GBAR_O PBAR_O CN+X_O CN+Y_O CN+Z_O + IO_AS00 + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + GORP = { CHANGED(P3BAR,0) | CHANGED(P2BAR,0) | CHANGED(P1BAR,0) | + CHANGED(G3BAR,0) | CHANGED(G2BAR,0) | CHANGED(G1BAR,0) | + CHANGED(G0BAR,0) } + + PINDLY: + GBAR_O = { + CASE ( + GORP & TRN_LH, DELAY(-1,6NS,-1), + DELAY(-1,5NS,-1) + ) + } + PBAR_O CN+X_O CN+Y_O CN+Z_O = { DELAY(-1,5NS,-1) } * .ENDS * *$ *--------- * 74AS194 4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS * * THE ALS/AS LOGIC CIRCUITS DATA BOOK, 1986, TI * NH 7/7/92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74AS194 CLK_I CLRBAR_I S1_I S0_I SL_I SR_I A_I B_I C_I D_I + QA_O QB_O QC_O QD_O + OPTIONAL: DPWR = $G_DPWR DGND = $G_DGND + PARAMS: MNTYMXDLY = 0 IO_LEVEL = 0 * UAS194LOG LOGICEXP(14,19) DPWR DGND + CLK_I CLRBAR_I S1_I S0_I SL_I SR_I A_I B_I C_I D_I QA QB QC QD + CLK CLRBAR S1 S0 SL SR A B C D KA KB KC KD JA JB JC JD CLOCK + D0_GATE IO_AS00 IO_LEVEL = {IO_LEVEL} + + LOGIC: * * INTERMEDIATE TERM + LOAD = { S1_I & S0_I } + SRIGHT = { ~S1_I & S0_I } + SLEFT = { S1_I & ~S0_I } + HOLD = { ~S1_I & ~S0_I } * * OUTPUT ASSIGNMENT * + CLK = { CLK_I } + CLRBAR = { CLRBAR_I } + S1 = { S1_I } + S0 = { S0_I } + SL = { SL_I } + SR = { SR_I } + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + + KA = { ~( (SR & SRIGHT) | (LOAD & A) | (SLEFT & QB) | (HOLD & QA) ) } + KB = { ~( (QA & SRIGHT) | (LOAD & B) | (SLEFT & QC) | (HOLD & QB) ) } + KC = { ~( (QB & SRIGHT) | (LOAD & C) | (SLEFT & QD) | (HOLD & QC) ) } + KD = { ~( (QC & SRIGHT) | (LOAD & D) | (SLEFT & SL) | (HOLD & QD) ) } + JA = { ~KA } + JB = { ~KB } + JC = { ~KC } + JD = { ~KD } + CLOCK = { ~CLK } * U1 JKFF(4) DPWR DGND $D_HI CLRBAR CLOCK JA JB JC JD KA KB KC KD + QA QB QC QD $D_NC $D_NC $D-NC $D_NC + D0_EFF IO_AS00 * UAS194DLY PINDLY (4,0,10) DPWR DGND + QA QB QC QD + CLK CLRBAR S0 S1 SL SR A B C D + QA_O QB_O QC_O QD_O + IO_AS00 + MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + + PINDLY: + QA_O QB_O QC_O QD_O = { + CASE( + CHANGED_LH(CLK,0), DELAY(3NS,-1,7NS), + CHANGED_HL(CLRBAR,0), DELAY(4NS,-1,12NS), + DELAY(5NS,8NS,13NS) ;DEFAULT + ) + } + + BOOLEAN: + NOT_CLEAR = { CLRBAR!='0 } + + FREQ: + NODE = CLK + MAXFREQ = 80MEG + + WIDTH: + NODE = CLK + MIN_HI = 2NS + MIN_LO = 6NS + + WIDTH: + NODE = CLRBAR + MIN_LO = 4NS + + SETUP_HOLD: + DATA(2) S0 S1 + CLOCK LH = CLK + SETUPTIME = 8NS + WHEN = { NOT_CLEAR } + + SETUP_HOLD: + DATA(1) SL + CLOCK LH = CLK + SETUPTIME = 3NS + WHEN = { NOT_CLEAR & (S1!='0 ^ CHANGED(S1,0)) & (S0!='1 ^ CHANGED(S0,0)) } + + SETUP_HOLD: + DATA(1) SR + CLOCK LH = CLK + SETUPTIME = 3NS + WHEN = { NOT_CLEAR & (S1!='1 ^ CHANGED(S1,0)) & (S0!='0 ^ CHANGED(S0,0)) } + + SETUP_HOLD: + DATA(4) A B C D + CLOCK LH = CLK + SETUPTIME = 3NS + WHEN = { NOT_CLEAR & (S1!='0 ^ CHANGED(S1,0)) & (S0!='0 ^ CHANGED(S0,0)) } + + SETUP_HOLD: + DATA(1) CLRBAR + CLOCK LH = CLK + RELEASETIME_LH = 6NS * .ENDS * *$ *--------- * 74AS195 4-BIT PARALLEL-ACCESS SHIFT REGISTERS * * THE ALS/AS LOGIC CIRCUITS DATA BOOK, 1986, TI * NH 7/6/92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74AS195 CLK_I SH/LDBAR_I CLRBAR_I J_I KBAR_I A_I B_I C_I D_I + QA_O QB_O QC_O QD_O QDBAR_O + OPTIONAL: DPWR = $G_DPWR DGND = $G_DGND + PARAMS: MNTYMXDLY = 0 IO_LEVEL = 0 * UAS195LOG LOGICEXP(13,18) DPWR DGND + CLK_I SH/LDBAR_I CLRBAR_I J_I KBAR_I A_I B_I C_I D_I QA QB QC QABAR + CLK SH/LDBAR CLRBAR J KBAR A B C D KA KB KC KD JA JB JC JD CLKBAR + D0_GATE IO_AS00 IO_LEVEL = {IO_LEVEL} + + LOGIC: + CLK = { CLK_I } + SH/LDBAR = { SH/LDBAR_I } + CLRBAR = { CLRBAR_I } + J = { J_I } + KBAR = { KBAR_I } + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + * INTERMEDIATE TERM + LOAD = { ~SH/LDBAR } + + KA = { ~((QABAR & J & SH/LDBAR) | (SH/LDBAR & KBAR & QA) | (LOAD & A)) } + KB = { ~( (QA & SH/LDBAR) | (LOAD & B) ) } + KC = { ~( (QB & SH/LDBAR) | (LOAD & C) ) } + KD = { ~( (QC & SH/LDBAR) | (LOAD & D) ) } + JA = { ~KA } + JB = { ~KB } + JC = { ~KC } + JD = { ~KD } + CLKBAR = { ~CLK } * U1 JKFF(4) DPWR DGND $D_HI CLRBAR CLKBAR JA JB JC JD KA KB KC KD + QA QB QC QD QABAR $D_NC $D_NC QDBAR + D0_EFF IO_AS00 * UAS195DLY PINDLY (5,0,9) DPWR DGND + QA QB QC QD QDBAR + CLK CLRBAR SH/LDBAR J KBAR A B C D + QA_O QB_O QC_O QD_O QDBAR_O + IO_AS00 + MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + + PINDLY: + QA_O QB_O QC_O QD_O = { + CASE( + CHANGED_LH(CLK,0) & TRN_LH, DELAY(3NS,-1,8.5NS), + CHANGED_LH(CLK,0) & TRN_HL, DELAY(2.5NS,-1,10.5NS), + CHANGED_HL(CLRBAR,0) & TRN_HL, DELAY(5NS,-1,11.5NS), + DELAY(6NS,8NS,12NS) ;DEFAULT + ) + } + QDBAR_O = { + CASE( + CHANGED_HL(CLRBAR,0) & TRN_LH, DELAY(4NS,-1,8NS), + CHANGED_LH(CLK,0) & TRN_LH, DELAY(3NS,-1,8.5NS), + CHANGED_LH(CLK,0) & TRN_HL, DELAY(2.5NS,-1,10.5NS), + DELAY(5NS,7NS,11NS) ;DEFAULT + ) + } + + BOOLEAN: + NOT_CLEAR = { CLRBAR!='0 } + + FREQ: + NODE = CLK + MAXFREQ = 70MEG + + WIDTH: + NODE = CLK + MIN_HI = 4NS + + WIDTH: + NODE = CLRBAR + MIN_LO = 4NS + + SETUP_HOLD: + DATA(1) SH/LDBAR + CLOCK LH = CLK + SETUPTIME = 8NS + WHEN = { NOT_CLEAR } + + SETUP_HOLD: + DATA(1) CLRBAR + CLOCK LH = CLK + RELEASETIME_LH = 6NS + + SETUP_HOLD: ;SHIFT MODE + DATA(2) J KBAR ;WHEN SH/LDBAR = 1 OR + CLOCK LH = CLK ;AT THE TRANSITION FROM H TO L + SETUPTIME = 3.5NS + HOLDTIME = 0.5NS + WHEN = { NOT_CLEAR & (SH/LDBAR!='0 ^ CHANGED(SH/LDBAR,0)) } + + SETUP_HOLD: ;LOAD MODE + DATA(4) A B C D ;WHEN SH/LDBAR = 0 OR + CLOCK LH = CLK ;AT THE TRANSITION FROM L TO H + SETUPTIME = 3.5NS + HOLDTIME = 0.5NS + WHEN = { NOT_CLEAR & (SH/LDBAR!='1 ^ CHANGED(SH/LDBAR,0)) } * .ENDS * *$ *---------- * 74AS230 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS * * The ALS/AS Logic Data Book, 1986, TI * tvh 06/30/89 Update interface and model names * .subckt 74AS230 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 1GBAR 2GBAR 1Y1 1Y2 1Y3 1Y4 + 2Y1 2Y2 2Y3 2Y4 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UA inva(2) DPWR DGND + 1GBAR 2GBAR G1 G2 + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} U1 inv3a(4) DPWR DGND + 1A1 1A2 1A3 1A4 G1 1Y1 1Y2 1Y3 1Y4 + D_AS230_1 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 buf3a(4) DPWR DGND + 2A1 2A2 2A3 2A4 G2 2Y1 2Y2 2Y3 2Y4 + D_AS230_2 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_AS230_1 utgate ( + tplhmn=2ns tplhmx=6.5ns + tphlmn=2ns tphlmx=5.7ns + tpzhmn=2ns tpzhmx=6.4ns + tpzlmn=2ns tpzlmx=8.5ns + tphzmn=2ns tphzmx=5ns + tplzmn=2ns tplzmx=9.5ns + ) .model D_AS230_2 utgate ( + tplhmn=2ns tplhmx=6.5ns + tphlmn=2ns tphlmx=5.7ns + tpzhmn=3ns tpzhmx=6ns + tpzlmn=3ns tpzlmx=9ns + tphzmn=3ns tphzmx=6ns + tplzmn=3ns tplzmx=7ns + ) *$ *---------- * 74AS231 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS * * The ALS/AS Logic Data Book, 1986, TI * tvh 06/30/89 Update interface and model names * .subckt 74AS231 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 G1BAR G2 1Y1 1Y2 1Y3 1Y4 2Y1 + 2Y2 2Y3 2Y4 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UA inv DPWR DGND + G1BAR G1 + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} U1 inv3a(4) DPWR DGND + 1A1 1A2 1A3 1A4 G1 1Y1 1Y2 1Y3 1Y4 + D_AS231_1 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 inv3a(4) DPWR DGND + 2A1 2A2 2A3 2A4 G2 2Y1 2Y2 2Y3 2Y4 + D_AS231_2 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_AS231_1 utgate ( + tplhmn=2ns tplhmx=6.5ns + tphlmn=2ns tphlmx=5.7ns + tpzhmn=2ns tpzhmx=6.4ns + tpzlmn=2ns tpzlmx=8.5ns + tphzmn=2ns tphzmx=5ns + tplzmn=2ns tplzmx=9.5ns + ) .model D_AS231_2 utgate ( + tplhmn=2ns tplhmx=6.5ns + tphlmn=2ns tphlmx=5.7ns + tpzhmn=3ns tpzhmx=6ns + tpzlmn=3ns tpzlmx=9ns + tphzmn=3ns tphzmx=6ns + tplzmn=3ns tplzmx=7ns + ) * *$ *---------- * 74AS240 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS * * The ALS/AS Logic Data Book, 1986, TI * tvh 06/30/89 Update interface and model names * .subckt 74AS240 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 G1BAR G2BAR 1Y1 1Y2 1Y3 1Y4 + 2Y1 2Y2 2Y3 2Y4 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UAB inva(2) DPWR DGND + G1BAR G2BAR G1 G2 + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} U1 inv3a(4) DPWR DGND + 1A1 1A2 1A3 1A4 G1 1Y1 1Y2 1Y3 1Y4 + D_AS240 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 inv3a(4) DPWR DGND + 2A1 2A2 2A3 2A4 G2 2Y1 2Y2 2Y3 2Y4 + D_AS240 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_AS240 utgate ( + tplhmn=2ns tplhmx=6.5ns + tphlmn=2ns tphlmx=5.7ns + tpzhmn=2ns tpzhmx=6.4ns + tpzlmn=2ns tpzlmx=9ns + tphzmn=2ns tphzmx=5ns + tplzmn=2ns tplzmx=9.5ns + ) *$ *--------- * 74AS241 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS * * The ALS/AS Logic Data Book, 1986, TI * tvh 06/30/89 Update interface and model names * jgt 09/08/92 Bug Fix: changed inverters to Buffers * .subckt 74AS241 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 G1BAR G2 1Y1 1Y2 1Y3 1Y4 2Y1 + 2Y2 2Y3 2Y4 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UA inv DPWR DGND + G1BAR G1 + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} U1 buf3a(4) DPWR DGND + 1A1 1A2 1A3 1A4 G1 1Y1 1Y2 1Y3 1Y4 + D_AS241_1 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 buf3a(4) DPWR DGND + 2A1 2A2 2A3 2A4 G2 2Y1 2Y2 2Y3 2Y4 + D_AS241_2 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_AS241_1 utgate ( + tplhmn=2ns tplhmx=6.2ns + tphlmn=2ns tphlmx=6.2ns + tpzhmn=2ns tpzhmx=9ns + tpzlmn=2ns tpzlmx=7.5ns + tphzmn=2ns tphzmx=6ns + tplzmn=2ns tplzmx=9ns + ) .model D_AS241_2 utgate ( + tplhmn=2ns tplhmx=6.2ns + tphlmn=2ns tphlmx=6.2ns + tpzhmn=3ns tpzhmx=10.5ns + tpzlmn=3ns tpzlmx=8.5ns + tphzmn=3ns tphzmx=7ns + tplzmn=3ns tplzmx=12ns + ) * *$ *---------- * 74AS242 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS * * The ALS/AS Logic Data Book, 1986, TI * tvh 06/30/89 Update interface and model names * .subckt 74AS242 A1 A2 A3 A4 GABBAR GBA B1 B2 B3 B4 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UA inv DPWR DGND + GABBAR GAB + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} U1 inv3a(4) DPWR DGND + A1 A2 A3 A4 GAB B1 B2 B3 B4 + D_AS242_1 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 inv3a(4) DPWR DGND + B1 B2 B3 B4 GBA A1 A2 A3 A4 + D_AS242_2 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_AS242_1 utgate ( + tplhmn=2ns tplhmx=6.5ns + tphlmn=2ns tphlmx=5.7ns + tpzhmn=2ns tpzhmx=5.5ns + tpzlmn=2ns tpzlmx=7.5ns + tphzmn=2ns tphzmx=6.5ns + tplzmn=2ns tplzmx=9.5ns + ) .model D_AS242_2 utgate ( + tplhmn=2ns tplhmx=6.5ns + tphlmn=2ns tphlmx=5.7ns + tpzhmn=3ns tpzhmx=6ns + tpzlmn=3ns tpzlmx=8ns + tphzmn=3ns tphzmx=6ns + tplzmn=3ns tplzmx=10.5ns + ) *$ *---------- * 74AS243 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS * * The ALS/AS Logic Data Book, 1986, TI * tvh 06/30/89 Update interface and model names * .subckt 74AS243 A1 A2 A3 A4 GABBAR GBA B1 B2 B3 B4 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UA inv DPWR DGND + GABBAR GAB + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} U1 buf3a(4) DPWR DGND + A1 A2 A3 A4 GAB B1 B2 B3 B4 + D_AS243_1 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 buf3a(4) DPWR DGND + B1 B2 B3 B4 GBA A1 A2 A3 A4 + D_AS243_2 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_AS243_1 utgate ( + tplhmn=3ns tplhmx=7.5ns + tphlmn=3ns tphlmx=6.5ns + tpzhmn=2ns tpzhmx=9ns + tpzlmn=2ns tpzlmx=7.5ns + tphzmn=2ns tphzmx=6.5ns + tplzmn=2ns tplzmx=9ns + ) .model D_AS243_2 utgate ( + tplhmn=3ns tplhmx=7.5ns + tphlmn=3ns tphlmx=6.5ns + tpzhmn=3ns tpzhmx=10.5ns + tpzlmn=3ns tpzlmx=8.5ns + tphzmn=3ns tphzmx=7ns + tplzmn=3ns tplzmx=11ns + ) *$ *---------- * 74AS244 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS * * The ALS/AS Logic Data Book, 1986, TI * tvh 06/30/89 Update interface and model names * .subckt 74AS244 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 G1BAR G2BAR 1Y1 1Y2 1Y3 1Y4 + 2Y1 2Y2 2Y3 2Y4 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UAB inva(2) DPWR DGND + G1BAR G2BAR G1 G2 + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} U1 buf3a(4) DPWR DGND + 1A1 1A2 1A3 1A4 G1 1Y1 1Y2 1Y3 1Y4 + D_AS244 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 buf3a(4) DPWR DGND + 2A1 2A2 2A3 2A4 G2 2Y1 2Y2 2Y3 2Y4 + D_AS244 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_AS244 utgate ( + tplhmn=2ns tplhmx=6.2ns + tphlmn=2ns tphlmx=6.2ns + tpzhmn=2ns tpzhmx=9ns + tpzlmn=2ns tpzlmx=7.5ns + tphzmn=2ns tphzmx=6ns + tplzmn=2ns tplzmx=9ns + ) *$ *---------- * 74AS245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS * * ALS/AS LOGIC CIRCUITS DATA BOOK, 1986, TI * JLS 9-2-92 UPDATE TIMING * .SUBCKT 74AS245 DIR_I GBAR_I + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 BUFA(2) DPWR DGND + DIR_I GBAR_I + DIR GBAR + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} U2 INV DPWR DGND + DIR DIRBAR + D0_GATE IO_AS00 U3 NORA(2,2) DPWR DGND + DIRBAR GBAR DIR GBAR + ENABLEAB ENABLEBA + D0_GATE IO_AS00 * U4 BUF3A(8) DPWR DGND + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + ENABLEAB + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + D_AS245 IO_AS00 + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U5 BUF3A(8) DPWR DGND + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + ENABLEBA + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + D_AS245 IO_AS00 + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} * .MODEL D_AS245 UTGATE ( + TPLHMN=2.0NS TPLHMX=7.5NS + TPHLMN=2.0NS TPHLMX=7.0NS + TPZHMN=2.0NS TPZHMX=9.0NS + TPZLMN=2.0NS TPZLMX=8.5NS + TPHZMN=2.0NS TPHZMX=5.5NS + TPLZMN=2.0NS TPLZMX=9.5NS + ) * .ENDS * *$ *------------------------------------------------------------------------- * 74AS250 MULTIPLEXER/DATA GENERATOR 16-1 LINE WITH 3-STATE OUTPUTS * * ALS/AS LOGIC CIRCUITS DATA BOOK, 1986, TI * tc 08/13/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74AS250 GBAR_I A_I B_I C_I D_I E0_I E1_I E2_I E3_I E4_I E5_I E6_I + E7_I E8_I E9_I E10_I E11_I E12_I E13_I E14_I E15_I W_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UAS250LOG LOGICEXP(21,22) DPWR DGND + GBAR_I A_I B_I C_I D_I E0_I E1_I E2_I E3_I E4_I E5_I E6_I E7_I E8_I E9_I + E10_I E11_I E12_I E13_I E14_I E15_I + GBAR A B C D E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 W + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} + LOGIC: + GBAR = { GBAR_I } + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + E0 = { E0_I } + E1 = { E1_I } + E2 = { E2_I } + E3 = { E3_I } + E4 = { E4_I } + E5 = { E5_I } + E6 = { E6_I } + E7 = { E7_I } + E8 = { E8_I } + E9 = { E9_I } + E10 = { E10_I } + E11 = { E11_I } + E12 = { E12_I } + E13 = { E13_I } + E14 = { E14_I } + E15 = { E15_I } + IA = { ~A } + IB = { ~B } + IC = { ~C } + ID = { ~D } + IE0 = { E0 & IA & IB & IC & ID } + IE1 = { E1 & A & IB & IC & ID } + IE2 = { E2 & IA & B & IC & ID } + IE3 = { E3 & A & B & IC & ID } + IE4 = { E4 & IA & IB & C & ID } + IE5 = { E5 & A & IB & C & ID } + IE6 = { E6 & IA & B & C & ID } + IE7 = { E7 & A & B & C & ID } + IE8 = { E8 & IA & IB & IC & D } + IE9 = { E9 & A & IB & IC & D } + IE10 = { E10 & IA & B & IC & D } + IE11 = { E11 & A & B & IC & D } + IE12 = { E12 & IA & IB & C & D } + IE13 = { E13 & A & IB & C & D } + IE14 = { E14 & IA & B & C & D } + IE15 = { E15 & A & B & C & D } + W = { ~(IE0 | IE1 | IE2 | IE3 | IE4 | IE5 | IE6 | IE7 | IE8 | + IE9 | IE10 | IE11 | IE12 | IE13 | IE14 | IE15) } * UAS250DLY PINDLY (1,1,20) DPWR DGND + W + GBAR + A B C D E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 + W_O + IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + DATA = { CHANGED(E0,0) | CHANGED(E1,0) | CHANGED(E2,0) | CHANGED(E3,0) | + CHANGED(E4,0) | CHANGED(E5,0) | CHANGED(E6,0) | CHANGED(E7,0) | + CHANGED(E8,0) | CHANGED(E9,0) | CHANGED(E10,0) | CHANGED(E11,0) | + CHANGED(E12,0) | CHANGED(E13,0) | CHANGED(E14,0) | CHANGED(E15,0) } + SELECT = { CHANGED(A,0) | CHANGED(B,0) | CHANGED(C,0) | CHANGED(D,0) } + TRISTATE: + ENABLE LO GBAR + W_O = { + CASE( + TRN_ZL, DELAY(4NS,-1,20NS), + SELECT & TRN_LH, DELAY(4NS,-1,13NS), + SELECT & TRN_HL, DELAY(4NS,-1,10NS), + DATA & TRN_LH, DELAY(3NS,-1,8NS), + TRN_ZH, DELAY(2NS,-1,7NS), + TRN_HZ, DELAY(2NS,-1,6NS), + TRN_LZ, DELAY(2NS,-1,6NS), + DATA & TRN_HL, DELAY(2NS,-1,6NS), + DELAY(5NS,-1,21NS) + ) + } * .ENDS * *$ *--------- * 74AS251 MULTIPLEXER/DATA SELECTOR 8-1 LINE WITH 3-STATE OUTPUTS * * ALS/AS LOGIC CIRCUITS DATA BOOK, 1986, TI * TC 08/24/92 REMODELED USING LOGICEXP, PINDLY, & CONSTRAINT DEVICES * .SUBCKT 74AS251 GBAR_I A_I B_I C_I D0_I D1_I D2_I D3_I D4_I D5_I D6_I D7_I + Y_O W_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UAS251LOG LOGICEXP(12,14) DPWR DGND + GBAR_I A_I B_I C_I D0_I D1_I D2_I D3_I D4_I D5_I D6_I D7_I + GBAR A B C D0 D1 D2 D3 D4 D5 D6 D7 W Y + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} + LOGIC: + GBAR = { GBAR_I } + A = { A_I } + B = { B_I } + C = { C_I } + D0 = { D0_I } + D1 = { D1_I } + D2 = { D2_I } + D3 = { D3_I } + D4 = { D4_I } + D5 = { D5_I } + D6 = { D6_I } + D7 = { D7_I } + IA = { ~A } + IB = { ~B } + IC = { ~C } + ID0 = { D0 & IA & IB & IC } + ID1 = { D1 & A & IB & IC } + ID2 = { D2 & IA & B & IC } + ID3 = { D3 & A & B & IC } + ID4 = { D4 & IA & IB & C } + ID5 = { D5 & A & IB & C } + ID6 = { D6 & IA & B & C } + ID7 = { D7 & A & B & C } + W = { ~(ID0 | ID1 | ID2 | ID3 | ID4 | ID5 | ID6 | ID7) } + Y = { ~W } * UAS251DLY PINDLY (2,1,11) DPWR DGND + W Y + GBAR + A B C D0 D1 D2 D3 D4 D5 D6 D7 + W_O Y_O + IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + DATA = { CHANGED(D0,0) | CHANGED(D1,0) | CHANGED(D2,0) | CHANGED(D3,0) | + CHANGED(D4,0) | CHANGED(D5,0) | CHANGED(D6,0) | CHANGED(D7,0) } + SELECT = { CHANGED(A,0) | CHANGED(B,0) | CHANGED(C,0) } + TRISTATE: + ENABLE LO GBAR + Y_O = { + CASE( + TRN_ZL, DELAY(-1,6NS,-1), + TRN_ZH, DELAY(-1,5NS,-1), + SELECT, DELAY(-1,5NS,-1), + DATA & TRN_HL, DELAY(-1,4NS,-1), + TRN_LZ, DELAY(-1,4NS,-1), + TRN_HZ, DELAY(-1,3NS,-1), + DATA & TRN_LH, DELAY(-1,3NS,-1), + DELAY(-1,7NS,-1) + ) + } + W_O = { + CASE( + TRN_ZL, DELAY(-1,6NS,-1), + TRN_ZH, DELAY(-1,5NS,-1), + SELECT, DELAY(-1,4.5NS,-1), + TRN_LZ, DELAY(-1,4NS,-1), + TRN_HZ, DELAY(-1,3NS,-1), + DATA & TRN_LH, DELAY(-1,3NS,-1), + DATA & TRN_HL, DELAY(-1,2.5NS,-1), + DELAY(-1,7NS,-1) + ) + } * .ENDS * *$ *--------- * 74AS253 DUAL 1-OF-4 DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS * * The ALS/AS Data Book, 1986, TI * JSW 8/24/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74AS253 G1BAR_I G2BAR_I A_I B_I 1C0_I 1C1_I 1C2_I 1C3_I + 2C0_I 2C1_I 2C2_I 2C3_I Y1_O Y2_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UAS253LOG LOGICEXP(12,14) DPWR DGND + G1BAR_I G2BAR_I A_I B_I 1C0_I 1C1_I 1C2_I 1C3_I 2C0_I 2C1_I 2C2_I 2C3_I + G1BAR G2BAR A B 1C0 1C1 1C2 1C3 2C0 2C1 2C2 2C3 Y1 Y2 + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} + LOGIC: + G1BAR = { G1BAR_I } + G2BAR = { G2BAR_I } + A = { A_I } + B = { B_I } + 1C0 = { 1C0_I } + 1C1 = { 1C1_I } + 1C2 = { 1C2_I } + 1C3 = { 1C3_I } + 2C0 = { 2C0_I } + 2C1 = { 2C1_I } + 2C2 = { 2C2_I } + 2C3 = { 2C3_I } + G1 = { ~G1BAR } + G2 = { ~G2BAR } + ABAR = { ~A } + BBAR = { ~B } + I0 = { G1 & BBAR & ABAR & 1C0 } + I1 = { G1 & BBAR & A & 1C1 } + I2 = { G1 & B & ABAR & 1C2 } + I3 = { G1 & B & A & 1C3 } + I4 = { G2 & BBAR & ABAR & 2C0 } + I5 = { G2 & BBAR & A & 2C1 } + I6 = { G2 & B & ABAR & 2C2 } + I7 = { G2 & B & A & 2C3 } + Y1 = { I0 | I1 | I2 | I3 } + Y2 = { I4 | I5 | I6 | I7 } * UAS253DLY PINDLY (2,2,10) DPWR DGND + Y1 Y2 + G1BAR G2BAR + A B 1C0 1C1 1C2 1C3 2C0 2C1 2C2 2C3 + Y1_O Y2_O + IO_AS00 + MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + BOOLEAN: + DATA1 = { (CHANGED(1C0,0) | CHANGED(1C1,0) | CHANGED(1C2,0) | + CHANGED(1C3,0)) } + DATA2 = { (CHANGED(2C0,0) | CHANGED(2C1,0) | CHANGED(2C2,0) | + CHANGED(2C3,0)) } + SELECT = { CHANGED(A,0) | CHANGED(B,0) } + TRISTATE: + ENABLE LO G1BAR + Y1_O = { + CASE( + TRN_ZH, DELAY(4NS,-1,12.5NS), + TRN_ZL, DELAY(4NS,-1,11.5NS), + TRN_HZ, DELAY(2NS,-1,6NS), + TRN_LZ, DELAY(2NS,-1,7NS), + SELECT & TRN_LH, DELAY(4NS,-1,13.5NS), + SELECT & TRN_HL, DELAY(4NS,-1,11.5NS), + DATA1 & TRN_LH, DELAY(3NS,-1,7.5NS), + DATA1 & TRN_HL, DELAY(3NS,-1,8NS), + DELAY(5NS,-1,14NS) + ) + } + TRISTATE: + ENABLE LO G2BAR + Y2_O = { + CASE( + TRN_ZH, DELAY(4NS,-1,12.5NS), + TRN_ZL, DELAY(4NS,-1,11.5NS), + TRN_HZ, DELAY(2NS,-1,6NS), + TRN_LZ, DELAY(2NS,-1,7NS), + SELECT & TRN_LH, DELAY(4NS,-1,13.5NS), + SELECT & TRN_HL, DELAY(4NS,-1,11.5NS), + DATA2 & TRN_LH, DELAY(3NS,-1,7.5NS), + DATA2 & TRN_HL, DELAY(3NS,-1,8NS), + DELAY(5NS,-1,14NS) + ) + } * .ENDS * *$ *--------- * 74AS257 QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS * WITH 3-STATE OUTPUTS * * The ALS/AS Data Book, 1986, TI * JSW 8/25/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74AS257 GBAR_I 1A_I 1B_I 2A_I 2B_I 3A_I 3B_I 4A_I 4B_I SEL_I + Y1_O Y2_O Y3_O Y4_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UAS257LOG LOGICEXP(10,14) DPWR DGND + GBAR_I 1A_I 1B_I 2A_I 2B_I 3A_I 3B_I 4A_I 4B_I SEL_I + GBAR 1A 1B 2A 2B 3A 3B 4A 4B SEL Y1 Y2 Y3 Y4 + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} + LOGIC: + GBAR = { GBAR_I } + 1A = { 1A_I } + 1B = { 1B_I } + 2A = { 2A_I } + 2B = { 2B_I } + 3A = { 3A_I } + 3B = { 3B_I } + 4A = { 4A_I } + 4B = { 4B_I } + SEL = { SEL_I } + SELBAR = { ~SEL } + Y1 = { (1A & SELBAR) | (1B & SEL) } + Y2 = { (2A & SELBAR) | (2B & SEL) } + Y3 = { (3A & SELBAR) | (3B & SEL) } + Y4 = { (4A & SELBAR) | (4B & SEL) } * UAS257DLY PINDLY (4,1,9) DPWR DGND + Y1 Y2 Y3 Y4 + GBAR + 1A 1B 2A 2B 3A 3B 4A 4B SEL + Y1_O Y2_O Y3_O Y4_O + IO_AS00 + MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + BOOLEAN: + DATA = { CHANGED(1A,0) | CHANGED(1B,0) | CHANGED(2A,0) | CHANGED(2B,0) | + CHANGED(3A,0) | CHANGED(3B,0) | CHANGED(4A,0) | CHANGED(4B,0) } + SELECT = { CHANGED(SEL,0) } + TRISTATE: + ENABLE LO = GBAR + Y1_O Y2_O Y3_O Y4_O = { + CASE( + TRN_ZH, DELAY(2NS,-1,7.5NS), + TRN_ZL, DELAY(2NS,-1,9.5NS), + TRN_HZ, DELAY(1.5NS,-1,6.5NS), + TRN_LZ, DELAY(2NS,-1,7NS), + SELECT & TRN_LH, DELAY(2NS,-1,11NS), + SELECT & TRN_HL, DELAY(2NS,-1,10NS), + DATA & TRN_LH, DELAY(1NS,-1,5.5NS), + DATA & TRN_HL, DELAY(1NS,-1,6NS), + DELAY(3NS,-1,12NS) + ) + } * .ENDS * *$ *--------- * 74AS258 QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS * WITH 3-STATE OUTPUTS * * The ALS/AS Data Book, 1986, TI * JSW 8/25/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74AS258 GBAR_I 1A_I 1B_I 2A_I 2B_I 3A_I 3B_I 4A_I 4B_I SEL_I + Y1_O Y2_O Y3_O Y4_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UAS258LOG LOGICEXP(10,14) DPWR DGND + GBAR_I 1A_I 1B_I 2A_I 2B_I 3A_I 3B_I 4A_I 4B_I SEL_I + GBAR 1A 1B 2A 2B 3A 3B 4A 4B SEL Y1 Y2 Y3 Y4 + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} + LOGIC: + GBAR = { GBAR_I } + 1A = { 1A_I } + 1B = { 1B_I } + 2A = { 2A_I } + 2B = { 2B_I } + 3A = { 3A_I } + 3B = { 3B_I } + 4A = { 4A_I } + 4B = { 4B_I } + SEL = { SEL_I } + SELBAR = { ~SEL } + Y1 = { ~((1A & SELBAR) | (1B & SEL)) } + Y2 = { ~((2A & SELBAR) | (2B & SEL)) } + Y3 = { ~((3A & SELBAR) | (3B & SEL)) } + Y4 = { ~((4A & SELBAR) | (4B & SEL)) } * UAS258DLY PINDLY (4,1,9) DPWR DGND + Y1 Y2 Y3 Y4 + GBAR + 1A 1B 2A 2B 3A 3B 4A 4B SEL + Y1_O Y2_O Y3_O Y4_O + IO_AS00 + MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + BOOLEAN: + DATA = { CHANGED(1A,0) | CHANGED(1B,0) | CHANGED(2A,0) | CHANGED(2B,0) | + CHANGED(3A,0) | CHANGED(3B,0) | CHANGED(4A,0) | CHANGED(4B,0) } + SELECT = { CHANGED(SEL,0) } + TRISTATE: + ENABLE LO = GBAR + Y1_O Y2_O Y3_O Y4_O = { + CASE( + TRN_ZH, DELAY(2NS,-1,8NS), + TRN_ZL, DELAY(2NS,-1,10NS), + TRN_HZ, DELAY(1.5NS,-1,6NS), + TRN_LZ, DELAY(2NS,-1,6.5NS), + SELECT & TRN_LH, DELAY(2NS,-1,9.5NS), + SELECT & TRN_HL, DELAY(2NS,-1,10NS), + DATA & TRN_LH, DELAY(1NS,-1,5NS), + DATA & TRN_HL, DELAY(1NS,-1,4NS), + DELAY(3NS,-1,11NS) + ) + } * .ENDS * *$ *------------------------------------------------------------------------- * 74AS264 LOOK-AHEAD CARRY GENERATOR * * ALS/AS LOGIC CIRCUITS DATA BOOK, 1986, TI * JLS 9-18-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES * .SUBCKT 74AS264 CE_I A0_I A1_I A2_I A3_I B0_I B1_I B2_I B3_I + C0_O C1_O C2_O RCOA_O RCOB_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UAS264LOG LOGICEXP (9,6) DPWR DGND + CE_I A0_I A1_I A2_I A3_I B0_I B1_I B2_I B3_I + CE + C0 C1 C2 RCOA RCOB + D0_GATE IO_AS00 + IO_LEVEL={IO_LEVEL} + + LOGIC: + CE = { CE_I } + A0 = { A0_I } + A1 = { A1_I } + A2 = { A2_I } + A3 = { A3_I } + B0 = { B0_I } + B1 = { B1_I } + B2 = { B2_I } + B3 = { B3_I } + RCOB = { CE | B0 | B1 | B2 | B3 } + RCOA = { (CE & A0 & A1 & A2 & A3) | + (B1 & A1 & A2 & A3) | + (B2 & A2 & A3) | + (B3 & A3) } + C2 = { (CE & A0 & A1 & A2) | + (B0 & A0 & A1 & A2) | + (B1 & A1 & A2) | + (B2 & A2) } + C1 = { (CE & A0 & A1) | + (B0 & A0 & A1) | + (B1 & A1) } + C0 = { (CE & A0) | + (B0 & A0) } * UAS264DLY PINDLY (5,0,1) DPWR DGND + C0 C1 C2 RCOA RCOB + CE + C0_O C1_O C2_O RCOA_O RCOB_O + IO_AS00 + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + PINDLY: + C0_O C1_O C2_O = { + CASE ( + CHANGED(CE,0) & TRN_LH, DELAY(-1,6NS,-1), + DELAY(-1,5NS,-1) + ) + } + RCOA_O RCOB_O = { DELAY(-1,5NS,-1) } * .ENDS * *$ *--------- * 74AS280 PARITY GENERATOR/CHECKER ODD/EVEN 9-BIT * * ALS/AS LOGIC CIRCUITS DATA BOOK, 1986, TI * JLS 8-25-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES * .SUBCKT 74AS280 A_I B_I C_I D_I E_I F_I G_I H_I I_I + EOUT_O OOUT_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UAS280LOG LOGICEXP (9,2) DPWR DGND + A_I B_I C_I D_I E_I F_I G_I H_I I_I + EOUT OOUT + D0_GATE IO_AS00 + IO_LEVEL={IO_LEVEL} + + LOGIC: + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + E = { E_I } + F = { F_I } + G = { G_I } + H = { H_I } + I = { I_I } + + ABC = { (A & ~B & ~C) | (~A & B & ~C) | (~A & ~B & C) | (A & B & C) } + DEF = { (D & ~E & ~F) | (~D & E & ~F) | (~D & ~E & F) | (D & E & F) } + GHI = { (G & ~H & ~I) | (~G & H & ~I) | (~G & ~H & I) | (G & H & I) } + EOUT = { (~ABC & DEF & GHI) | (ABC & ~DEF & GHI) | (ABC & DEF & ~GHI) | + (~ABC & ~DEF & ~GHI) } + OOUT = { ~EOUT } * UAS280DLY PINDLY (2,0,0) DPWR DGND + EOUT OOUT + + EOUT_O OOUT_O + IO_AS00 + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + PINDLY: + EOUT_O = { + CASE ( + TRN_HL, DELAY(3NS,-1,11NS), + DELAY(3NS,-1,12NS) + ) + } + OOUT_O = { + CASE ( + TRN_HL, DELAY(3NS,-1,11.5NS), + DELAY(3NS,-1,12NS) + ) + } * .ENDS * *$ *------------------------------------------------------------------------- * 74AS282 LOOK-AHEAD CARRY GENERATOR * * ALS/AS LOGIC CIRCUITS DATA BOOK, 1986, TI * JLS 9-18-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES * .SUBCKT 74AS282 S0_I S1_I CNA_I CNB_I + P0BAR_I P1BAR_I P2BAR_I P3BAR_I G0BAR_I G1BAR_I G2BAR_I G3BAR_I + PBAR_O GBAR_O CN+Z_O CN+Y_O CN+X_O CN/_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UAS282LOG LOGICEXP (12,18) DPWR DGND + S0_I S1_I CNA_I CNB_I + P0BAR_I P1BAR_I P2BAR_I P3BAR_I G0BAR_I G1BAR_I G2BAR_I G3BAR_I + S0 S1 CNA CNB + P0BAR P1BAR P2BAR P3BAR G0BAR G1BAR G2BAR G3BAR + PBAR GBAR CN+Z CN+Y CN+X CN/ + D0_GATE IO_AS00 + IO_LEVEL={IO_LEVEL} + + LOGIC: + S0 = { S0_I } + S1 = { S1_I } + CNA = { CNA_I } + CNB = { CNB_I } + P0BAR = { P0BAR_I } + P1BAR = { P1BAR_I } + P2BAR = { P2BAR_I } + P3BAR = { P3BAR_I } + G0BAR = { G0BAR_I } + G1BAR = { G1BAR_I } + G2BAR = { G2BAR_I } + G3BAR = { G3BAR_I } + CN/ = { (~S0 & ~S1 & CNA) | + ( S0 & ~S1 & ~CNA) | + (~S0 & S1 & CNB) | + ( S0 & S1 & ~CNB) } + PBAR = { P0BAR | P1BAR | P2BAR | P3BAR } + GBAR = { ( G0BAR & G1BAR & G2BAR & G3BAR) | + (P1BAR & G1BAR & G2BAR & G3BAR) | + (P2BAR & G2BAR & G3BAR) | + (P3BAR & G3BAR) } + CN+Z = { (~CN/ & G0BAR & G1BAR & G2BAR) | + (P0BAR & G0BAR & G1BAR & G2BAR) | + (P1BAR & G1BAR & G2BAR) | + (P2BAR & G2BAR) } + CN+Y = { (~CN/ & G0BAR & G1BAR) | + (P0BAR & G0BAR & G1BAR) | + (P1BAR & G1BAR) } + CN+X = { (~CN/ & G0BAR) | + (P0BAR & G0BAR) } * UAS282DLY PINDLY (6,0,4) DPWR DGND + GBAR PBAR CN+X CN+Y CN+Z CN/ + S0 S1 CNA CNB + GBAR_O PBAR_O CN+X_O CN+Y_O CN+Z_O CN/_O + IO_AS00 + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + SELCAR = { CHANGED(S0,0) | CHANGED(CNA,0) | + CHANGED(S1,0) | CHANGED(CNB,0) } + + PINDLY: + GBAR_O = { + CASE ( + TRN_LH, DELAY(-1,6NS,-1), + DELAY(-1,5NS,-1) + ) + } + PBAR_O = { DELAY(-1,5NS,-1) } + CN+X_O CN+Y_O CN+Z_O = { + CASE ( + SELCAR & TRN_LH, DELAY(-1,6NS,-1), + SELCAR & TRN_HL, DELAY(-1,6NS,-1), + DELAY(-1,5NS,-1) + ) + } + CN/_O = { DELAY(-1,6NS,-1) } * .ENDS * *$ *------------------------------------------------------------------------- * 74AS286 PARITY GENERATOR/CHECKER 9-BIT * * ALS/AS LOGIC CIRCUITS DATA BOOK, TI, 1986 * JLS 8-16-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES * .SUBCKT 74AS286 A_I B_I C_I D_I E_I F_I G_I H_I I_I XMITBAR_I + PIO_B PE_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UAS286LOG LOGICEXP (11,13) DPWR DGND + A_I B_I C_I D_I E_I F_I G_I H_I I_I XMITBAR_I PIO_B + A B C D E F G H I XMITBAR PIO_IN PIO_OUT PE + D0_GATE IO_AS00 + IO_LEVEL={IO_LEVEL} + + LOGIC: + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + E = { E_I } + F = { F_I } + G = { G_I } + H = { H_I } + I = { I_I } + XMITBAR = { XMITBAR_I } + PIO_IN = { PIO_B } + + PARITY = { A ^ B ^ C ^ D ^ E ^ F ^ G ^ H ^ I } + PIO_OUT = { ~PARITY } + PE = { (PARITY ^ PIO_IN) | ~XMITBAR } * UAS286DLY PINDLY (2,1,1) DPWR DGND + PIO_OUT PE + XMITBAR + PIO_IN + PIO_B PE_O + IO_AS00 + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + POLAR = { CHANGED(PIO_IN,0) } + + TRISTATE: + ENABLE LO XMITBAR + PIO_B = { + CASE ( + TRN_ZH, DELAY(3NS,-1,13.0NS), + TRN_ZL, DELAY(3NS,-1,16.0NS), + TRN_HZ, DELAY(3NS,-1,11.5NS), + TRN_LZ, DELAY(3NS,-1,10.0NS), + TRN_LH, DELAY(3NS,-1,15.0NS), + TRN_HL, DELAY(3NS,-1,14.0NS), + DELAY(3NS,-1,16.0NS) + ) + } + PINDLY: + PE_O = { + CASE ( + POLAR, DELAY(3NS,-1, 9.0NS), + DELAY(3NS,-1,16.5NS) + ) + } * .ENDS * *$ *--------- * 74AS298 MULTIPLEXERS QUAD 2-INPUT WITH STORAGE * * ALS/AS LOGIC DATA BOOK, 1986, TI * TC 08/25/92 REMODELED USING LOGICEXP, PINDLY, & CONSTRAINT DEVICES * .SUBCKT 74AS298 WS_I CLK_I A1_I A2_I B1_I B2_I C1_I C2_I D1_I D2_I + QA_O QB_O QC_O QD_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 JKFF(4) DPWR DGND $D_HI $D_HI CLK + JA JB JC JD KA KB KC KD QA QB QC QD $D_NC $D_NC $D_NC $D_NC + D0_EFF IO_AS00 * UAS298LOG LOGICEXP(10,18) DPWR DGND + WS_I CLK_I A1_I A2_I B1_I B2_I C1_I C2_I D1_I D2_I + WS CLK A1 A2 B1 B2 C1 C2 D1 D2 JA JB JC JD KA KB KC KD + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} + LOGIC: + WS = { WS_I } + CLK = { CLK_I } + A1 = { A1_I } + A2 = { A2_I } + B1 = { B1_I } + B2 = { B2_I } + C1 = { C1_I } + C2 = { C2_I } + D1 = { D1_I } + D2 = { D2_I } + IWS = { ~WS } + KA = { ~((A1 & IWS) | (WS & A2)) } + KB = { ~((B1 & IWS) | (WS & B2)) } + KC = { ~((C1 & IWS) | (WS & C2)) } + KD = { ~((D1 & IWS) | (WS & D2)) } + JA = { ~KA } + JB = { ~KB } + JC = { ~KC } + JD = { ~KD } * UAS298DLY PINDLY (4,0,10) DPWR DGND + QA QB QC QD + A1 A2 B1 B2 C1 C2 D1 D2 WS CLK + QA_O QB_O QC_O QD_O + IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + PINDLY: + QA_O QB_O QC_O QD_O = { + CASE( + TRN_LH, DELAY(2NS,-1,9NS), + DELAY(1NS,-1,11NS) + ) + } + FREQ: + NODE = CLK + MAXFREQ = 100MEG + WIDTH: + NODE = CLK + MIN_LO = 5NS + MIN_HI = 5NS + SETUP_HOLD: + DATA(4) = A1 B1 C1 D1 + CLOCK HL = CLK + SETUPTIME = 4.5NS + HOLDTIME = 3.5NS + WHEN = { WS!='1 ^ CHANGED(WS,0) } + SETUP_HOLD: + DATA(4) = A2 B2 C2 D2 + CLOCK HL = CLK + SETUPTIME = 4.5NS + HOLDTIME = 3.5NS + WHEN = { WS!='0 ^ CHANGED(WS,0) } + SETUP_HOLD: + DATA(1) = WS + CLOCK HL = CLK + SETUPTIME = 13NS + HOLDTIME = 1NS * .ENDS * *$ *--------- * 74AS352 DUAL 4-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS * * The ALS/AS Data Book, 1986, TI * JSW 8/24/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74AS352 G1BAR_I G2BAR_I A_I B_I 1C0_I 1C1_I 1C2_I 1C3_I + 2C0_I 2C1_I 2C2_I 2C3_I Y1_O Y2_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UAS352LOG LOGICEXP(12,14) DPWR DGND + G1BAR_I G2BAR_I A_I B_I 1C0_I 1C1_I 1C2_I 1C3_I 2C0_I 2C1_I 2C2_I 2C3_I + G1BAR G2BAR A B 1C0 1C1 1C2 1C3 2C0 2C1 2C2 2C3 Y1 Y2 + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} + LOGIC: + G1BAR = { G1BAR_I } + G2BAR = { G2BAR_I } + A = { A_I } + B = { B_I } + 1C0 = { 1C0_I } + 1C1 = { 1C1_I } + 1C2 = { 1C2_I } + 1C3 = { 1C3_I } + 2C0 = { 2C0_I } + 2C1 = { 2C1_I } + 2C2 = { 2C2_I } + 2C3 = { 2C3_I } + G1 = { ~G1BAR } + G2 = { ~G2BAR } + ABAR = { ~A } + BBAR = { ~B } + I0 = { G1 & BBAR & ABAR & 1C0 } + I1 = { G1 & BBAR & A & 1C1 } + I2 = { G1 & B & ABAR & 1C2 } + I3 = { G1 & B & A & 1C3 } + I4 = { G2 & BBAR & ABAR & 2C0 } + I5 = { G2 & BBAR & A & 2C1 } + I6 = { G2 & B & ABAR & 2C2 } + I7 = { G2 & B & A & 2C3 } + Y1 = { ~(I0 | I1 | I2 | I3) } + Y2 = { ~(I4 | I5 | I6 | I7) } * UAS352DLY PINDLY (2,0,12) DPWR DGND + Y1 Y2 + G1BAR G2BAR A B 1C0 1C1 1C2 1C3 2C0 2C1 2C2 2C3 + Y1_O Y2_O + IO_AS00 + MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + BOOLEAN: + DATA1 = { (CHANGED(1C0,0) | CHANGED(1C1,0) | CHANGED(1C2,0) | + CHANGED(1C3,0)) } + DATA2 = { (CHANGED(2C0,0) | CHANGED(2C1,0) | CHANGED(2C2,0) | + CHANGED(2C3,0)) } + SELECT = { CHANGED(A,0) | CHANGED(B,0) } + PINDLY: + Y1_O = { + CASE( + SELECT & TRN_HL, DELAY(4NS,-1,13NS), + CHANGED(G1BAR,0) & TRN_HL, DELAY(4NS,-1,12NS), + SELECT & TRN_LH, DELAY(4NS,-1,11NS), + CHANGED(G1BAR,0) & TRN_LH, DELAY(3NS,-1,7NS), + DATA1 & TRN_LH, DELAY(2NS,-1,6.5NS), + DATA1 & TRN_HL, DELAY(2NS,-1,6NS), + DELAY(5NS,-1,14NS) + ) + } + Y2_O = { + CASE( + SELECT & TRN_HL, DELAY(4NS,-1,13NS), + CHANGED(G2BAR,0) & TRN_HL, DELAY(4NS,-1,12NS), + SELECT & TRN_LH, DELAY(4NS,-1,11NS), + CHANGED(G2BAR,0) & TRN_LH, DELAY(3NS,-1,7NS), + DATA2 & TRN_LH, DELAY(2NS,-1,6.5NS), + DATA2 & TRN_HL, DELAY(2NS,-1,6NS), + DELAY(5NS,-1,14NS) + ) + } * .ENDS * *$ *--------- * 74AS353A DUAL 1-OF-4 DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS * * The ALS/AS Data Book, 1986, TI * JSW 8/24/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74AS353A G1BAR_I G2BAR_I A_I B_I 1C0_I 1C1_I 1C2_I 1C3_I + 2C0_I 2C1_I 2C2_I 2C3_I Y1_O Y2_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UAS353ALOG LOGICEXP(12,14) DPWR DGND + G1BAR_I G2BAR_I A_I B_I 1C0_I 1C1_I 1C2_I 1C3_I 2C0_I 2C1_I 2C2_I 2C3_I + G1BAR G2BAR A B 1C0 1C1 1C2 1C3 2C0 2C1 2C2 2C3 Y1 Y2 + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} + LOGIC: + G1BAR = { G1BAR_I } + G2BAR = { G2BAR_I } + A = { A_I } + B = { B_I } + 1C0 = { 1C0_I } + 1C1 = { 1C1_I } + 1C2 = { 1C2_I } + 1C3 = { 1C3_I } + 2C0 = { 2C0_I } + 2C1 = { 2C1_I } + 2C2 = { 2C2_I } + 2C3 = { 2C3_I } + G1 = { ~G1BAR } + G2 = { ~G2BAR } + ABAR = { ~A } + BBAR = { ~B } + I0 = { G1 & BBAR & ABAR & 1C0 } + I1 = { G1 & BBAR & A & 1C1 } + I2 = { G1 & B & ABAR & 1C2 } + I3 = { G1 & B & A & 1C3 } + I4 = { G2 & BBAR & ABAR & 2C0 } + I5 = { G2 & BBAR & A & 2C1 } + I6 = { G2 & B & ABAR & 2C2 } + I7 = { G2 & B & A & 2C3 } + Y1 = { ~(I0 | I1 | I2 | I3) } + Y2 = { ~(I4 | I5 | I6 | I7) } * UAS353ADLY PINDLY (2,2,10) DPWR DGND + Y1 Y2 + G1BAR G2BAR + A B 1C0 1C1 1C2 1C3 2C0 2C1 2C2 2C3 + Y1_O Y2_O + IO_AS00 + MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + BOOLEAN: + DATA1 = { (CHANGED(1C0,0) | CHANGED(1C1,0) | CHANGED(1C2,0) | + CHANGED(1C3,0)) } + DATA2 = { (CHANGED(2C0,0) | CHANGED(2C1,0) | CHANGED(2C2,0) | + CHANGED(2C3,0)) } + SELECT = { CHANGED(A,0) | CHANGED(B,0) } + TRISTATE: + ENABLE LO G1BAR + Y1_O = { + CASE( + TRN_ZH, DELAY(3NS,-1,7.5NS), + TRN_ZL, DELAY(4NS,-1,12.5NS), + TRN_HZ, DELAY(2NS,-1,5.5NS), + TRN_LZ, DELAY(3NS,-1,7.5NS), + SELECT & TRN_HL, DELAY(4NS,-1,12NS), + SELECT & TRN_LH, DELAY(3NS,-1,9NS), + DATA1 & TRN_LH, DELAY(3NS,-1,7.5NS), + DATA1 & TRN_HL, DELAY(2NS,-1,6NS), + DELAY(5NS,-1,13NS) + ) + } + TRISTATE: + ENABLE LO G2BAR + Y2_O = { + CASE( + TRN_ZH, DELAY(3NS,-1,7.5NS), + TRN_ZL, DELAY(4NS,-1,12.5NS), + TRN_HZ, DELAY(2NS,-1,5.5NS), + TRN_LZ, DELAY(3NS,-1,7.5NS), + SELECT & TRN_HL, DELAY(4NS,-1,12NS), + SELECT & TRN_LH, DELAY(3NS,-1,9NS), + DATA2 & TRN_LH, DELAY(3NS,-1,7.5NS), + DATA2 & TRN_HL, DELAY(2NS,-1,6NS), + DELAY(5NS,-1,13NS) + ) + } * .ENDS * *$ *--------- * 74AS373 Octal D-Type Transparent Latches with 3-STATE Outputs * * The ALS/AS Data Book, 1986, TI * atl 7/18/89 Update interface and model names * .subckt 74AS373 OCBAR C 1D 2D 3D 4D 5D 6D 7D 8D 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UA inv DPWR DGND + OCBAR OC + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} U1 dltch(8) DPWR DGND + $D_HI $D_HI C + 1D 2D 3D 4D 5D 6D 7D 8D + 1QI 2QI 3QI 4QI 5QI 6QI 7QI 8QI + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D_AS373_1 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 buf3a(8) DPWR DGND + 1QI 2QI 3QI 4QI 5QI 6QI 7QI 8QI + OC + 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q + D_AS373_2 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_AS373_1 ugff ( + tpgqlhmn=3ns tpgqlhmx=5.5ns + tpgqhlmn=1.5ns tpgqhlmx=1.5ns + twghmn=4.5ns tsudgmn=2ns + thdgmn=3ns + ) .model D_AS373_2 utgate ( + tplhmn=3.5ns tplhmx=6ns + tphlmn=3.5ns tphlmx=6ns + tpzhmn=2ns tpzhmx=6.5ns + tpzlmn=4.5ns tpzlmx=9.5ns + tphzmn=3ns tphzmx=6.5ns + tplzmn=3ns tplzmx=7ns + ) *$ *--------- * 74AS374 Octal D-Type Edge-Triggered Flip-Flops with 3-STATE Outputs * * The ALS/AS Data Book, 1986, TI * atl 7/18/89 Update interface and model names * .subckt 74AS374 OCBAR CLK D1 D2 D3 D4 D5 D6 D7 D8 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UOC inv DPWR DGND + OCBAR OC + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} UD dff(8) DPWR DGND + $D_HI $D_HI CLK + D1 D2 D3 D4 D5 D6 D7 D8 + SQ1 SQ2 SQ3 SQ4 SQ5 SQ6 SQ7 SQ8 + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D_AS374_1 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UQS buf3a(8) DPWR DGND + SQ1 SQ2 SQ3 SQ4 SQ5 SQ6 SQ7 SQ8 + OC + Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 + D_AS374_2 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_AS374_1 ueff ( + twclklmn=3ns twclkhmn=4ns + tsudclkmn=2ns thdclkmn=2ns + ) .model D_AS374_2 utgate ( + tplhmn=3ns tplhmx=8ns + tphlmn=4ns tphlmx=9ns + tpzhmn=2ns tpzhmx=6ns + tpzlmn=3ns tpzlmx=10ns + tphzmn=2ns tphzmx=6ns + tplzmn=2ns tplzmx=6ns + ) *$ *--------- * 74AS533 Octal D-TYPE Transparent Latches with 3-STATE Outputs * * The ALS/AS Data Book, 1986, TI * atl 7/19/89 Update interface and model names * .subckt 74AS533 OCBAR C 1D 2D 3D 4D 5D 6D 7D 8D 1QBAR 2QBAR 3QBAR 4QBAR 5QBAR + 6QBAR 7QBAR 8QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U0 inv DPWR DGND + OCBAR OC + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} U1 dltch(8) DPWR DGND + $D_HI $D_HI C + 1D 2D 3D 4D 5D 6D 7D 8D + 1QI 2QI 3QI 4QI 5QI 6QI 7QI 8QI + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D_AS533_1 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 inv3a(8) DPWR DGND + 1QI 2QI 3QI 4QI 5QI 6QI 7QI 8QI + OC + 1QBAR 2QBAR 3QBAR 4QBAR 5QBAR 6QBAR 7QBAR 8QBAR + D_AS533_2 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_AS533_1 ugff ( + tpgqlhmn=0.5ns tpgqlhmx=1ns + tpgqhlmn=1ns tpgqhlmx=1.5ns + twghmn=2ns tsudgmn=2ns + thdgmn=3ns + ) .model D_AS533_2 utgate ( + tplhmn=4ns tplhmx=7.5ns + tphlmn=4ns tphlmx=7ns + tpzhmn=2ns tpzhmx=6.5ns + tpzlmn=4.5ns tpzlmx=9.5ns + tphzmn=3ns tphzmx=6.5ns + tplzmn=3ns tplzmx=7ns + ) *$ *--------- * 74AS534 Octal D-TYPE Edge-Triggered Flip-Flops with 3-STATE Outputs * * The ALS/AS Data Book, 1986, TI * atl 7/19/89 Update interface and model names * .subckt 74AS534 OCBAR CLK 1D 2D 3D 4D 5D 6D 7D 8D 1QBAR 2QBAR 3QBAR 4QBAR 5QBAR + 6QBAR 7QBAR 8QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UOC inv DPWR DGND + OCBAR OC + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} UDFF dff(8) DPWR DGND + $D_HI $D_HI CLK + 1D 2D 3D 4D 5D 6D 7D 8D + 1QQ 2QQ 3QQ 4QQ 5QQ 6QQ 7QQ 8QQ + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D_AS534_1 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UOCQ inv3a(8) DPWR DGND + 1QQ 2QQ 3QQ 4QQ 5QQ 6QQ 7QQ 8QQ + OC + 1QBAR 2QBAR 3QBAR 4QBAR 5QBAR 6QBAR 7QBAR 8QBAR + D_AS534_2 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_AS534_1 ueff ( + twclklmn=3ns twclkhmn=4ns + tsudclkmn=2ns thdclkmn=2ns + ) .model D_AS534_2 utgate ( + tplhmn=3ns tplhmx=8ns + tphlmn=4ns tphlmx=9ns + tpzhmn=2ns tpzhmx=6ns + tpzlmn=3ns tpzlmx=10ns + tphzmn=2ns tphzmx=6ns + tplzmn=2ns tplzmx=6ns + ) *$ *--------- * 74AS573 Octal D-TYPE Transparent Latches with 3-STATE Outputs * * The ALS/AS Data Book, 1986, TI * atl 7/20/89 Update interface and model names * .subckt 74AS573 OCBAR C 1D 2D 3D 4D 5D 6D 7D 8D 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U0 inv DPWR DGND + OCBAR OC + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} U1 dltch(8) DPWR DGND + $D_HI $D_HI C + 1D 2D 3D 4D 5D 6D 7D 8D + 1QI 2QI 3QI 4QI 5QI 6QI 7QI 8QI + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D_AS573_1 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 buf3a(8) DPWR DGND + 1QI 2QI 3QI 4QI 5QI 6QI 7QI 8QI + OC + 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q + D_AS573_2 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_AS573_1 ugff ( + tpgqlhmn=3ns tpgqlhmx=5.5ns + tpgqhlmn=1ns tpgqhlmx=1.5ns + twghmn=4.5ns tsudgmn=2ns + thdgmn=3ns + ) .model D_AS573_2 utgate ( + tplhmn=3ns tplhmx=6ns + tphlmn=3ns tphlmx=6ns + tpzhmn=2ns tpzhmx=6.5ns + tpzlmn=4ns tpzlmx=9.5ns + tphzmn=2ns tphzmx=6.5ns + tplzmn=2ns tplzmx=7ns + ) *$ *--------- * 74AS574 Octal D-TYPE Edge-Triggered Flip-Flops with 3-STATE Outputs * * The ALS/AS Data Book, 1986, TI * atl 7/20/89 Update interface and model names * .subckt 74AS574 OCBAR CLK 1D 2D 3D 4D 5D 6D 7D 8D 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UOC inv DPWR DGND + OCBAR OC + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} UD dff(8) DPWR DGND + $D_HI $D_HI CLK + 1D 2D 3D 4D 5D 6D 7D 8D + SQ1 SQ2 SQ3 SQ4 SQ5 SQ6 SQ7 SQ8 + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D_AS574_1 IO_AS00 MNTYMXDLY={MNTYMXDLY} UQS buf3a(8) DPWR DGND + SQ1 SQ2 SQ3 SQ4 SQ5 SQ6 SQ7 SQ8 + OC + 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q + D_AS574_2 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_AS574_1 ueff ( + twclklmn=2ns twclkhmn=4ns + tsudclkmn=2ns thdclkmn=2ns + ) .model D_AS574_2 utgate ( + tplhmn=3ns tplhmx=8ns + tphlmn=4ns tphlmx=9ns + tpzhmn=2ns tpzhmx=6ns + tpzlmn=3ns tpzlmx=10ns + tphzmn=2ns tphzmx=6ns + tplzmn=2ns tplzmx=6ns + ) *$ *--------- * 74AS575 Octal D-TYPE Edge-Triggered Flip-Flops with 3-STATE Outputs * * The ALS/AS Data Book, 1986, TI * atl 7/21/89 Update interface and model names * .subckt 74AS575 OCBAR CLK CLRBAR 1D 2D 3D 4D 5D 6D 7D 8D 1Q 2Q 3Q 4Q 5Q 6Q + 7Q 8Q + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UOC inv DPWR DGND + OCBAR OC + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} UBUF1 buf DPWR DGND + CLRBAR CLRBAR_BUF + D_AS575_1 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UBUF2 buf DPWR DGND + CLRBAR_BUF CLRBARX + D0_GATE IO_AS00 UBUF3 buf DPWR DGND + CLRBAR_BUF CLRBARX + D_AS575_2 IO_AS00 MNTYMXDLY={MNTYMXDLY} UAND anda(2,8) DPWR DGND + CLRBARX 1D + CLRBARX 2D + CLRBARX 3D + CLRBARX 4D + CLRBARX 5D + CLRBARX 6D + CLRBARX 7D + CLRBARX 8D + 1DD 2DD 3DD 4DD 5DD 6DD 7DD 8DD + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} UDFF dff(8) DPWR DGND + $D_HI $D_HI CLK + 1DD 2DD 3DD 4DD 5DD 6DD 7DD 8DD + 1QQ 2QQ 3QQ 4QQ 5QQ 6QQ 7QQ 8QQ + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D_AS575_3 IO_AS00 MNTYMXDLY={MNTYMXDLY} UOCQ buf3a(8) DPWR DGND + 1QQ 2QQ 3QQ 4QQ 5QQ 6QQ 7QQ 8QQ + OC + 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q + D_AS575_4 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_AS575_1 ugate ( + tplhmn=2ns tphlmn=2ns + ) .model D_AS575_2 ugate ( + tplhmn=1.5ns tphlmn=1.5ns + ) .model D_AS575_3 ueff ( + twclklmn=2ns twclkhmn=4ns + tsudclkmn=2ns thdclkmn=2ns + ) .model D_AS575_4 utgate ( + tplhmn=3ns tplhmx=8ns + tphlmn=4ns tphlmx=9ns + tpzhmn=2ns tpzhmx=6ns + tpzlmn=3ns tpzlmx=10ns + tphzmn=2ns tphzmx=6ns + tplzmn=2ns tplzmx=6ns + ) *$ *--------- * 74AS576 Octal D-TYPE Edge-Triggered Flip-Flops with 3-STATE Outputs * * The ALS/AS Data Book, 1986, TI * atl 7/21/89 Update interface and model names * .subckt 74AS576 OCBAR CLK 1D 2D 3D 4D 5D 6D 7D 8D 1QBAR 2QBAR 3QBAR 4QBAR 5QBAR + 6QBAR 7QBAR 8QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UOC inv DPWR DGND + OCBAR OC + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} UDFF dff(8) DPWR DGND + $D_HI $D_HI CLK + 1D 2D 3D 4D 5D 6D 7D 8D + 1QQ 2QQ 3QQ 4QQ 5QQ 6QQ 7QQ 8QQ + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D_AS576_1 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UOCQ inv3a(8) DPWR DGND + 1QQ 2QQ 3QQ 4QQ 5QQ 6QQ 7QQ 8QQ + OC + 1QBAR 2QBAR 3QBAR 4QBAR 5QBAR 6QBAR 7QBAR 8QBAR + D_AS576_2 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_AS576_1 ueff ( + twclklmn=2ns twclkhmn=4ns + tsudclkmn=2ns thdclkmn=2ns + ) .model D_AS576_2 utgate ( + tplhmn=3ns tplhmx=8ns + tphlmn=4ns tphlmx=9ns + tpzhmn=2ns tpzhmx=6ns + tpzlmn=3ns tpzlmx=10ns + tphzmn=2ns tphzmx=6ns + tplzmn=2ns tplzmx=6ns + ) *$ *--------- * 74AS577 Octal D-TYPE Edge-Triggered Flip-Flops with 3-STATE Outputs * * The ALS/AS Data Book, 1986, TI * atl 9/6/89 Update interface and model names * .subckt 74AS577 OCBAR CLK CLRBAR 1D 2D 3D 4D 5D 6D 7D 8D 1QBAR 2QBAR 3QBAR + 4QBAR 5QBAR 6QBAR 7QBAR 8QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UBUF buf DPWR DGND + CLRBAR CLB + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} UINV inv DPWR DGND + OCBAR OC + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} UCLBX1 buf DPWR DGND + CLB CLBX + D_AS577_1 IO_AS00 MNTYMXDLY={MNTYMXDLY} UCLBX2 buf DPWR DGND + CLB CLBX + D_AS577_2 IO_AS00 MNTYMXDLY={MNTYMXDLY} UD anda(2,8) DPWR DGND + 1D CLBX + 2D CLBX + 3D CLBX + 4D CLBX + 5D CLBX + 6D CLBX + 7D CLBX + 8D CLBX + D1 D2 D3 D4 D5 D6 D7 D8 + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} UQI dff(8) DPWR DGND + $D_HI $D_HI CLK + D1 D2 D3 D4 D5 D6 D7 D8 + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + 1QI 2QI 3QI 4QI 5QI 6QI 7QI 8QI + D_AS577_3 IO_AS00 MNTYMXDLY={MNTYMXDLY} UQB buf3a(8) DPWR DGND + 1QI 2QI 3QI 4QI 5QI 6QI 7QI 8QI + OC + 1QBAR 2QBAR 3QBAR 4QBAR 5QBAR 6QBAR 7QBAR 8QBAR + D_AS577_4 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_AS577_1 ugate ( + tplhmn=2ns tphlmn=2ns + ) .model D_AS577_2 ugate ( + tplhmn=3.5ns tphlmn=3.5ns + ) .model D_AS577_3 ueff ( + twclklmn=2ns twclkhmn=4ns + tsudclkmn=2ns thdclkmn=2ns + ) .model D_AS577_4 utgate ( + tplhmn=3ns tplhmx=8ns + tphlmn=4ns tphlmx=9ns + tpzhmn=2ns tpzhmx=6ns + tpzlmn=3ns tpzlmx=10ns + tphzmn=2ns tphzmx=6ns + tplzmn=2ns tplzmx=6ns + ) *$ *--------- * 74AS580 Octal D-TYPE Transparent Inverting Latches with 3-STATE Outputs * * The ALS/AS Data Book, 1986, TI * atl 7/21/89 Update interface and model names * .subckt 74AS580 OCBAR C 1D 2D 3D 4D 5D 6D 7D 8D 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U0 inv DPWR DGND + OCBAR OC + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} U1 dltch(8) DPWR DGND + $D_HI $D_HI C + 1D 2D 3D 4D 5D 6D 7D 8D + 1QI 2QI 3QI 4QI 5QI 6QI 7QI 8QI + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D_AS580_1 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 inv3a(8) DPWR DGND + 1QI 2QI 3QI 4QI 5QI 6QI 7QI 8QI + OC + 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q + D_AS580_2 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_AS580_1 ugff ( + tpgqlhmn=1ns tpgqlhmx=1ns + tpgqhlmn=2ns tpgqhlmx=1.5ns + twghmn=2ns tsudgmn=2ns + thdgmn=3ns + ) .model D_AS580_2 utgate ( + tplhmn=3ns tplhmx=7.5ns + tphlmn=3ns tphlmx=7ns + tpzhmn=2ns tpzhmx=6.5ns + tpzlmn=4ns tpzlmx=9.5ns + tphzmn=2ns tphzmx=6.5ns + tplzmn=2ns tplzmx=7ns + ) * *$ *---------- * 74AS620 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS * * ALS/AS LOGIC CIRCUITS DATA BOOK, 1986, TI * JLS 9-3-92 UPDATE TIMING * .SUBCKT 74AS620 GBABAR_I GAB_I + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 BUF DPWR DGND + GAB_I GAB + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} U2 INV DPWR DGND + GBABAR_I GBA + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} * U3 INV3A(8) DPWR DGND + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + GAB + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + D_AS620_AB IO_AS00 + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U4 INV3A(8) DPWR DGND + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + GBA + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + D_AS620_BA IO_AS00 + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} * .MODEL D_AS620_AB UTGATE ( + TPLHMN=1NS TPLHMX= 7NS + TPHLMN=2NS TPHLMX= 6NS + TPZHMN=2NS TPZHMX= 8NS + TPZLMN=2NS TPZLMX= 9NS + TPHZMN=1NS TPHZMX= 6NS + TPLZMN=2NS TPLZMX=13NS + ) .MODEL D_AS620_BA UTGATE ( + TPLHMN=1NS TPLHMX= 7NS + TPHLMN=2NS TPHLMX= 6NS + TPZHMN=2NS TPZHMX= 8NS + TPZLMN=2NS TPZLMX= 9NS + TPHZMN=1NS TPHZMX= 6NS + TPLZMN=2NS TPLZMX=12NS + ) * .ENDS * *$ *--------- * 74AS621 OCTAL BUS TRANSCEIVERS WITH OPEN-COLLECTOR OUTPUTS * * ALS/AS LOGIC CIRCUITS DATA BOOK, 1986, TI * KN 8/28/92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74AS621 GBABAR_I GAB_I A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UAS621LOG LOGICEXP(18,18) DPWR DGND + GBABAR_I GAB_I A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + GBABAR GAB A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} + + LOGIC: + * BUFFER: + GBABAR = { GBABAR_I } + GAB = { GAB_I } + GABBAR = { ~GAB_I } + * OUTPUT ASSIGNMENTS + A1 = { B1_B | GBABAR } + A2 = { B2_B | GBABAR } + A3 = { B3_B | GBABAR } + A4 = { B4_B | GBABAR } + A5 = { B5_B | GBABAR } + A6 = { B6_B | GBABAR } + A7 = { B7_B | GBABAR } + A8 = { B8_B | GBABAR } + B1 = { A1_B | GABBAR } + B2 = { A2_B | GABBAR } + B3 = { A3_B | GABBAR } + B4 = { A4_B | GABBAR } + B5 = { A5_B | GABBAR } + B6 = { A6_B | GABBAR } + B7 = { A7_B | GABBAR } + B8 = { A8_B | GABBAR } * UAS621DLY PINDLY (16,0,18) DPWR DGND + A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 + GBABAR GAB A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + IO_AS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + A_OUTPUT = { (GBABAR!='1 & GAB!='1) | (GBABAR!='1 & GAB!='0) | + (GBABAR!='0 & GAB!='1) } + B_OUTPUT = { (GBABAR!='0 & GAB!='0) | (GBABAR!='1 & GAB!='0) | + (GBABAR!='0 & GAB!='1) } + GBABAR_CHANGE = { CHANGED(GBABAR,0) } + GAB_CHANGE = { CHANGED(GAB,0) } + NO_DIR_CH = { ~(CHANGED(GBABAR,0) | CHANGED(GAB,0)) } + + PINDLY: + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B = { + CASE( + A_OUTPUT & GBABAR_CHANGE & TRN_LH, DELAY(5NS,-1,21NS), + A_OUTPUT & TRN_LH, DELAY(5NS,-1,21NS), + A_OUTPUT & GBABAR_CHANGE & TRN_HL, DELAY(1NS,-1,9NS), + A_OUTPUT & TRN_HL, DELAY(1NS,-1,7.5NS), + B_OUTPUT, DELAY(0NS,0NS,0NS), + DELAY(6NS,-1,22NS) ;DEFAULT + ) + } + + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B = { + CASE( + B_OUTPUT & NO_DIR_CH & TRN_LH, DELAY(5NS,-1,24NS), + B_OUTPUT & GAB_CHANGE & TRN_LH, DELAY(5NS,-1,22NS), + B_OUTPUT & GAB_CHANGE & TRN_HL, DELAY(1NS,-1,10NS), + B_OUTPUT & NO_DIR_CH & TRN_HL, DELAY(1NS,-1,7.5NS), + A_OUTPUT, DELAY(0NS,0NS,0NS), + DELAY(6NS,-1,25NS) ;DEFAULT + ) + } * .ENDS * *$ *--------- * 74AS622 OCTAL BUS TRANSCEIVERS WITH OPEN-COLLECTOR OUTPUTS * * ALS/AS LOGIC CIRCUITS DATA BOOK, 1986, TI * KN 8/28/92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74AS622 GBABAR_I GAB_I A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UAS622LOG LOGICEXP(18,18) DPWR DGND + GBABAR_I GAB_I A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + GBABAR GAB A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} + + LOGIC: + * BUFFER: + GBABAR = { GBABAR_I } + GBA = { ~GBABAR } + GAB = { GAB_I } + * OUTPUT ASSIGNMENTS + A1 = { ~(B1_B & GBA) } + A2 = { ~(B2_B & GBA) } + A3 = { ~(B3_B & GBA) } + A4 = { ~(B4_B & GBA) } + A5 = { ~(B5_B & GBA) } + A6 = { ~(B6_B & GBA) } + A7 = { ~(B7_B & GBA) } + A8 = { ~(B8_B & GBA) } + B1 = { ~(A1_B & GAB) } + B2 = { ~(A2_B & GAB) } + B3 = { ~(A3_B & GAB) } + B4 = { ~(A4_B & GAB) } + B5 = { ~(A5_B & GAB) } + B6 = { ~(A6_B & GAB) } + B7 = { ~(A7_B & GAB) } + B8 = { ~(A8_B & GAB) } * UAS622DLY PINDLY (16,0,18) DPWR DGND + A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 + GBABAR GAB A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + IO_AS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + A_OUTPUT = { (GBABAR!='1 & GAB!='1) | (GBABAR!='1 & GAB!='0) | + (GBABAR!='0 & GAB!='1) } + B_OUTPUT = { (GBABAR!='0 & GAB!='0) | (GBABAR!='1 & GAB!='0) | + (GBABAR!='0 & GAB!='1) } + GBABAR_CHANGE = { CHANGED(GBABAR,0) } + GAB_CHANGE = { CHANGED(GAB,0) } + NO_DIR_CH = { ~(CHANGED(GBABAR,0) | CHANGED(GAB,0)) } + + PINDLY: + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B = { + CASE( + A_OUTPUT & NO_DIR_CH & TRN_LH, DELAY(5NS,-1,25NS), + A_OUTPUT & GBABAR_CHANGE & TRN_LH, DELAY(5NS,-1,22NS), + A_OUTPUT & GBABAR_CHANGE & TRN_HL, DELAY(1NS,-1,10NS), + A_OUTPUT & NO_DIR_CH & TRN_HL, DELAY(1NS,-1,8NS), + B_OUTPUT, DELAY(0NS,0NS,0NS), + DELAY(6NS,-1,26NS) ;DEFAULT + ) + } + + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B = { + CASE( + B_OUTPUT & NO_DIR_CH & TRN_LH, DELAY(5NS,-1,24.5NS), + B_OUTPUT & GAB_CHANGE & TRN_LH, DELAY(5NS,-1,23NS), + B_OUTPUT & GAB_CHANGE & TRN_HL, DELAY(1NS,-1,10.5NS), + B_OUTPUT & NO_DIR_CH & TRN_HL, DELAY(1NS,-1,8NS), + A_OUTPUT, DELAY(0NS,0NS,0NS), + DELAY(5NS,-1,25NS) ;DEFAULT + ) + } * .ENDS * *$ *---------- * 74AS623 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS * * ALS/AS LOGIC CIRCUITS DATA BOOK, 1986, TI * JLS 9-3-92 UPDATE TIMING * .SUBCKT 74AS623 GBABAR_I GAB_I + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 BUF DPWR DGND + GAB_I GAB + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} U2 INV DPWR DGND + GBABAR_I GBA + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} * U3 BUF3A(8) DPWR DGND + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + GAB + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + D_AS623_AB IO_AS00 + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U4 BUF3A(8) DPWR DGND + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + GBA + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + D_AS623_BA IO_AS00 + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} * .MODEL D_AS623_AB UTGATE ( + TPLHMN=1.0NS TPLHMX= 9.0NS + TPHLMN=1.0NS TPHLMX= 8.0NS + TPZHMN=2.0NS TPZHMX=11.5NS + TPZLMN=2.0NS TPZLMX=11.0NS + TPHZMN=1.0NS TPHZMX= 7.0NS + TPLZMN=1.0NS TPLZMX= 9.0NS + ) .MODEL D_AS623_BA UTGATE ( + TPLHMN=1.0NS TPLHMX= 9.0NS + TPHLMN=1.0NS TPHLMX= 8.5NS + TPZHMN=2.0NS TPZHMX=11.0NS + TPZLMN=2.0NS TPZLMX=10.0NS + TPHZMN=1.0NS TPHZMX= 7.5NS + TPLZMN=1.0NS TPLZMX=11.5NS + ) * .ENDS * *$ *--------- * 74AS638 BUS TRANSCEIVERS OCTAL WITH 3-STATE AND OPEN-COLLECTOR OUTPUTS * * ALS/AS LOGIC DATA BOOK, 1986, TI * TC 09/11/92 REMODELED USING LOGICEXP, PINDLY, & CONSTRAINT DEVICES .SUBCKT 74AS638 GBAR_I DIR_I + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 UAS638LOG LOGICEXP(18,35) DPWR DGND + GBAR_I DIR_I + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + GBAR DIR A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 + A1_O A2_O A3_O A4_O A5_O A6_O A7_O A8_O + B1_O B2_O B3_O B4_O B5_O B6_O B7_O B8_O ENB + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} + LOGIC: + GBAR = { GBAR_I } + DIR = { DIR_I } + A1 = { A1_B } + A2 = { A2_B } + A3 = { A3_B } + A4 = { A4_B } + A5 = { A5_B } + A6 = { A6_B } + A7 = { A7_B } + A8 = { A8_B } + B1 = { B1_B } + B2 = { B2_B } + B3 = { B3_B } + B4 = { B4_B } + B5 = { B5_B } + B6 = { B6_B } + B7 = { B7_B } + B8 = { B8_B } + ENA = { ~(GBAR | DIR) } + ENB = { ~GBAR & DIR } + A1_O = { ~(ENA & B1) } + A2_O = { ~(ENA & B2) } + A3_O = { ~(ENA & B3) } + A4_O = { ~(ENA & B4) } + A5_O = { ~(ENA & B5) } + A6_O = { ~(ENA & B6) } + A7_O = { ~(ENA & B7) } + A8_O = { ~(ENA & B8) } + B1_O = { ~A1 } + B2_O = { ~A2 } + B3_O = { ~A3 } + B4_O = { ~A4 } + B5_O = { ~A5 } + B6_O = { ~A6 } + B7_O = { ~A7 } + B8_O = { ~A8 } UAS638DLY_1 PINDLY(8,0,9) DPWR DGND + A1_O A2_O A3_O A4_O A5_O A6_O A7_O A8_O + GBAR B1 B2 B3 B4 B5 B6 B7 B8 + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + IO_AS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + BUS_B = { CHANGED(B1,0) | CHANGED(B2,0) | CHANGED(B3,0) | CHANGED(B4,0) | + CHANGED(B5,0) | CHANGED(B6,0) | CHANGED(B7,0) | CHANGED(B8,0) } + ENABLE = { CHANGED(GBAR,0) } + PINDLY: + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B = { + CASE( + BUS_B & TRN_LH, DELAY(5NS,-1,20NS), + ENABLE & TRN_LH, DELAY(5NS,-1,19NS), + ENABLE & TRN_HL, DELAY(2NS,-1,9NS), + BUS_B & TRN_HL, DELAY(2NS,-1,7NS), + DELAY(6NS,-1,21NS) + ) + } UAS638DLY_2 PINDLY(8,1,8) DPWR DGND + B1_O B2_O B3_O B4_O B5_O B6_O B7_O B8_O + ENB + A1 A2 A3 A4 A5 A6 A7 A8 + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + BUS_A = { CHANGED(A1,0) | CHANGED(A2,0) | CHANGED(A3,0) | CHANGED(A4,0) | + CHANGED(A5,0) | CHANGED(A6,0) | CHANGED(A7,0) | CHANGED(A8,0) } + TRISTATE: + ENABLE HI ENB + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B = { + CASE( + BUS_A & TRN_HL, DELAY(2NS,-1,6.5NS), + BUS_A & TRN_LH, DELAY(2NS,-1,7NS), + TRN_ZH, DELAY(2NS,-1,8NS), + TRN_ZL, DELAY(2NS,-1,10NS), + TRN_HZ, DELAY(2NS,-1,7NS), + TRN_LZ, DELAY(2NS,-1,10NS), + DELAY(3NS,-1,11NS) + ) + } .ENDS *$ *--------- * 74AS639 BUS TRANSCEIVERS OCTAL WITH 3-STATE AND OPEN-COLLECTOR OUTPUTS * * ALS/AS LOGIC DATA BOOK, 1986, TI * TC 09/11/92 REMODELED USING LOGICEXP, PINDLY, & CONSTRAINT DEVICES .SUBCKT 74AS639 GBAR_I DIR_I + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 UAS639LOG LOGICEXP(18,35) DPWR DGND + GBAR_I DIR_I + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + GBAR DIR A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 + A1_O A2_O A3_O A4_O A5_O A6_O A7_O A8_O + B1_O B2_O B3_O B4_O B5_O B6_O B7_O B8_O ENB + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} + LOGIC: + GBAR = { GBAR_I } + DIR = { DIR_I } + A1 = { A1_B } + A2 = { A2_B } + A3 = { A3_B } + A4 = { A4_B } + A5 = { A5_B } + A6 = { A6_B } + A7 = { A7_B } + A8 = { A8_B } + B1 = { B1_B } + B2 = { B2_B } + B3 = { B3_B } + B4 = { B4_B } + B5 = { B5_B } + B6 = { B6_B } + B7 = { B7_B } + B8 = { B8_B } + ENA = { ~(GBAR | DIR) } + ENB = { ~GBAR & DIR } + A1_O = { ~(ENA & ~B1) } + A2_O = { ~(ENA & ~B2) } + A3_O = { ~(ENA & ~B3) } + A4_O = { ~(ENA & ~B4) } + A5_O = { ~(ENA & ~B5) } + A6_O = { ~(ENA & ~B6) } + A7_O = { ~(ENA & ~B7) } + A8_O = { ~(ENA & ~B8) } + B1_O = { A1 } + B2_O = { A2 } + B3_O = { A3 } + B4_O = { A4 } + B5_O = { A5 } + B6_O = { A6 } + B7_O = { A7 } + B8_O = { A8 } UAS639DLY_1 PINDLY(8,0,9) DPWR DGND + A1_O A2_O A3_O A4_O A5_O A6_O A7_O A8_O + GBAR B1 B2 B3 B4 B5 B6 B7 B8 + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + IO_AS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + BUS_B = { CHANGED(B1,0) | CHANGED(B2,0) | CHANGED(B3,0) | CHANGED(B4,0) | + CHANGED(B5,0) | CHANGED(B6,0) | CHANGED(B7,0) | CHANGED(B8,0) } + ENABLE = { CHANGED(GBAR,0) } + PINDLY: + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B = { + CASE( + BUS_B & TRN_LH, DELAY(5NS,-1,22NS), + ENABLE & TRN_LH, DELAY(5NS,-1,21.5NS), + ENABLE & TRN_HL, DELAY(2NS,-1,11.5NS), + BUS_B & TRN_HL, DELAY(2NS,-1,9NS), + DELAY(6NS,-1,23NS) + ) + } UAS639DLY_2 PINDLY(8,1,8) DPWR DGND + B1_O B2_O B3_O B4_O B5_O B6_O B7_O B8_O + ENB + A1 A2 A3 A4 A5 A6 A7 A8 + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + BUS_A = { CHANGED(A1,0) | CHANGED(A2,0) | CHANGED(A3,0) | CHANGED(A4,0) | + CHANGED(A5,0) | CHANGED(A6,0) | CHANGED(A7,0) | CHANGED(A8,0) } + TRISTATE: + ENABLE HI ENB + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B = { + CASE( + BUS_A & TRN_LH, DELAY(2NS,-1,9.5NS), + BUS_A & TRN_HL, DELAY(2NS,-1,9NS), + TRN_ZH, DELAY(2NS,-1,10.5NS), + TRN_ZL, DELAY(2NS,-1,10.5NS), + TRN_HZ, DELAY(2NS,-1,7NS), + TRN_LZ, DELAY(2NS,-1,10.5NS), + DELAY(3NS,-1,11NS) + ) + } .ENDS *$ *---------- * 74AS640 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS * * ALS/AS LOGIC CIRCUITS DATA BOOK, 1986, TI * JLS 9-3-92 UPDATE TIMING * .SUBCKT 74AS640 GBAR_I DIR_I + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 BUFA(2) DPWR DGND + GBAR_I DIR_I + GBAR DIR + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} U2 INV DPWR DGND + DIR DIRBAR + D0_GATE IO_AS00 U3 NORA(2,2) DPWR DGND + DIRBAR GBAR DIR GBAR + ENABLEAB ENABLEBA + D0_GATE IO_AS00 * U4 INV3A(8) DPWR DGND + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + ENABLEAB + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + D_AS640 IO_AS00 + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U5 INV3A(8) DPWR DGND + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + ENABLEBA + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + D_AS640 IO_AS00 + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} * .MODEL D_AS640 UTGATE ( + TPLHMN=2NS TPLHMX= 7NS + TPHLMN=2NS TPHLMX= 6NS + TPZHMN=2NS TPZHMX= 8NS + TPZLMN=2NS TPZLMX=10NS + TPHZMN=2NS TPHZMX= 8NS + TPLZMN=2NS TPLZMX=13NS + ) * .ENDS * *$ *--------- * 74AS641 OCTAL BUS TRANSCEIVERS WITH OPEN-COLLECTOR OUTPUTS * * ALS/AS LOGIC CIRCUITS DATA BOOK, 1986, TI * NH 8/28/92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74AS641 GBAR_I DIR_I A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UAS641LOG LOGICEXP(18,20) DPWR DGND + GBAR_I DIR_I A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B B1_B B2_B B3_B B4_B + B5_B B6_B B7_B B8_B + GBAR DIR A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 ATOB BTOA + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} + + LOGIC: + * BUFFER + GBAR = { GBAR_I } + DIR = { DIR_I } + * OUTPUT ASSIGNMENTS + ATOB = { ~GBAR & DIR } + BTOA = { ~GBAR & ~DIR } + A1 = { ~(~B1_B & BTOA) } + A2 = { ~(~B2_B & BTOA) } + A3 = { ~(~B3_B & BTOA) } + A4 = { ~(~B4_B & BTOA) } + A5 = { ~(~B5_B & BTOA) } + A6 = { ~(~B6_B & BTOA) } + A7 = { ~(~B7_B & BTOA) } + A8 = { ~(~B8_B & BTOA) } + B1 = { ~(~A1_B & ATOB) } + B2 = { ~(~A2_B & ATOB) } + B3 = { ~(~A3_B & ATOB) } + B4 = { ~(~A4_B & ATOB) } + B5 = { ~(~A5_B & ATOB) } + B6 = { ~(~A6_B & ATOB) } + B7 = { ~(~A7_B & ATOB) } + B8 = { ~(~A8_B & ATOB) } * UAS641DLY PINDLY (16,0,4) DPWR DGND + A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 + GBAR DIR ATOB BTOA + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B B1_B B2_B B3_B B4_B + B5_B B6_B B7_B B8_B + IO_AS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + A_EN = { BTOA!='0 } + B_EN = { ATOB!='0 } + + PINDLY: + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B = { + CASE( + A_EN & CHANGED(DIR,0) & TRN_LH, DELAY(5NS,-1,22NS), + CHANGED(GBAR,0) & TRN_LH, DELAY(5NS,-1,21NS), + A_EN & TRN_LH, DELAY(5NS,-1,21NS), + A_EN & CHANGED(DIR,0) & TRN_HL, DELAY(1NS,-1,10NS), + CHANGED(GBAR,0) & TRN_HL, DELAY(1NS,-1,9NS), + A_EN & TRN_HL, DELAY(1NS,-1,7.5NS), + B_EN & CHANGED(DIR,0), DELAY(0,0,0), + DELAY(6NS,-1,23NS) ;DEFAULT + ) + } + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B = { + CASE( + B_EN & CHANGED(DIR,0) & TRN_LH, DELAY(5NS,-1,22NS), + CHANGED(GBAR,0) & TRN_LH, DELAY(5NS,-1,21NS), + B_EN & TRN_LH, DELAY(5NS,-1,21NS), + B_EN & CHANGED(DIR,0) & TRN_HL, DELAY(1NS,-1,10NS), + CHANGED(GBAR,0) & TRN_HL, DELAY(1NS,-1,9NS), + B_EN & TRN_HL, DELAY(1NS,-1,7.5NS), + A_EN & CHANGED(DIR,0), DELAY(0,0,0), + DELAY(6NS,-1,23NS) ;DEFAULT + ) + } * .ENDS * *$ *--------- * 74AS642 OCTAL BUS TRANSCEIVERS WITH OPEN-COLLECTOR OUTPUTS * * ALS/AS LOGIC CIRCUITS DATA BOOK, 1986, TI * NH 8/31/92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74AS642 GBAR_I DIR_I A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UAS642LOG LOGICEXP(18,20) DPWR DGND + GBAR_I DIR_I A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B B1_B B2_B B3_B B4_B + B5_B B6_B B7_B B8_B + GBAR DIR A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 ATOB BTOA + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} + + LOGIC: + * BUFFER + GBAR = { GBAR_I } + DIR = { DIR_I } + * OUTPUT ASSIGNMENTS + ATOB = { ~GBAR & DIR } + BTOA = { ~GBAR & ~DIR } + A1 = { ~(B1_B & BTOA) } + A2 = { ~(B2_B & BTOA) } + A3 = { ~(B3_B & BTOA) } + A4 = { ~(B4_B & BTOA) } + A5 = { ~(B5_B & BTOA) } + A6 = { ~(B6_B & BTOA) } + A7 = { ~(B7_B & BTOA) } + A8 = { ~(B8_B & BTOA) } + B1 = { ~(A1_B & ATOB) } + B2 = { ~(A2_B & ATOB) } + B3 = { ~(A3_B & ATOB) } + B4 = { ~(A4_B & ATOB) } + B5 = { ~(A5_B & ATOB) } + B6 = { ~(A6_B & ATOB) } + B7 = { ~(A7_B & ATOB) } + B8 = { ~(A8_B & ATOB) } * UAS642DLY PINDLY (16,0,4) DPWR DGND + A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 + GBAR DIR ATOB BTOA + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B B1_B B2_B B3_B B4_B + B5_B B6_B B7_B B8_B + IO_AS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + A_EN = { BTOA!='0 } + B_EN = { ATOB!='0 } + + PINDLY: + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B = { + CASE( + A_EN & TRN_LH, DELAY(5NS,-1,24NS), + A_EN & CHANGED(DIR,0) & TRN_LH, DELAY(5NS,-1,23.5NS), + CHANGED(GBAR,0) & TRN_LH, DELAY(5NS,-1,22NS), + A_EN & CHANGED(DIR,0) & TRN_HL, DELAY(1NS,-1,11.5NS), + CHANGED(GBAR,0) & TRN_HL, DELAY(1NS,-1,10NS), + A_EN & TRN_HL, DELAY(1NS,-1,7.5NS), + B_EN & CHANGED(DIR,0), DELAY(0,0,0), + DELAY(6NS,-1,25NS) ;DEFAULT + ) + } + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B = { + CASE( + B_EN & TRN_LH, DELAY(5NS,-1,24NS), + B_EN & CHANGED(DIR,0) & TRN_LH, DELAY(5NS,-1,23.5NS), + CHANGED(GBAR,0) & TRN_LH, DELAY(5NS,-1,22NS), + B_EN & CHANGED(DIR,0) & TRN_HL, DELAY(1NS,-1,11.5NS), + CHANGED(GBAR,0) & TRN_HL, DELAY(1NS,-1,10NS), + B_EN & TRN_HL, DELAY(1NS,-1,7.5NS), + A_EN & CHANGED(DIR,0), DELAY(0,0,0), + DELAY(6NS,-1,25NS) ;DEFAULT + ) + } * .ENDS * *$ *--------- * 74AS643 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS * * THE ALS/AS DATA BOOK, 1986, TI * ATL 9/8/89 UPDATE INTERFACE AND MODEL NAMES * KC 9/1/92 * .SUBCKT 74AS643 GBAR DIR A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 UBUF BUF DPWR DGND + DIR DR + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} UINV INVA(2) DPWR DGND + DR GBAR DRB G + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} UEN ANDA(2,2) DPWR DGND + DR G DRB G EAB EBA + D0_GATE IO_AS00 UA BUF3A(8) DPWR DGND + B1 B2 B3 B4 B5 B6 B7 B8 + EBA + A1 A2 A3 A4 A5 A6 A7 A8 + D_AS643_1 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UB INV3A(8) DPWR DGND + A1 A2 A3 A4 A5 A6 A7 A8 + EAB + B1 B2 B3 B4 B5 B6 B7 B8 + D_AS643_2 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ENDS * .MODEL D_AS643_1 UTGATE ( + TPLHMN=2NS TPLHMX=10NS + TPHLMN=2NS TPHLMX=9NS + TPZHMN=2NS TPZHMX=11NS + TPZLMN=2NS TPZLMX=11NS + TPHZMN=2NS TPHZMX=7.5NS + TPLZMN=2NS TPLZMX=10.5NS + ) .MODEL D_AS643_2 UTGATE ( + TPLHMN=2NS TPLHMX=8NS + TPHLMN=2NS TPHLMX=7NS + TPZHMN=2NS TPZHMX=10NS + TPZLMN=2NS TPZLMX=10NS + TPHZMN=2NS TPHZMX=7NS + TPLZMN=2NS TPLZMX=10NS + ) * *$ *--------- * 74AS644 OCTAL BUS TRANSCEIVERS WITH OPEN-COLLECTOR OUTPUTS * * ALS/AS LOGIC CIRCUITS DATA BOOK, 1986, TI * NH 8/31/92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74AS644 GBAR_I DIR_I A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UAS644LOG LOGICEXP(18,20) DPWR DGND + GBAR_I DIR_I A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B B1_B B2_B B3_B B4_B + B5_B B6_B B7_B B8_B + GBAR DIR A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 ATOB BTOA + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} + + LOGIC: + * BUFFER + GBAR = { GBAR_I } + DIR = { DIR_I } + * OUTPUT ASSIGNMENTS + ATOB = { ~GBAR & DIR } + BTOA = { ~GBAR & ~DIR } + A1 = { ~(~B1_B & BTOA) } + A2 = { ~(~B2_B & BTOA) } + A3 = { ~(~B3_B & BTOA) } + A4 = { ~(~B4_B & BTOA) } + A5 = { ~(~B5_B & BTOA) } + A6 = { ~(~B6_B & BTOA) } + A7 = { ~(~B7_B & BTOA) } + A8 = { ~(~B8_B & BTOA) } + B1 = { ~(A1_B & ATOB) } + B2 = { ~(A2_B & ATOB) } + B3 = { ~(A3_B & ATOB) } + B4 = { ~(A4_B & ATOB) } + B5 = { ~(A5_B & ATOB) } + B6 = { ~(A6_B & ATOB) } + B7 = { ~(A7_B & ATOB) } + B8 = { ~(A8_B & ATOB) } * UAS644DLY PINDLY (16,0,4) DPWR DGND + A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 + GBAR DIR ATOB BTOA + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B B1_B B2_B B3_B B4_B + B5_B B6_B B7_B B8_B + IO_AS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + A_EN = { BTOA!='0 } + B_EN = { ATOB!='0 } + + PINDLY: + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B = { + CASE( + A_EN & CHANGED(DIR,0) & TRN_LH, DELAY(5NS,-1,22NS), + CHANGED(GBAR,0) & TRN_LH, DELAY(5NS,-1,21NS), + A_EN & TRN_LH, DELAY(5NS,-1,21NS), + A_EN & CHANGED(DIR,0) & TRN_HL, DELAY(1NS,-1,10NS), + CHANGED(GBAR,0) & TRN_HL, DELAY(1NS,-1,9NS), + A_EN & TRN_HL, DELAY(1NS,-1,7.5NS), + B_EN & CHANGED(DIR,0), DELAY(0,0,0), + DELAY(6NS,-1,23NS) ;DEFAULT + ) + } + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B = { + CASE( + B_EN & TRN_LH, DELAY(5NS,-1,24NS), + B_EN & CHANGED(DIR,0) & TRN_LH, DELAY(5NS,-1,22NS), + CHANGED(GBAR,0) & TRN_LH, DELAY(5NS,-1,21NS), + B_EN & CHANGED(DIR,0) & TRN_HL, DELAY(1NS,-1,10NS), + CHANGED(GBAR,0) & TRN_HL, DELAY(1NS,-1,9NS), + B_EN & TRN_HL, DELAY(1NS,-1,7.5NS), + A_EN & CHANGED(DIR,0), DELAY(0,0,0), + DELAY(6NS,-1,25NS) ;DEFAULT + ) + } * .ENDS * *$ *--------- * 74AS645 OCTAL BUS TRANSCEIVERS * * THE ALS/AS DATA BOOK, 1986, TI * ATL 7/24/89 UPDATE INTERFACE AND MODEL NAMES * .SUBCKT 74AS645 GBAR DIR A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UBUFF BUFA(2) DPWR DGND + GBAR DIR GBAR_BUF DIR_BUF + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} UA NOR(2) DPWR DGND + GBAR_BUF DIR_BUF T1 + D0_GATE IO_AS00 UB INV DPWR DGND + GBAR_BUF RE1 + D0_GATE IO_AS00 UC AND(2) DPWR DGND + RE1 DIR_BUF T2 + D0_GATE IO_AS00 U1 BUF3A(8) DPWR DGND + A1 A2 A3 A4 A5 A6 A7 A8 + T2 + B1 B2 B3 B4 B5 B6 B7 B8 + D_AS645 IO_AS00_ST MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 BUF3A(8) DPWR DGND + B1 B2 B3 B4 B5 B6 B7 B8 + T1 + A1 A2 A3 A4 A5 A6 A7 A8 + D_AS645 IO_AS00_ST MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ENDS * .MODEL D_AS645 UTGATE ( + TPLHMN=2NS TPLHMX=9.5NS + TPHLMN=2NS TPHLMX=9NS + TPZHMN=2NS TPZHMX=11NS + TPZLMN=2NS TPZLMX=10NS + TPHZMN=2NS TPHZMX=7NS + TPLZMN=2NS TPLZMX=12NS + ) * *$ *--------- * 74AS646 OCTAL BUS TRANSCEIVER/REGISTER WITH 3-STATE OUTPUTS * * AS/AS Logic Data Book, 1986, TI * JSW 8/31/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74AS646 GBAR_I DIR_I CBA_I SBA_I CAB_I SAB_I + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UAS646LOG1 LOGICEXP(38,40) DPWR DGND + GBAR_I DIR_I CBA_I SBA_I CAB_I SAB_I + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + QA1 QA2 QA3 QA4 QA5 QA6 QA7 QA8 + QB1 QB2 QB3 QB4 QB5 QB6 QB7 QB8 + GBAR DIR CBA SBA CAB SAB + A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 + A1_OUT A2_OUT A3_OUT A4_OUT A5_OUT A6_OUT A7_OUT A8_OUT + B1_OUT B2_OUT B3_OUT B4_OUT B5_OUT B6_OUT B7_OUT B8_OUT + ENA ENB + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} + LOGIC: + GBAR = { GBAR_I } + DIR = { DIR_I } + CBA = { CBA_I } + SBA = { SBA_I } + SBABAR = { ~SBA } + CAB = { CAB_I } + SAB = { SAB_I } + SABBAR = { ~SAB } + ENA = { ~DIR & ~GBAR } + ENB = { DIR & ~GBAR } + A1 = { A1_B } + B1 = { B1_B } + A2 = { A2_B } + B2 = { B2_B } + A3 = { A3_B } + B3 = { B3_B } + A4 = { A4_B } + B4 = { B4_B } + A5 = { A5_B } + B5 = { B5_B } + A6 = { A6_B } + B6 = { B6_B } + A7 = { A7_B } + B7 = { B7_B } + A8 = { A8_B } + B8 = { B8_B } + A1_OUT = { ~((~B1 & SBABAR) | (SBA & QB1)) } + B1_OUT = { ~((~A1 & SABBAR) | (SAB & QA1)) } + A2_OUT = { ~((~B2 & SBABAR) | (SBA & QB2)) } + B2_OUT = { ~((~A2 & SABBAR) | (SAB & QA2)) } + A3_OUT = { ~((~B3 & SBABAR) | (SBA & QB3)) } + B3_OUT = { ~((~A3 & SABBAR) | (SAB & QA3)) } + A4_OUT = { ~((~B4 & SBABAR) | (SBA & QB4)) } + B4_OUT = { ~((~A4 & SABBAR) | (SAB & QA4)) } + A5_OUT = { ~((~B5 & SBABAR) | (SBA & QB5)) } + B5_OUT = { ~((~A5 & SABBAR) | (SAB & QA5)) } + A6_OUT = { ~((~B6 & SBABAR) | (SBA & QB6)) } + B6_OUT = { ~((~A6 & SABBAR) | (SAB & QA6)) } + A7_OUT = { ~((~B7 & SBABAR) | (SBA & QB7)) } + B7_OUT = { ~((~A7 & SABBAR) | (SAB & QA7)) } + A8_OUT = { ~((~B8 & SBABAR) | (SBA & QB8)) } + B8_OUT = { ~((~A8 & SABBAR) | (SAB & QA8)) } * UAREG DFF(8) DPWR DGND $D_HI $D_HI CAB + A1 A2 A3 A4 A5 A6 A7 A8 + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + QA1 QA2 QA3 QA4 QA5 QA6 QA7 QA8 + D0_EFF IO_AS00 * UBREG DFF(8) DPWR DGND $D_HI $D_HI CBA + B1 B2 B3 B4 B5 B6 B7 B8 + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + QB1 QB2 QB3 QB4 QB5 QB6 QB7 QB8 + D0_EFF IO_AS00 * UAS646DLY PINDLY (16,2,23) DPWR DGND + A1_OUT A2_OUT A3_OUT A4_OUT A5_OUT A6_OUT A7_OUT A8_OUT B1_OUT B2_OUT B3_OUT B4_OUT B5_OUT B6_OUT B7_OUT B8_OUT + ENA ENB + A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 CAB CBA SAB SBA GBAR DIR DIR + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + IO_AS00 + MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + BOOLEAN: + BUSA = { CHANGED(A1,0) | CHANGED(A2,0) | CHANGED(A3,0) | CHANGED(A4,0) + | CHANGED(A5,0) | CHANGED(A6,0) | CHANGED(A7,0) | CHANGED(A8,0) } + BUSB = { CHANGED(B1,0) | CHANGED(B2,0) | CHANGED(B3,0) | CHANGED(B4,0) + | CHANGED(B5,0) | CHANGED(B6,0) | CHANGED(B7,0) | CHANGED(B8,0) } + + TRISTATE: + ENABLE HI ENA + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B = { + CASE( + CHANGED(CBA,0) & TRN_LH & SBA=='1, DELAY(2NS,-1,8.5NS), + CHANGED(CBA,0) & TRN_HL & SBA=='1, DELAY(2NS,-1,9NS), + BUSB & TRN_LH & SBA!='1, DELAY(2NS,-1,9NS), + BUSB & TRN_HL & SBA!='1, DELAY(1NS,-1,7NS), + CHANGED(SBA,0) & TRN_LH, DELAY(2NS,-1,11NS), + CHANGED(SBA,0) & TRN_HL, DELAY(2NS,-1,9NS), + CHANGED(GBAR,0) & TRN_ZH, DELAY(2NS,-1,9NS), + CHANGED(GBAR,0) & TRN_ZL, DELAY(3NS,-1,14NS), + CHANGED(GBAR,0) & TRN_$Z, DELAY(2NS,-1,9NS), + CHANGED(DIR,0) & TRN_ZH, DELAY(3NS,-1,16NS), + CHANGED(DIR,0) & TRN_ZL, DELAY(3NS,-1,18NS), + CHANGED(DIR,0) & TRN_$Z, DELAY(2NS,-1,10NS), + DELAY(4NS,-1,19NS) + ) + } + TRISTATE: + ENABLE HI ENB + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B = { + CASE( + CHANGED(CAB,0) & TRN_LH & SAB=='1, DELAY(2NS,-1,8.5NS), + CHANGED(CAB,0) & TRN_HL & SAB=='1, DELAY(2NS,-1,9NS), + BUSA & TRN_LH & SAB!='1, DELAY(2NS,-1,9NS), + BUSA & TRN_HL & SAB!='1, DELAY(1NS,-1,7NS), + CHANGED(SAB,0) & TRN_LH, DELAY(2NS,-1,11NS), + CHANGED(SAB,0) & TRN_HL, DELAY(2NS,-1,9NS), + CHANGED(GBAR,0) & TRN_ZH, DELAY(2NS,-1,9NS), + CHANGED(GBAR,0) & TRN_ZL, DELAY(3NS,-1,14NS), + CHANGED(GBAR,0) & TRN_$Z, DELAY(2NS,-1,9NS), + CHANGED(DIR,0) & TRN_ZH, DELAY(3NS,-1,16NS), + CHANGED(DIR,0) & TRN_ZL, DELAY(3NS,-1,18NS), + CHANGED(DIR,0) & TRN_$Z, DELAY(2NS,-1,10NS), + DELAY(4NS,-1,19NS) + ) + } + FREQ: + NODE = CAB + MAXFREQ = 90MEG + FREQ: + NODE = CBA + MAXFREQ = 90MEG + WIDTH: + NODE = CAB + MIN_HI = 5NS + MIN_LO = 6NS + WIDTH: + NODE = CBA + MIN_HI = 5NS + MIN_LO = 6NS + SETUP_HOLD: + DATA(8) = A1 A2 A3 A4 A5 A6 A7 A8 + CLOCK LH = CAB + SETUPTIME = 6NS + WHEN = { DIR!='0 } + SETUP_HOLD: + DATA(8) = B1 B2 B3 B4 B5 B6 B7 B8 + CLOCK LH = CBA + SETUPTIME = 6NS + WHEN = { DIR!='1 } * .ENDS * *$ *--------- * 74AS648 OCTAL BUS TRANSCEIVER/REGISTER WITH 3-STATE OUTPUTS * * AS/AS Logic Data Book, 1986, TI * JSW 9/7/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74AS648 GBAR_I DIR_I CBA_I SBA_I CAB_I SAB_I + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UAS648LOG1 LOGICEXP(38,40) DPWR DGND + GBAR_I DIR_I CBA_I SBA_I CAB_I SAB_I + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + QA1 QA2 QA3 QA4 QA5 QA6 QA7 QA8 + QB1 QB2 QB3 QB4 QB5 QB6 QB7 QB8 + GBAR DIR CBA SBA CAB SAB + A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 + A1_OUT A2_OUT A3_OUT A4_OUT A5_OUT A6_OUT A7_OUT A8_OUT + B1_OUT B2_OUT B3_OUT B4_OUT B5_OUT B6_OUT B7_OUT B8_OUT + ENA ENB + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} + LOGIC: + GBAR = { GBAR_I } + DIR = { DIR_I } + CBA = { CBA_I } + SBA = { SBA_I } + SBABAR = { ~SBA } + CAB = { CAB_I } + SAB = { SAB_I } + SABBAR = { ~SAB } + ENA = { ~DIR & ~GBAR } + ENB = { DIR & ~GBAR } + A1 = { A1_B } + B1 = { B1_B } + A2 = { A2_B } + B2 = { B2_B } + A3 = { A3_B } + B3 = { B3_B } + A4 = { A4_B } + B4 = { B4_B } + A5 = { A5_B } + B5 = { B5_B } + A6 = { A6_B } + B6 = { B6_B } + A7 = { A7_B } + B7 = { B7_B } + A8 = { A8_B } + B8 = { B8_B } + A1_OUT = { ~((B1 & SBABAR) | (SBA & QB1)) } + B1_OUT = { ~((A1 & SABBAR) | (SAB & QA1)) } + A2_OUT = { ~((B2 & SBABAR) | (SBA & QB2)) } + B2_OUT = { ~((A2 & SABBAR) | (SAB & QA2)) } + A3_OUT = { ~((B3 & SBABAR) | (SBA & QB3)) } + B3_OUT = { ~((A3 & SABBAR) | (SAB & QA3)) } + A4_OUT = { ~((B4 & SBABAR) | (SBA & QB4)) } + B4_OUT = { ~((A4 & SABBAR) | (SAB & QA4)) } + A5_OUT = { ~((B5 & SBABAR) | (SBA & QB5)) } + B5_OUT = { ~((A5 & SABBAR) | (SAB & QA5)) } + A6_OUT = { ~((B6 & SBABAR) | (SBA & QB6)) } + B6_OUT = { ~((A6 & SABBAR) | (SAB & QA6)) } + A7_OUT = { ~((B7 & SBABAR) | (SBA & QB7)) } + B7_OUT = { ~((A7 & SABBAR) | (SAB & QA7)) } + A8_OUT = { ~((B8 & SBABAR) | (SBA & QB8)) } + B8_OUT = { ~((A8 & SABBAR) | (SAB & QA8)) } * UAREG DFF(8) DPWR DGND $D_HI $D_HI CAB + A1 A2 A3 A4 A5 A6 A7 A8 + QA1 QA2 QA3 QA4 QA5 QA6 QA7 QA8 + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D0_EFF IO_AS00 * UBREG DFF(8) DPWR DGND $D_HI $D_HI CBA + B1 B2 B3 B4 B5 B6 B7 B8 + QB1 QB2 QB3 QB4 QB5 QB6 QB7 QB8 + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D0_EFF IO_AS00 * UAS648DLY PINDLY (16,2,23) DPWR DGND + A1_OUT A2_OUT A3_OUT A4_OUT A5_OUT A6_OUT A7_OUT A8_OUT B1_OUT B2_OUT B3_OUT B4_OUT B5_OUT B6_OUT B7_OUT B8_OUT + ENA ENB + A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 CAB CBA SAB SBA GBAR DIR DIR + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + IO_AS00 + MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + BOOLEAN: + BUSA = { CHANGED(A1,0) | CHANGED(A2,0) | CHANGED(A3,0) | CHANGED(A4,0) + | CHANGED(A5,0) | CHANGED(A6,0) | CHANGED(A7,0) | CHANGED(A8,0) } + BUSB = { CHANGED(B1,0) | CHANGED(B2,0) | CHANGED(B3,0) | CHANGED(B4,0) + | CHANGED(B5,0) | CHANGED(B6,0) | CHANGED(B7,0) | CHANGED(B8,0) } + + TRISTATE: + ENABLE HI ENA + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B = { + CASE( + CHANGED(CBA,0) & TRN_LH & SBA=='1, DELAY(2NS,-1,8.5NS), + CHANGED(CBA,0) & TRN_HL & SBA=='1, DELAY(2NS,-1,9NS), + BUSB & TRN_LH & SBA!='1, DELAY(2NS,-1,8NS), + BUSB & TRN_HL & SBA!='1, DELAY(1NS,-1,7NS), + CHANGED(SBA,0) & TRN_LH, DELAY(2NS,-1,11NS), + CHANGED(SBA,0) & TRN_HL, DELAY(2NS,-1,9NS), + CHANGED(GBAR,0) & TRN_ZH, DELAY(2NS,-1,9NS), + CHANGED(GBAR,0) & TRN_ZL, DELAY(3NS,-1,15NS), + CHANGED(GBAR,0) & TRN_$Z, DELAY(2NS,-1,9NS), + CHANGED(DIR,0) & TRN_ZH, DELAY(3NS,-1,16NS), + CHANGED(DIR,0) & TRN_ZL, DELAY(3NS,-1,18NS), + CHANGED(DIR,0) & TRN_$Z, DELAY(2NS,-1,10NS), + DELAY(4NS,-1,19NS) + ) + } + TRISTATE: + ENABLE HI ENB + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B = { + CASE( + CHANGED(CAB,0) & TRN_LH & SAB=='1, DELAY(2NS,-1,8.5NS), + CHANGED(CAB,0) & TRN_HL & SAB=='1, DELAY(2NS,-1,9NS), + BUSA & TRN_LH & SAB!='1, DELAY(2NS,-1,8NS), + BUSA & TRN_HL & SAB!='1, DELAY(1NS,-1,7NS), + CHANGED(SAB,0) & TRN_LH, DELAY(2NS,-1,11NS), + CHANGED(SAB,0) & TRN_HL, DELAY(2NS,-1,9NS), + CHANGED(GBAR,0) & TRN_ZH, DELAY(2NS,-1,9NS), + CHANGED(GBAR,0) & TRN_ZL, DELAY(3NS,-1,15NS), + CHANGED(GBAR,0) & TRN_$Z, DELAY(2NS,-1,9NS), + CHANGED(DIR,0) & TRN_ZH, DELAY(3NS,-1,16NS), + CHANGED(DIR,0) & TRN_ZL, DELAY(3NS,-1,18NS), + CHANGED(DIR,0) & TRN_$Z, DELAY(2NS,-1,10NS), + DELAY(4NS,-1,19NS) + ) + } + FREQ: + NODE = CAB + MAXFREQ = 90MEG + FREQ: + NODE = CBA + MAXFREQ = 90MEG + WIDTH: + NODE = CAB + MIN_HI = 5NS + MIN_LO = 6NS + WIDTH: + NODE = CBA + MIN_HI = 5NS + MIN_LO = 6NS + SETUP_HOLD: + DATA(8) = A1 A2 A3 A4 A5 A6 A7 A8 + CLOCK LH = CAB + SETUPTIME = 6NS + WHEN = { DIR!='0 } + SETUP_HOLD: + DATA(8) = B1 B2 B3 B4 B5 B6 B7 B8 + CLOCK LH = CBA + SETUPTIME = 6NS + WHEN = { DIR!='1 } * .ENDS * *$ *--------- * 74AS651 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH INVERTED 3-STATE OUTPUTS * * ALS/AS LOGIC DATA BOOK, 1986, TI * JSW 09/10/92 REMODELED USING LOGICEXP, PINDLY, & CONSTRAINT DEVICES * * NOTE: ADDITIONAL LOGIC WAS ADDED TO MODEL THE BIDIRECTIONAL PINS OF THIS * DEVICE. * .SUBCKT 74AS651 GBABAR_I GAB_I CBA_I SBA_I CAB_I SAB_I A1_B A2_B A3_B A4_B + A5_B A6_B A7_B A8_B B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 DFF(8) DPWR DGND $D_HI $D_HI CAB + A1_IO A2_IO A3_IO A4_IO A5_IO A6_IO A7_IO A8_IO + QB1 QB2 QB3 QB4 QB5 QB6 QB7 QB8 + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D0_EFF IO_AS00 * U2 DFF(8) DPWR DGND $D_HI $D_HI CBA + B1_IO B2_IO B3_IO B4_IO B5_IO B6_IO B7_IO B8_IO + QA1 QA2 QA3 QA4 QA5 QA6 QA7 QA8 + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D0_EFF IO_AS00 * U3 BUF3A(8) DPWR DGND + A1_O A2_O A3_O A4_O A5_O A6_O A7_O A8_O IGBABAR + A1_IO A2_IO A3_IO A4_IO A5_IO A6_IO A7_IO A8_IO + D0_TGATE IO_AS00 * U4 BUF3A(8) DPWR DGND + B1_O B2_O B3_O B4_O B5_O B6_O B7_O B8_O GAB + B1_IO B2_IO B3_IO B4_IO B5_IO B6_IO B7_IO B8_IO + D0_TGATE IO_AS00 * U5 BUF3A(8) DPWR DGND + A1 A2 A3 A4 A5 A6 A7 A8 GBABAR + A1_IO A2_IO A3_IO A4_IO A5_IO A6_IO A7_IO A8_IO + D0_TGATE IO_AS00 * U6 BUF3A(8) DPWR DGND + B1 B2 B3 B4 B5 B6 B7 B8 IGAB + B1_IO B2_IO B3_IO B4_IO B5_IO B6_IO B7_IO B8_IO + D0_TGATE IO_AS00 * UAS651LOG LOGICEXP(38,40) DPWR DGND + GBABAR_I GAB_I CBA_I SBA_I CAB_I SAB_I A1_B A2_B A3_B A4_B A5_B A6_B + A7_B A8_B B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B QA1 QA2 QA3 + QA4 QA5 QA6 QA7 QA8 QB1 QB2 QB3 QB4 QB5 + QB6 QB7 QB8 + GBABAR GAB CBA SBA CAB SAB A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 + A1_O A2_O A3_O A4_O A5_O A6_O A7_O A8_O B1_O B2_O B3_O B4_O B5_O B6_O + B7_O B8_O IGAB IGBABAR + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} + LOGIC: + GBABAR = { GBABAR_I } + GAB = { GAB_I } + CBA = { CBA_I } + SBA = { SBA_I } + CAB = { CAB_I } + SAB = { SAB_I } + A1 = { A1_B } + A2 = { A2_B } + A3 = { A3_B } + A4 = { A4_B } + A5 = { A5_B } + A6 = { A6_B } + A7 = { A7_B } + A8 = { A8_B } + B1 = { B1_B } + B2 = { B2_B } + B3 = { B3_B } + B4 = { B4_B } + B5 = { B5_B } + B6 = { B6_B } + B7 = { B7_B } + B8 = { B8_B } + ISAB = { ~SAB } + ISBA = { ~SBA } + IGAB = { ~GAB } + IGBABAR = { ~GBABAR } + A1_O = { ~((SBA & QA1) | (ISBA & B1)) } + A2_O = { ~((SBA & QA2) | (ISBA & B2)) } + A3_O = { ~((SBA & QA3) | (ISBA & B3)) } + A4_O = { ~((SBA & QA4) | (ISBA & B4)) } + A5_O = { ~((SBA & QA5) | (ISBA & B5)) } + A6_O = { ~((SBA & QA6) | (ISBA & B6)) } + A7_O = { ~((SBA & QA7) | (ISBA & B7)) } + A8_O = { ~((SBA & QA8) | (ISBA & B8)) } + B1_O = { ~((SAB & QB1) | (ISAB & A1)) } + B2_O = { ~((SAB & QB2) | (ISAB & A2)) } + B3_O = { ~((SAB & QB3) | (ISAB & A3)) } + B4_O = { ~((SAB & QB4) | (ISAB & A4)) } + B5_O = { ~((SAB & QB5) | (ISAB & A5)) } + B6_O = { ~((SAB & QB6) | (ISAB & A6)) } + B7_O = { ~((SAB & QB7) | (ISAB & A7)) } + B8_O = { ~((SAB & QB8) | (ISAB & A8)) } * UAS651DLY PINDLY (16,2,22) DPWR DGND + A1_IO A2_IO A3_IO A4_IO A5_IO A6_IO A7_IO A8_IO B1_IO B2_IO B3_IO B4_IO B5_IO B6_IO B7_IO B8_IO + GBABAR GAB + CBA SBA CAB SAB A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 B7 B8 + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + CLOCK_BA = { CHANGED_LH(CBA,0) } + CLOCK_AB = { CHANGED_LH(CAB,0) } + SEL_BA = { CHANGED(SBA,0) } + SEL_AB = { CHANGED(SAB,0) } + BUS_A = { CHANGED(A1,0) | CHANGED(A2,0) | CHANGED(A3,0) | CHANGED(A4,0) | + CHANGED(A5,0) | CHANGED(A6,0) | CHANGED(A7,0) | CHANGED(A8,0) } + BUS_B = { CHANGED(B1,0) | CHANGED(B2,0) | CHANGED(B3,0) | CHANGED(B4,0) | + CHANGED(B5,0) | CHANGED(B6,0) | CHANGED(B7,0) | CHANGED(B8,0) } + TRISTATE: + ENABLE LO GBABAR + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B = { + CASE( + BUS_B & TRN_HL, DELAY(1NS,-1,7NS), + CLOCK_BA & TRN_LH, DELAY(2NS,-1,8.5NS), + CLOCK_BA & TRN_HL, DELAY(2NS,-1,9NS), + BUS_B & TRN_LH, DELAY(2NS,-1,8NS), + SEL_BA & TRN_HL, DELAY(2NS,-1,9NS), + TRN_$Z, DELAY(2NS,-1,9NS), + TRN_ZH, DELAY(2NS,-1,10NS), + SEL_BA & TRN_LH, DELAY(2NS,-1,11NS), + TRN_ZL, DELAY(3NS,-1,16NS), + DELAY(4NS,-1,17NS) + ) + } + TRISTATE: + ENABLE HI GAB + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B = { + CASE( + BUS_A & TRN_HL, DELAY(1NS,-1,7NS), + CLOCK_AB & TRN_LH, DELAY(2NS,-1,8.5NS), + CLOCK_AB & TRN_HL, DELAY(2NS,-1,9NS), + BUS_A & TRN_LH, DELAY(2NS,-1,8NS), + SEL_AB & TRN_HL, DELAY(2NS,-1,9NS), + TRN_HZ, DELAY(2NS,-1,10NS), + SEL_AB & TRN_LH, DELAY(2NS,-1,11NS), + TRN_ZH, DELAY(3NS,-1,11NS), + TRN_LZ, DELAY(2NS,-1,11NS), + TRN_ZL, DELAY(3NS,-1,16NS), + DELAY(4NS,-1,17NS) + ) + } + FREQ: + NODE = CBA + MAXFREQ = 90MEG + FREQ: + NODE = CAB + MAXFREQ = 90MEG + WIDTH: + NODE = CBA + MIN_LO = 6NS + MIN_HI = 5NS + WIDTH: + NODE = CAB + MIN_LO = 6NS + MIN_HI = 5NS + SETUP_HOLD: + DATA(8) = A1 A2 A3 A4 A5 A6 A7 A8 + CLOCK LH = CAB + SETUPTIME = 6NS + SETUP_HOLD: + DATA(8) = B1 B2 B3 B4 B5 B6 B7 B8 + CLOCK LH = CBA + SETUPTIME = 6NS * .ENDS * *$ *--------- * 74AS652 BUS TRANSCEIVERS AND REGISTERS OCTAL WITH 3-STATE OUTPUTS * * ALS/AS LOGIC DATA BOOK, 1986, TI * TC 09/04/92 REMODELED USING LOGICEXP, PINDLY, & CONSTRAINT DEVICES * * NOTE: ADDITIONAL LOGIC WAS ADDED TO MODEL THE BIDIRECTIONAL PINS OF THIS * DEVICE. * .SUBCKT 74AS652 GBABAR_I GAB_I CBA_I SBA_I CAB_I SAB_I + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 DFF(8) DPWR DGND $D_HI $D_HI CAB + A1_IO A2_IO A3_IO A4_IO A5_IO A6_IO A7_IO A8_IO + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + QB1BAR QB2BAR QB3BAR QB4BAR QB5BAR QB6BAR QB7BAR QB8BAR + D0_EFF IO_AS00 * U2 DFF(8) DPWR DGND $D_HI $D_HI CBA + B1_IO B2_IO B3_IO B4_IO B5_IO B6_IO B7_IO B8_IO + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + QA1BAR QA2BAR QA3BAR QA4BAR QA5BAR QA6BAR QA7BAR QA8BAR + D0_EFF IO_AS00 * U3 BUF3A(8) DPWR DGND + A1_O A2_O A3_O A4_O A5_O A6_O A7_O A8_O IGBABAR + A1_IO A2_IO A3_IO A4_IO A5_IO A6_IO A7_IO A8_IO + D0_TGATE IO_AS00 * U4 BUF3A(8) DPWR DGND + B1_O B2_O B3_O B4_O B5_O B6_O B7_O B8_O GAB + B1_IO B2_IO B3_IO B4_IO B5_IO B6_IO B7_IO B8_IO + D0_TGATE IO_AS00 * U5 BUF3A(8) DPWR DGND + A1 A2 A3 A4 A5 A6 A7 A8 GBABAR + A1_IO A2_IO A3_IO A4_IO A5_IO A6_IO A7_IO A8_IO + D0_TGATE IO_AS00 * U6 BUF3A(8) DPWR DGND + B1 B2 B3 B4 B5 B6 B7 B8 IGAB + B1_IO B2_IO B3_IO B4_IO B5_IO B6_IO B7_IO B8_IO + D0_TGATE IO_AS00 * UAS652LOG LOGICEXP(38,40) DPWR DGND + GBABAR_I GAB_I CBA_I SBA_I CAB_I SAB_I + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + QA1BAR QA2BAR QA3BAR QA4BAR QA5BAR QA6BAR QA7BAR QA8BAR + QB1BAR QB2BAR QB3BAR QB4BAR QB5BAR QB6BAR QB7BAR QB8BAR + GBABAR GAB CBA SBA CAB SAB A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 + A1_O A2_O A3_O A4_O A5_O A6_O A7_O A8_O + B1_O B2_O B3_O B4_O B5_O B6_O B7_O B8_O IGAB IGBABAR + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} + LOGIC: + GBABAR = { GBABAR_I } + GAB = { GAB_I } + CBA = { CBA_I } + SBA = { SBA_I } + CAB = { CAB_I } + SAB = { SAB_I } + A1 = { A1_B } + A2 = { A2_B } + A3 = { A3_B } + A4 = { A4_B } + A5 = { A5_B } + A6 = { A6_B } + A7 = { A7_B } + A8 = { A8_B } + B1 = { B1_B } + B2 = { B2_B } + B3 = { B3_B } + B4 = { B4_B } + B5 = { B5_B } + B6 = { B6_B } + B7 = { B7_B } + B8 = { B8_B } + ISAB = { ~SAB } + ISBA = { ~SBA } + IGAB = { ~GAB } + IGBABAR = { ~GBABAR } + A1_O = { ~((SBA & QA1BAR) | (ISBA & ~B1)) } + A2_O = { ~((SBA & QA2BAR) | (ISBA & ~B2)) } + A3_O = { ~((SBA & QA3BAR) | (ISBA & ~B3)) } + A4_O = { ~((SBA & QA4BAR) | (ISBA & ~B4)) } + A5_O = { ~((SBA & QA5BAR) | (ISBA & ~B5)) } + A6_O = { ~((SBA & QA6BAR) | (ISBA & ~B6)) } + A7_O = { ~((SBA & QA7BAR) | (ISBA & ~B7)) } + A8_O = { ~((SBA & QA8BAR) | (ISBA & ~B8)) } + B1_O = { ~((SAB & QB1BAR) | (ISAB & ~A1)) } + B2_O = { ~((SAB & QB2BAR) | (ISAB & ~A2)) } + B3_O = { ~((SAB & QB3BAR) | (ISAB & ~A3)) } + B4_O = { ~((SAB & QB4BAR) | (ISAB & ~A4)) } + B5_O = { ~((SAB & QB5BAR) | (ISAB & ~A5)) } + B6_O = { ~((SAB & QB6BAR) | (ISAB & ~A6)) } + B7_O = { ~((SAB & QB7BAR) | (ISAB & ~A7)) } + B8_O = { ~((SAB & QB8BAR) | (ISAB & ~A8)) } * UAS652DLY PINDLY (16,2,22) DPWR DGND + A1_IO A2_IO A3_IO A4_IO A5_IO A6_IO A7_IO A8_IO B1_IO B2_IO B3_IO B4_IO B5_IO B6_IO B7_IO B8_IO + GBABAR GAB + CBA SBA CAB SAB A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 B7 B8 + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + CLOCK_BA = { CHANGED_LH(CBA,0) } + CLOCK_AB = { CHANGED_LH(CAB,0) } + SEL_BA = { CHANGED(SBA,0) } + SEL_AB = { CHANGED(SAB,0) } + BUS_A = { CHANGED(A1,0) | CHANGED(A2,0) | CHANGED(A3,0) | CHANGED(A4,0) | + CHANGED(A5,0) | CHANGED(A6,0) | CHANGED(A7,0) | CHANGED(A8,0) } + BUS_B = { CHANGED(B1,0) | CHANGED(B2,0) | CHANGED(B3,0) | CHANGED(B4,0) | + CHANGED(B5,0) | CHANGED(B6,0) | CHANGED(B7,0) | CHANGED(B8,0) } + TRISTATE: + ENABLE LO GBABAR + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B = { + CASE( + SEL_BA & TRN_LH, DELAY(2NS,-1,11NS), + SEL_BA & TRN_HL, DELAY(2NS,-1,9NS), + BUS_B & TRN_LH, DELAY(2NS,-1,9NS), + CLOCK_BA & TRN_HL, DELAY(2NS,-1,9NS), + CLOCK_BA & TRN_LH, DELAY(2NS,-1,8.5NS), + BUS_B & TRN_HL, DELAY(1NS,-1,7NS), + TRN_ZH, DELAY(2NS,-1,10NS), + TRN_ZL, DELAY(3NS,-1,16NS), + TRN_$Z, DELAY(2NS,-1,9NS), + DELAY(4NS,-1,17NS) + ) + } + TRISTATE: + ENABLE HI GAB + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B = { + CASE( + SEL_AB & TRN_LH, DELAY(2NS,-1,11NS), + SEL_AB & TRN_HL, DELAY(2NS,-1,9NS), + BUS_A & TRN_LH, DELAY(2NS,-1,9NS), + CLOCK_AB & TRN_HL, DELAY(2NS,-1,9NS), + CLOCK_AB & TRN_LH, DELAY(2NS,-1,8.5NS), + BUS_A & TRN_HL, DELAY(1NS,-1,7NS), + TRN_ZH, DELAY(3NS,-1,11NS), + TRN_ZL, DELAY(3NS,-1,16NS), + TRN_HZ, DELAY(2NS,-1,10NS), + TRN_LZ, DELAY(2NS,-1,11NS), + DELAY(4NS,-1,17NS) + ) + } + FREQ: + NODE = CBA + MAXFREQ = 90MEG + FREQ: + NODE = CAB + MAXFREQ = 90MEG + WIDTH: + NODE = CBA + MIN_LO = 6NS + MIN_HI = 5NS + WIDTH: + NODE = CAB + MIN_LO = 6NS + MIN_HI = 5NS + SETUP_HOLD: + DATA(8) = A1 A2 A3 A4 A5 A6 A7 A8 + CLOCK LH = CAB + SETUPTIME = 6NS + SETUP_HOLD: + DATA(8) = B1 B2 B3 B4 B5 B6 B7 B8 + CLOCK LH = CBA + SETUPTIME = 6NS * .ENDS * *$ *--------- * 74AS756 Octal Buffers and Line Drivers with Open-Collector Outputs * * The ALS/AS Data Book, 1986, TI * atl 7/27/89 Update interface and model names * .subckt 74AS756 GBAR A1 A2 A3 A4 Y1 Y2 Y3 Y4 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 inv DPWR DGND + GBAR G + D_AS756_1 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 nanda(2,4) DPWR DGND + A1 G + A2 G + A3 G + A4 G + Y1 Y2 Y3 Y4 + D_AS756_2 IO_AS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_AS756_1 ugate ( + tphlmx=0.5ns tplhmx=1.5ns + ) .model D_AS756_2 ugate ( + tplhmn=3ns tplhmx=19ns + tphlmn=1ns tphlmx=6ns + ) *$ *------------------------------------------------------------------------- * 74AS757 Octal Buffers and Line Drivers with Open-Collectors Outputs * * The ALS/AS Data Book, 1986, TI * atl 7/27/89 Update interface and model names * .subckt 74AS757 1GBAR 1A1 1A2 1A3 1A4 1Y1 1Y2 1Y3 1Y4 2G 2A1 2A2 2A3 2A4 2Y1 + 2Y2 2Y3 2Y4 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1G buf DPWR DGND + 1GBAR 1GBAR_BUF + D_AS757_1 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U1 ora(2,4) DPWR DGND + 1A1 1GBAR_BUF + 1A2 1GBAR_BUF + 1A3 1GBAR_BUF + 1A4 1GBAR_BUF + 1Y1 1Y2 1Y3 1Y4 + D_AS757_3 IO_AS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2G inv DPWR DGND + 2G 2GBAR + D_AS757_2 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 ora(2,4) DPWR DGND + 2A1 2GBAR + 2A2 2GBAR + 2A3 2GBAR + 2A4 2GBAR + 2Y1 2Y2 2Y3 2Y4 + D_AS757_3 IO_AS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_AS757_1 ugate ( + tplhmx=1.5ns tphlmx=1ns + ) .model D_AS757_2 ugate ( + tplhmx=2.5ns tphlmx=1.5ns + ) .model D_AS757_3 ugate ( + tplhmn=3ns tplhmx=18.5ns + tphlmn=1ns tphlmx=6ns + ) * *$ *--------- * 74AS758 QUADRUPLE BUS TRANSCEIVERS WITH OPEN-COLLECTOR OUTPUTS * * ALS/AS LOGIC CIRCUITS DATA BOOK, 1986, TI * NH 9/1/92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT * .SUBCKT 74AS758 A1_B A2_B A3_B A4_B GABBAR_I GBA_I B1_B B2_B B3_B B4_B + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UAS758LOG LOGICEXP(10,10) DPWR DGND + A1_B A2_B A3_B A4_B GABBAR_I GBA_I B1_B B2_B B3_B B4_B + A1 A2 A3 A4 GABBAR GBA B1 B2 B3 B4 + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} + + LOGIC: * * BUFFER: + GABBAR = { GABBAR_I } + GBA = { GBA_I } + GAB = { ~GABBAR } + * OUTPUT ASSIGNMENTS + A1 = { ~(B1_B & GBA) } + A2 = { ~(B2_B & GBA) } + A3 = { ~(B3_B & GBA) } + A4 = { ~(B4_B & GBA) } + B1 = { ~(A1_B & GAB) } + B2 = { ~(A2_B & GAB) } + B3 = { ~(A3_B & GAB) } + B4 = { ~(A4_B & GAB) } * UAS758DLY PINDLY (8,0,2) DPWR DGND + A1 A2 A3 A4 B1 B2 B3 B4 + GABBAR GBA + A1_B A2_B A3_B A4_B B1_B B2_B B3_B B4_B + IO_AS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + PINDLY: + A1_B A2_B A3_B A4_B = { + CASE( + TRN_LH, DELAY(3NS,-1,19.5NS), + CHANGED(GBA,0) & TRN_HL, DELAY(1NS,-1,7.5NS), + DELAY(1NS,-1,6NS) + ) + } + B1_B B2_B B3_B B4_B = { + CASE( + CHANGED(GABBAR,0) & TRN_LH, DELAY(3NS,-1,21NS), + TRN_LH, DELAY(3NS,-1,19.5NS), + CHANGED(GABBAR,0) & TRN_HL, DELAY(1NS,-1,8NS), + DELAY(1NS,-1,6NS) + ) + } * .ENDS * *$ *------------------------------------------------------------------------- * 74AS759 QUADRUPLE BUS TRANSCEIVERS WITH OPEN-COLLECTOR OUTPUTS * * ALS/AS LOGIC CIRCUITS DATA BOOK, 1986, TI * NH 9/2/92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT * .SUBCKT 74AS759 A1_B A2_B A3_B A4_B GABBAR_I GBA_I B1_B B2_B B3_B B4_B + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UAS759LOG LOGICEXP(10,10) DPWR DGND + A1_B A2_B A3_B A4_B GABBAR_I GBA_I B1_B B2_B B3_B B4_B + A1 A2 A3 A4 GABBAR GBA B1 B2 B3 B4 + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} + + LOGIC: * * BUFFER: + GABBAR = { GABBAR_I } + GBA = { GBA_I } + GAB = { ~GABBAR } + * OUTPUT ASSIGNMENTS + A1 = { ~(~B1_B & GBA) } + A2 = { ~(~B2_B & GBA) } + A3 = { ~(~B3_B & GBA) } + A4 = { ~(~B4_B & GBA) } + B1 = { ~(~A1_B & GAB) } + B2 = { ~(~A2_B & GAB) } + B3 = { ~(~A3_B & GAB) } + B4 = { ~(~A4_B & GAB) } * UAS759DLY PINDLY (8,0,2) DPWR DGND + A1 A2 A3 A4 B1 B2 B3 B4 + GABBAR GBA + A1_B A2_B A3_B A4_B B1_B B2_B B3_B B4_B + IO_AS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + PINDLY: + A1_B A2_B A3_B A4_B = { + CASE( + TRN_LH, DELAY(3NS,-1,20NS), + CHANGED(GBA,0) & TRN_HL, DELAY(1NS,-1,7NS), + DELAY(1NS,-1,6NS) + ) + } + B1_B B2_B B3_B B4_B = { + CASE( + CHANGED(GABBAR,0) & TRN_LH, DELAY(3NS,-1,21NS), + TRN_LH, DELAY(3NS,-1,20NS), + CHANGED(GABBAR,0) & TRN_HL, DELAY(1NS,-1,7.5NS), + DELAY(1NS,-1,6NS) + ) + } * .ENDS * *$ *--------- * 74AS760 Octal Buffers and Line Drivers with Open-Collector Outputs * * The ALS/AS Data Book, 1986, TI * atl 7/27/89 Update interface and model names * .subckt 74AS760 GBAR A1 A2 A3 A4 Y1 Y2 Y3 Y4 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UG buf DPWR DGND + GBAR GBAF + D_AS760_1 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UCTRL ora(2,4) DPWR DGND + A1 GBAF + A2 GBAF + A3 GBAF + A4 GBAF + Y1 Y2 Y3 Y4 + D_AS760_2 IO_AS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_AS760_1 ugate ( + tphlmx=1ns + ) .model D_AS760_2 ugate ( + tplhmn=3ns tplhmx=18.5ns + tphlmn=1ns tphlmx=6ns + ) *$ *--------- * 74AS762 Octal Buffers and Line Drivers with Open-Collector Outputs * * The ALS/AS Data Book, 1986, TI * atl 10/24/89 Update interface and model names * .subckt 74AS762 GBAR A1 A2 A3 A4 Y1 Y2 Y3 Y4 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UG inv DPWR DGND + GBAR G + D_AS762_1 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UY nanda(2,4) DPWR DGND + A1 G + A2 G + A3 G + A4 G + Y1 Y2 Y3 Y4 + D_AS762_2 IO_AS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_AS762_1 ugate ( + tplhmx=1.5ns tphlmx=0.5ns + ) .model D_AS762_2 ugate ( + tplhmn=3ns tplhmx=19ns + tphlmn=1ns tphlmx=6ns + ) *$ *--------- * 74AS763 Octal Buffers and Line Drivers with Open-Collector Outputs * * The ALS/AS Data Book, 1986, TI * atl 7/27/89 Update interface and model names * .subckt 74AS763 1GBAR 1A1 1A2 1A3 1A4 1Y1 1Y2 1Y3 1Y4 2G 2A1 2A2 2A3 2A4 2Y1 + 2Y2 2Y3 2Y4 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1G inv DPWR DGND + 1GBAR 1G + D_AS763_1 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U11 nanda(2,4) DPWR DGND + 1A1 1G + 1A2 1G + 1A3 1G + 1A4 1G + 1Y1 1Y2 1Y3 1Y4 + D_AS763_3 IO_AS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2G buf DPWR DGND + 2G 2G_BUF + D_AS763_2 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U21 nanda(2,4) DPWR DGND + 2A1 2G_BUF + 2A2 2G_BUF + 2A3 2G_BUF + 2A4 2G_BUF + 2Y1 2Y2 2Y3 2Y4 + D_AS763_3 IO_AS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_AS763_1 ugate ( + tphlmx=0.5ns tplhmx=1.5ns + ) .model D_AS763_2 ugate ( + tphlmx=1ns tplhmx=2ns + ) .model D_AS763_3 ugate ( + tplhmn=3ns tplhmx=19ns + tphlmn=1ns tphlmx=6ns + ) *$ *--------- * 74AS804B Hex 2-Input NAND Drivers * * The ALS/AS Data Book, 1986, TI * atl 7/27/89 Update interface and model names * .subckt 74AS804B A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(2) DPWR DGND + A B Y + D_AS804B IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_AS804B ugate ( + tplhmn=1ns tplhmx=4ns + tphlmn=1ns tphlmx=4ns + ) *$ *--------- * 74AS805B Hex 2-Input NOR Drivers * * The ALS/AS Data Book, 1986, TI * atl 7/27/89 Update interface and model names * .subckt 74AS805B A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nor(2) DPWR DGND + A B Y + D_AS805B IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_AS805B ugate ( + tplhmn=1ns tplhmx=4.3ns + tphlmn=1ns tphlmx=4.3ns + ) *$ *--------- * 74AS808B Hex 2-Input AND Drivers * * The ALS/AS Data Book, 1986, TI * atl 7/27/89 Update interface and model names * .subckt 74AS808B A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 and(2) DPWR DGND + A B Y + D_AS808B IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_AS808B ugate ( + tplhmn=1ns tplhmx=6ns + tphlmn=1ns tphlmx=6ns + ) *$ *--------- * 74AS810 Quadruple 2-Input Exclusive-NOR Gates * * The ALS/AS Data Book, 1986, TI * atl 7/27/89 Update interface and model names * .subckt 74AS810 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nxor DPWR DGND + A B Y + D_AS810 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_AS810 ugate ( + tplhty=3.4ns tphlty=5.3ns + ) *$ *--------- * 74AS811 Quadruple 2-Input Exclusive-NOR Gates With Open-Collector Outputs * * The ALS/AS Data Book, 1986, TI * atl 7/27/89 Update interface and model names * .subckt 74AS811 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nxor DPWR DGND + A B Y + D_AS811_1 IO_AS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_AS811_1 ugate ( + tplhty=10ns tphlty=5.7ns + ) *$ *--------- * 74AS821 10-bit Bus Interface Flip-Flops with 3-STATE Outputs * * The ALS/AS Data Book, 1986, TI * atl 7/27/89 Update interface and model names * * Note: Minimum clock width is less than propagation delay, so the width * might not be checked. * .subckt 74AS821 OCBAR CLK 1D 2D 3D 4D 5D 6D 7D 8D 9D 10D 1Q 2Q 3Q 4Q 5Q 6Q + 7Q 8Q 9Q 10Q + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UOC inv DPWR DGND + OCBAR OC + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} UDFF dff(10) DPWR DGND + $D_HI $D_HI CLK + 1D 2D 3D 4D 5D + 6D 7D 8D 9D 10D + 1QQ 2QQ 3QQ 4QQ 5QQ + 6QQ 7QQ 8QQ 9QQ 10QQ + $D_NC $D_NC $D_NC $D_NC $D_NC + $D_NC $D_NC $D_NC $D_NC $D_NC + D_AS821_1 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UOCQ buf3a(10) DPWR DGND + 1QQ 2QQ 3QQ 4QQ 5QQ + 6QQ 7QQ 8QQ 9QQ 10QQ + OC + 1Q 2Q 3Q 4Q 5Q + 6Q 7Q 8Q 9Q 10Q + D_AS821_2 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_AS821_1 ueff ( + twclklmn=8ns twclkhmn=8ns + tsudclkmn=6ns + ) .model D_AS821_2 utgate ( + tplhmn=3.5ns tplhmx=7.5ns + tphlmn=3.5ns tphlmx=10.5ns + tpzhmn=4ns tpzhmx=11ns + tpzlmn=4ns tpzlmx=12ns + tphzmn=2ns tphzmx=8ns + tplzmn=2ns tplzmx=8ns + ) *$ *--------- * 74AS822 10-bit Bus Interface Flip-Flops with 3-STATE Outputs * * The ALS/AS Data Book, 1986, TI * atl 7/27/89 Update interface and model names * * Note: Minimum clock width is less than propagation delay, so the width * might not be checked. * .subckt 74AS822 OCBAR CLK 1DBAR 2DBAR 3DBAR 4DBAR 5DBAR 6DBAR 7DBAR 8DBAR 9DBAR + 10DBAR 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q 10Q + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UOC inv DPWR DGND + OCBAR OC + D0_GATE IO_AS00 UD inva(10) DPWR DGND + 1DBAR 2DBAR 3DBAR 4DBAR 5DBAR + 6DBAR 7DBAR 8DBAR 9DBAR 10DBAR + 1D 2D 3D 4D 5D + 6D 7D 8D 9D 10D + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} UDFF dff(10) DPWR DGND + $D_HI $D_HI CLK + 1D 2D 3D 4D 5D + 6D 7D 8D 9D 10D + 1QQ 2QQ 3QQ 4QQ 5QQ + 6QQ 7QQ 8QQ 9QQ 10QQ + $D_NC $D_NC $D_NC $D_NC $D_NC + $D_NC $D_NC $D_NC $D_NC $D_NC + D_AS822_1 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UOCQ buf3a(10) DPWR DGND + 1QQ 2QQ 3QQ 4QQ 5QQ + 6QQ 7QQ 8QQ 9QQ 10QQ + OC + 1Q 2Q 3Q 4Q 5Q + 6Q 7Q 8Q 9Q 10Q + D_AS822_2 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_AS822_1 ueff ( + twclklmn=8ns twclkhmn=8ns + tsudclkmn=6ns + ) .model D_AS822_2 utgate ( + tplhmn=3.5ns tplhmx=7.5ns + tphlmn=3.5ns tphlmx=10.5ns + tpzhmn=4ns tpzhmx=11ns + tpzlmn=4ns tpzlmx=12ns + tphzmn=2ns tphzmx=8ns + tplzmn=2ns tplzmx=8ns + ) *$ *--------- * 74AS823 9-bit Bus Interface Flip-Flops with 3-STATE Outputs * * The ALS/AS Data Book, 1986, TI * atl 7/27/89 Update interface and model names * .subckt 74AS823 OCBAR CLRBAR CLKENBAR CLK 1D 2D 3D 4D 5D 6D 7D 8D 9D 1Q 2Q + 3Q 4Q 5Q 6Q 7Q 8Q 9Q + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UBUFF buf DPWR DGND + CLK CLK_BUF + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} UA nor(2) DPWR DGND + CLKENBAR B A + D0_GATE IO_AS00 UINV inva(2) DPWR DGND + OCBAR A OC ABAR + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} UAND anda(2,2) DPWR DGND + ABAR CLK_BUF AX CLK_BUF B C1 + D0_GATE IO_AS00 UABX inv DPWR DGND + A ABX + D_AS823_1 IO_AS00 MNTYMXDLY={MNTYMXDLY} UAP nxor DPWR DGND + A ABX AP + D0_GATE IO_AS00 UAPX and(2) DPWR DGND + AP $D_X APX + D0_GATE IO_AS00 UAX xor DPWR DGND + APX A AX + D0_GATE IO_AS00 UDFF dff(9) DPWR DGND + $D_HI CLRBAR C1 + 1D 2D 3D 4D 5D 6D 7D 8D 9D + 1QQ 2QQ 3QQ 4QQ 5QQ 6QQ 7QQ 8QQ 9QQ + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D_AS823_2 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UOCQ buf3a(9) DPWR DGND + 1QQ 2QQ 3QQ 4QQ 5QQ 6QQ 7QQ 8QQ 9QQ + OC + 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q + D_AS823_3 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_AS823_1 ugate ( + tplhmn=6ns tphlmn=6ns + ) .model D_AS823_2 ueff ( + twclklmn=8ns twclkhmn=8ns + twpclmn=4ns tppcqhlmx=2ns + tsudclkmn=6ns tsupcclkhmn=8ns + ) .model D_AS823_3 utgate ( + tplhmn=3.5ns tplhmx=7.5ns + tphlmn=3.5ns tphlmx=11ns + tpzhmn=4ns tpzhmx=11ns + tpzlmn=4ns tpzlmx=12ns + tphzmn=2ns tphzmx=8ns + tplzmn=2ns tplzmx=8ns + ) *$ *--------- * 74AS824 9-bit Bus Interface Flip-Flops with 3-STATE Outputs * * The ALS/AS Data Book, 1986, TI * atl 7/27/89 Update interface and model names * .subckt 74AS824 OCBAR CLRBAR CLKENBAR CLK 1DBAR 2DBAR 3DBAR 4DBAR 5DBAR 6DBAR + 7DBAR 8DBAR 9DBAR 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UBUFF buf DPWR DGND + CLK CLK_BUF + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} UA nor(2) DPWR DGND + CLKENBAR B A + D0_GATE IO_AS00 UINV inva(2) DPWR DGND + OCBAR A OC ABAR + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} UAND anda(2,2) DPWR DGND + ABAR CLK_BUF AX CLK_BUF B C1 + D0_GATE IO_AS00 UABX inv DPWR DGND + A ABX + D_AS824_1 IO_AS00 MNTYMXDLY={MNTYMXDLY} UAP nxor DPWR DGND + A ABX AP + D0_GATE IO_AS00 UAPX and(2) DPWR DGND + AP $D_X APX + D0_GATE IO_AS00 UAX xor DPWR DGND + APX A AX + D0_GATE IO_AS00 UD inva(9) DPWR DGND + 1DBAR 2DBAR 3DBAR 4DBAR 5DBAR 6DBAR 7DBAR 8DBAR 9DBAR + 1D 2D 3D 4D 5D 6D 7D 8D 9D + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} UDFF dff(9) DPWR DGND + $D_HI CLRBAR C1 + 1D 2D 3D 4D 5D 6D 7D 8D 9D + 1QQ 2QQ 3QQ 4QQ 5QQ 6QQ 7QQ 8QQ 9QQ + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D_AS824_2 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UOCQ buf3a(9) DPWR DGND + 1QQ 2QQ 3QQ 4QQ 5QQ 6QQ 7QQ 8QQ 9QQ + OC + 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q + D_AS824_3 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_AS824_1 ugate ( + tplhmn=6ns tphlmn=6ns + ) .model D_AS824_2 ueff ( + twclklmn=8ns twclkhmn=8ns + twpclmn=4ns tppcqhlmx=2ns + tsudclkmn=6ns tsupcclkhmn=8ns + ) .model D_AS824_3 utgate ( + tplhmn=3.5ns tplhmx=7.5ns + tphlmn=3.5ns tphlmx=11ns + tpzhmn=4ns tpzhmx=11ns + tpzlmn=4ns tpzlmx=12ns + tphzmn=2ns tphzmx=8ns + tplzmn=2ns tplzmx=8ns + ) *$ *------------------------------------------------------------------------- * 74AS825 8-bit Bus Interface Flip-Flops with 3-STATE Outputs * * The ALS/AS Data Book, 1986, TI * atl 7/27/89 Update interface and model names * .subckt 74AS825 OC1BAR OC2BAR OC3BAR CLRBAR CLKENBAR CLK 1D 2D 3D 4D 5D 6D + 7D 8D 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UBUFF buf DPWR DGND + CLK CLK_BUF + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} UNOR nora(3,2) DPWR DGND + OC1BAR OC2BAR OC3BAR CLKENBAR B $D_LO OC A + D0_GATE IO_AS00 UABAR inv DPWR DGND + A ABAR + D0_GATE IO_AS00 UAND anda(2,2) DPWR DGND + ABAR CLK_BUF AX CLK_BUF B C1 + D0_GATE IO_AS00 UABX inv DPWR DGND + A ABX + D_AS825_1 IO_AS00 MNTYMXDLY={MNTYMXDLY} UAP nxor DPWR DGND + A ABX AP + D0_GATE IO_AS00 UAPX and(2) DPWR DGND + AP $D_X APX + D0_GATE IO_AS00 UAX xor DPWR DGND + APX A AX + D0_GATE IO_AS00 UDFF dff(8) DPWR DGND + $D_HI CLRBAR C1 + 1D 2D 3D 4D 5D 6D 7D 8D + 1QQ 2QQ 3QQ 4QQ 5QQ 6QQ 7QQ 8QQ + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D_AS825_2 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UOCQ buf3a(8) DPWR DGND + 1QQ 2QQ 3QQ 4QQ 5QQ 6QQ 7QQ 8QQ + OC + 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q + D_AS825_3 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_AS825_1 ugate ( + tplhmn=6ns tphlmn=6ns + ) .model D_AS825_2 ueff ( + twclklmn=8ns twclkhmn=8ns + twpclmn=4ns tppcqhlmx=2ns + tsudclkmn=6ns tsupcclkhmn=8ns + ) .model D_AS825_3 utgate ( + tplhmn=3.5ns tplhmx=7.5ns + tphlmn=3.5ns tphlmx=11ns + tpzhmn=4ns tpzhmx=11ns + tpzlmn=4ns tpzlmx=12ns + tphzmn=2ns tphzmx=8ns + tplzmn=2ns tplzmx=8ns + ) *$ *------------------------------------------------------------------------- * 74AS826 8-bit Bus Interface Flip-Flops with 3-STATE Outputs * * The ALS/AS Data Book, 1986, TI * atl 7/27/89 Update interface and model names * .subckt 74AS826 OC1BAR OC2BAR OC3BAR CLRBAR CLKENBAR CLK 1DBAR 2DBAR 3DBAR + 4DBAR 5DBAR 6DBAR 7DBAR 8DBAR 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UBUFF buf DPWR DGND + CLK CLK_BUF + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} UNOR nora(3,2) DPWR DGND + OC1BAR OC2BAR OC3BAR CLKENBAR B $D_LO OC A + D0_GATE IO_AS00 UABAR inv DPWR DGND + A ABAR + D0_GATE IO_AS00 UAND anda(2,2) DPWR DGND + ABAR CLK_BUF AX CLK_BUF B C1 + D0_GATE IO_AS00 UABX inv DPWR DGND + A ABX + D_AS826_1 IO_AS00 MNTYMXDLY={MNTYMXDLY} UAP nxor DPWR DGND + A ABX AP + D0_GATE IO_AS00 UAPX and(2) DPWR DGND + AP $D_X APX + D0_GATE IO_AS00 UAX xor DPWR DGND + APX A AX + D0_GATE IO_AS00 UD inva(8) DPWR DGND + 1DBAR 2DBAR 3DBAR 4DBAR 5DBAR 6DBAR 7DBAR 8DBAR + 1D 2D 3D 4D 5D 6D 7D 8D + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} UDFF dff(8) DPWR DGND + $D_HI CLRBAR C1 + 1D 2D 3D 4D 5D 6D 7D 8D + 1QQ 2QQ 3QQ 4QQ 5QQ 6QQ 7QQ 8QQ + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D_AS826_2 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UOCQ buf3a(8) DPWR DGND + 1QQ 2QQ 3QQ 4QQ 5QQ 6QQ 7QQ 8QQ + OC + 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q + D_AS826_3 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_AS826_1 ugate ( + tplhmn=6ns tphlmn=6ns + ) .model D_AS826_2 ueff ( + twclklmn=8ns twclkhmn=8ns + twpclmn=4ns tppcqhlmx=2ns + tsudclkmn=6ns tsupcclkhmn=8ns + ) .model D_AS826_3 utgate ( + tplhmn=3.5ns tplhmx=7.5ns + tphlmn=3.5ns tphlmx=11ns + tpzhmn=4ns tpzhmx=11ns + tpzlmn=4ns tpzlmx=12ns + tphzmn=2ns tphzmx=8ns + tplzmn=2ns tplzmx=8ns + ) *$ *--------- * 74AS832B Hex 2-Input OR Drivers * * The ALS/AS Data Book, 1986, TI * atl 7/28/89 Update interface and model names * .subckt 74AS832B A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 or(2) DPWR DGND + A B Y + D_AS832B IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_AS832B ugate ( + tplhmn=1ns tplhmx=6.3ns + tphlmn=1ns tphlmx=6.3ns + ) *$ *--------- * 74AS841 10-bit Bus Interface D-Type Latches with 3-State Outputs * * The ALS/AS Data Book, 1986, TI * atl 10/24/89 Update interface and model names * .subckt 74AS841 OCBAR C 1D 2D 3D 4D 5D 6D 7D 8D 9D 10D 1Q 2Q 3Q 4Q 5Q 6Q 7Q + 8Q 9Q 10Q + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UOC inv DPWR DGND + OCBAR OC + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} UQI dltch(10) DPWR DGND + $D_HI $D_HI C + 1D 2D 3D 4D 5D + 6D 7D 8D 9D 10D + Q1 Q2 Q3 Q4 Q5 + Q6 Q7 Q8 Q9 Q10 + $D_NC $D_NC $D_NC $D_NC $D_NC + $D_NC $D_NC $D_NC $D_NC $D_NC + D_AS841_1 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UQ buf3a(10) DPWR DGND + Q1 Q2 Q3 Q4 Q5 + Q6 Q7 Q8 Q9 Q10 + OC + 1Q 2Q 3Q 4Q 5Q + 6Q 7Q 8Q 9Q 10Q + D_AS841_2 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_AS841_1 ugff ( + twghmn=4ns tsudgmn=2.5ns + thdgmn=2.5ns tpgqlhmn=1ns + tpgqlhmx=5.5ns tpgqhlmn=1ns + tpgqhlmx=3ns + ) .model D_AS841_2 utgate ( + tplhmn=1ns tplhmx=6.5ns + tphlmn=1ns tphlmx=9ns + tpzhmn=2ns tpzhmx=10.5ns + tpzlmn=2ns tpzlmx=13.5ns + tphzmn=1ns tphzmx=8ns + tplzmn=1ns tplzmx=8ns + ) *$ *--------- * 74AS842 10-bit Bus Interface D-Type Latches with 3-STATE Outputs * * The ALS/AS Data Book, 1986, TI * atl 10/25/89 Update interface and model names * .subckt 74AS842 OCBAR C 1DBAR 2DBAR 3DBAR 4DBAR 5DBAR 6DBAR 7DBAR 8DBAR 9DBAR + 10DBAR 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q 10Q + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UOC inv DPWR DGND + OCBAR OC + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} UQI dltch(10) DPWR DGND + $D_HI $D_HI C + 1DBAR 2DBAR 3DBAR 4DBAR 5DBAR + 6DBAR 7DBAR 8DBAR 9DBAR 10DBAR + $D_NC $D_NC $D_NC $D_NC $D_NC + $D_NC $D_NC $D_NC $D_NC $D_NC + Q1 Q2 Q3 Q4 Q5 + Q6 Q7 Q8 Q9 Q10 + D_AS842_1 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UQ buf3a(10) DPWR DGND + Q1 Q2 Q3 Q4 Q5 + Q6 Q7 Q8 Q9 Q10 + OC + 1Q 2Q 3Q 4Q 5Q + 6Q 7Q 8Q 9Q 10Q + D_AS842_2 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_AS842_1 ugff ( + twghmn=4ns tsudgmn=2.5ns + thdgmn=2.5ns tpgqlhmn=1ns + tpgqlhmx=3.5ns tpgqhlmn=1ns + tpgqhlmx=3ns + ) .model D_AS842_2 utgate ( + tplhmn=1ns tplhmx=8.5ns + tphlmn=1ns tphlmx=9ns + tpzhmn=2ns tpzhmx=12ns + tpzlmn=2ns tpzlmx=12.5ns + tphzmn=1ns tphzmx=8ns + tplzmn=1ns tplzmx=8ns + ) *$ *--------- * 74AS843 9-bit Bus Interface D-TYPE Latches with 3-STATE Outputs * * The ALS/AS Data Book, 1986, TI * atl 10/25/89 Update interface and model names * .subckt 74AS843 OCBAR C PREBAR CLRBAR 1D 2D 3D 4D 5D 6D 7D 8D 9D 1Q 2Q 3Q 4Q + 5Q 6Q 7Q 8Q 9Q + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UOC inv DPWR DGND + OCBAR OC + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} UQI dltch(9) DPWR DGND + PREBAR CLRBAR C + 1D 2D 3D 4D 5D 6D 7D 8D 9D + Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D_AS843_1 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UQ buf3a(9) DPWR DGND + Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 + OC + 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q + D_AS843_2 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_AS843_1 ugff ( + twghmn=4ns twpclmn=4ns + tsudgmn=2.5ns thdgmn=2.5ns + tppcqlhmn=1ns tppcqlhmx=3.5ns + tppcqhlmn=1ns tppcqhlmx=4ns + tpgqlhmn=1ns tpgqlhmx=5.5ns + tpgqhlmn=1ns tpgqhlmx=3ns + ) .model D_AS843_2 utgate ( + tplhmn=1ns tplhmx=6.5ns + tphlmn=1ns tphlmx=9ns + tpzhmn=2ns tpzhmx=10.5ns + tpzlmn=2ns tpzlmx=13.5ns + tphzmn=1ns tphzmx=8ns + tplzmn=1ns tplzmx=8ns + ) *$ *--------- * 74AS844 9-bit Bus Interface D-TYPE Latches with 3-STATE Outputs * * The ALS/AS Data Book, 1986, TI * atl 10/26/89 Update interface and model names * .subckt 74AS844 OCBAR C PREBAR CLRBAR 1DBAR 2DBAR 3DBAR 4DBAR 5DBAR 6DBAR 7DBAR + 8DBAR 9DBAR 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UOC inv DPWR DGND + OCBAR OC + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} UQI dltch(9) DPWR DGND + CLRBAR PREBAR C + 1DBAR 2DBAR 3DBAR 4DBAR 5DBAR 6DBAR 7DBAR 8DBAR 9DBAR + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 + D_AS844_1 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UQ buf3a(9) DPWR DGND + Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 + OC + 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q + D_AS844_2 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_AS844_1 ugff ( + twghmn=4ns twpclmn=4ns + tsudgmn=2.5ns thdgmn=2.5ns + tppcqlhmn=1ns tppcqlhmx=1.5ns + tppcqhlmn=1ns tppcqhlmx=3.5ns + tpgqlhmn=1ns tpgqlhmx=4ns + tpgqhlmn=1ns tpgqhlmx=3ns + ) .model D_AS844_2 utgate ( + tplhmn=1ns tplhmx=8.5ns + tphlmn=1ns tphlmx=10ns + tpzhmn=2ns tpzhmx=10ns + tpzlmn=2ns tpzlmx=13.5ns + tphzmn=1ns tphzmx=8ns + tplzmn=1ns tplzmx=8ns + ) *$ *--------- * 74AS845 8-bit Bus Interface D-TYPE Latches with 3-STATE Outputs * * The ALS/AS Data Book, 1986, TI * atl 10/27/89 Update interface and model names * .subckt 74AS845 OCBAR1 OCBAR2 OCBAR3 C PREBAR CLRBAR 1D 2D 3D 4D 5D 6D 7D 8D + 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UOC nor(3) DPWR DGND + OCBAR1 OCBAR2 OCBAR3 OC + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} UQI dltch(8) DPWR DGND + PREBAR CLRBAR C + 1D 2D 3D 4D 5D 6D 7D 8D + Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D_AS845_1 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UQ buf3a(8) DPWR DGND + Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 + OC + 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q + D_AS845_2 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_AS845_1 ugff ( + twghmn=4ns twpclmn=4ns + tsudgmn=2.5ns thdgmn=2.5ns + tppcqlhmn=1ns tppcqlhmx=3.5ns + tppcqhlmn=1ns tppcqhlmx=4ns + tpgqlhmn=1ns tpgqlhmx=5.5ns + tpgqhlmn=1ns tpgqhlmx=3ns + ) .model D_AS845_2 utgate ( + tplhmn=1ns tplhmx=6.5ns + tphlmn=1ns tphlmx=9ns + tpzhmn=2ns tpzhmx=10ns + tpzlmn=2ns tpzlmx=13.5ns + tphzmn=1ns tphzmx=8ns + tplzmn=1ns tplzmx=8ns + ) *$ *--------- * 74AS846 8-bit Bus Interface D-TYPE Latches with 3-STATE Outputs * * The ALS/AS Data Book, 1986, TI * atl 10/27/89 Update interface and model names * .subckt 74AS846 OCBAR1 OCBAR2 OCBAR3 C PREBAR CLRBAR 1DBAR 2DBAR 3DBAR 4DBAR + 5DBAR 6DBAR 7DBAR 8DBAR 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UOC nor(3) DPWR DGND + OCBAR1 OCBAR2 OCBAR3 OC + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} UQI dltch(8) DPWR DGND + CLRBAR PREBAR C + 1DBAR 2DBAR 3DBAR 4DBAR 5DBAR 6DBAR 7DBAR 8DBAR + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 + D_AS846_1 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UQ buf3a(8) DPWR DGND + Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 + OC + 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q + D_AS846_2 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_AS846_1 ugff ( + twghmn=4ns twpclmn=4ns + tsudgmn=2.5ns thdgmn=2.5ns + tppcqlhmn=1ns tppcqlhmx=1.5ns + tppcqhlmn=1ns tppcqhlmx=3.5ns + tpgqlhmn=1ns tpgqlhmx=4ns + tpgqhlmn=1ns tpgqhlmx=3ns + ) .model D_AS846_2 utgate ( + tplhmn=1ns tplhmx=8.5ns + tphlmn=1ns tphlmx=10ns + tpzhmn=2ns tpzhmx=12ns + tpzlmn=2ns tpzlmx=13.5ns + tphzmn=1ns tphzmx=8ns + tplzmn=1ns tplzmx=8ns + ) * *$ *--------- * 74AS857 MULTIPLEXERS UNIVERSAL 2-1 LINE HEX WITH 3-STATE OUTPUTS * * ALS/AS LOGIC DATA BOOK, 1986, TI * TC 08/27/92 REMODELED USING LOGICEXP, PINDLY, & CONSTRAINT DEVICES * .SUBCKT 74AS857 S0_I S1_I COMP_I 1A_I 1B_I 2A_I 2B_I 3A_I 3B_I 4A_I 4B_I + 5A_I 5B_I 6A_I 6B_I 1Y_O 2Y_O 3Y_O 4Y_O 5Y_O 6Y_O OPER_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UAS857LOG LOGICEXP(15,24) DPWR DGND + S0_I S1_I COMP_I 1A_I 1B_I 2A_I 2B_I 3A_I 3B_I 4A_I 4B_I 5A_I 5B_I + 6A_I 6B_I + S0 S1 COMP 1A 1B 2A 2B 3A 3B 4A 4B 5A 5B 6A 6B 1Y 2Y 3Y 4Y 5Y 6Y + OPER OEN1 OEN2 + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} + LOGIC: + S0 = { S0_I } + S1 = { S1_I } + COMP = { COMP_I } + 1A = { 1A_I } + 1B = { 1B_I } + 2A = { 2A_I } + 2B = { 2B_I } + 3A = { 3A_I } + 3B = { 3B_I } + 4A = { 4A_I } + 4B = { 4B_I } + 5A = { 5A_I } + 5B = { 5B_I } + 6A = { 6A_I } + 6B = { 6B_I } + I1B = { ~1B } + I2B = { ~2B } + I3B = { ~3B } + I4B = { ~4B } + I5B = { ~5B } + I6B = { ~6B } + IS0 = { ~S0 } + IS1 = { ~S1 } + ICOMP = { ~COMP } + IOP1 = { 1A | 2A | 3A | 4A | 5A | 6A | S1 | S0 } + IOP2 = { 1B | 2B | 3B | 4B | 5B | 6B | S1 | IS0 } + IY1A = { 1A & IS0 & IS1 & ICOMP } + IY1B = { 1B & S0 & IS1 & ICOMP } + IY1C = { 1A & 1B & IS0 & ICOMP } + IY1D = { ~1A & IS0 & COMP } + IY1E = { I1B & S0 & COMP } + IY1F = { I1B & S1 & COMP } + IY2A = { 2A & IS0 & IS1 & ICOMP } + IY2B = { 2B & S0 & IS1 & ICOMP } + IY2C = { 2A & 2B & IS0 & ICOMP } + IY2D = { ~2A & IS0 & COMP } + IY2E = { I2B & S0 & COMP } + IY2F = { I2B & S1 & COMP } + IY3A = { 3A & IS0 & IS1 & ICOMP } + IY3B = { 3B & S0 & IS1 & ICOMP } + IY3C = { 3A & 3B & IS0 & ICOMP } + IY3D = { ~3A & IS0 & COMP } + IY3E = { I3B & S0 & COMP } + IY3F = { I3B & S1 & COMP } + IY4A = { 4A & IS0 & IS1 & ICOMP } + IY4B = { 4B & S0 & IS1 & ICOMP } + IY4C = { 4A & 4B & IS0 & ICOMP } + IY4D = { ~4A & IS0 & COMP } + IY4E = { I4B & S0 & COMP } + IY4F = { I4B & S1 & COMP } + IY5A = { 5A & IS0 & IS1 & ICOMP } + IY5B = { 5B & S0 & IS1 & ICOMP } + IY5C = { 5A & 5B & IS0 & ICOMP } + IY5D = { ~5A & IS0 & COMP } + IY5E = { I5B & S0 & COMP } + IY5F = { I5B & S1 & COMP } + IY6A = { 6A & IS0 & IS1 & ICOMP } + IY6B = { 6B & S0 & IS1 & ICOMP } + IY6C = { 6A & 6B & IS0 & ICOMP } + IY6D = { ~6A & IS0 & COMP } + IY6E = { I6B & S0 & COMP } + IY6F = { I6B & S1 & COMP } + 1Y = { IY1A | IY1B | IY1C | IY1D | IY1E | IY1F } + 2Y = { IY2A | IY2B | IY2C | IY2D | IY2E | IY2F } + 3Y = { IY3A | IY3B | IY3C | IY3D | IY3E | IY3F } + 4Y = { IY4A | IY4B | IY4C | IY4D | IY4E | IY4F } + 5Y = { IY5A | IY5B | IY5C | IY5D | IY5E | IY5F } + 6Y = { IY6A | IY6B | IY6C | IY6D | IY6E | IY6F } + OPER = { ~(IOP1 & IOP2) } + OEN1 = { ~(S0 & S1 & COMP) } + OEN2 = { ~((COMP & S1) | (IS0 & S1)) } * UAS857DLY PINDLY (7,2,15) DPWR DGND + 1Y 2Y 3Y 4Y 5Y 6Y OPER + OEN1 OEN2 + S0 S1 COMP 1A 1B 2A 2B 3A 3B 4A 4B 5A 5B 6A 6B + 1Y_O 2Y_O 3Y_O 4Y_O 5Y_O 6Y_O OPER_O + IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + SELECT = { CHANGED(S0,0) | CHANGED(S1,0) } + DATA = { CHANGED(1A,0) | CHANGED(1B,0) | CHANGED(2A,0) | CHANGED(2B,0) | + CHANGED(3A,0) | CHANGED(3B,0) | CHANGED(4A,0) | CHANGED(4B,0) | + CHANGED(5A,0) | CHANGED(5B,0) | CHANGED(6A,0) | CHANGED(6B,0) } + COMPLEMENT = { CHANGED(COMP,0) } + TRISTATE: + ENABLE HI OEN1 + 1Y_O 2Y_O 3Y_O 4Y_O 5Y_O 6Y_O = { + CASE( + COMPLEMENT & (TRN_LH | TRN_HL), DELAY(2NS,-1,13NS), + SELECT & (TRN_LH | TRN_HL), DELAY(2NS,-1,13NS), + SELECT & TRN_Z$, DELAY(2NS,-1,12NS), + COMPLEMENT & TRN_Z$, DELAY(2NS,-1,12NS), + DATA & COMP=='1 & (TRN_LH | TRN_HL), DELAY(2NS,-1,12NS), + SELECT & TRN_$Z, DELAY(2NS,-1,11NS), + DATA & COMP=='0 & (TRN_LH | TRN_HL), DELAY(2NS,-1,10NS), + COMPLEMENT & TRN_$Z, DELAY(2NS,-1,9NS), + DELAY(3NS,-1,14NS) + ) + } + TRISTATE: + ENABLE HI OEN2 + OPER_O = { + CASE( + SELECT & (TRN_LH | TRN_HL), DELAY(2NS,-1,18NS), + DATA & (TRN_LH | TRN_HL), DELAY(2NS,-1,14NS), + COMPLEMENT & TRN_Z$, DELAY(2NS,-1,13NS), + SELECT & TRN_Z$, DELAY(2NS,-1,12NS), + SELECT & TRN_$Z, DELAY(2NS,-1,9NS), + COMPLEMENT & TRN_$Z, DELAY(2NS,-1,9NS), + DELAY(3NS,-1,19NS) + ) + } * .ENDS * *$ *--------- * 74AS874 Dual 4-bit D-TYPE Edge-Triggered Flip-Flops * * The ALS/AS Data Book, 1986, TI * atl 7/28/89 Update interface and model names * .subckt 74AS874 OCBAR CLK CLRBAR D1 D2 D3 D4 Q1 Q2 Q3 Q4 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UOC inv DPWR DGND + OCBAR OC + D0_GATE IO_AS00 IO_LEVEL={IO_LEVEL} UDFF dff(4) DPWR DGND + $D_HI CLRBAR CLK + D1 D2 D3 D4 + 1QQ 2QQ 3QQ 4QQ $D_NC $D_NC $D_NC $D_NC + D_AS874_1 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UOCQ buf3a(4) DPWR DGND + 1QQ 2QQ 3QQ 4QQ OC Q1 Q2 Q3 Q4 + D_AS874_2 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_AS874_1 ueff ( + twclklmn=4ns twclkhmn=3ns + twpclmn=2ns tsudclkmn=2ns + tsupcclkhmn=4ns tppcqhlmx=1ns + thdclkmn=1ns tpclkqhlmx=2ns + ) .model D_AS874_2 utgate ( + tplhmn=3ns tplhmx=8.5ns + tphlmn=4ns tphlmx=8.5ns + tpzhmn=2ns tpzhmx=7ns + tpzlmn=3ns tpzlmx=10.5ns + tphzmn=2ns tphzmx=6ns + tplzmn=2ns tplzmx=7.5ns + ) * *$ *------------------------------------------------------------------------- * 74AS881A ALU / FUNCTION GENERATOR * * ALS/AS LOGIC CIRCUITS DATA BOOK, 1986, TI * JLS 9-11-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES .SUBCKT 74AS881A A0BAR_I A1BAR_I A2BAR_I A3BAR_I B0BAR_I B1BAR_I B2BAR_I + B3BAR_I S0_I S1_I S2_I S3_I M_I CN_I F0BAR_O F1BAR_O F2BAR_O F3BAR_O + AEQUALB_O PBAR_O GBAR_O CN+4_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 UAS881ALOG LOGICEXP (14,22) DPWR DGND + A0BAR_I A1BAR_I A2BAR_I A3BAR_I B0BAR_I B1BAR_I B2BAR_I B3BAR_I + S0_I S1_I S2_I S3_I M_I CN_I + A0BAR A1BAR A2BAR A3BAR B0BAR B1BAR B2BAR B3BAR + S0 S1 S2 S3 M CN + F0BAR F1BAR F2BAR F3BAR AEQUALB PBAR GBAR CN+4 + D0_GATE IO_AS00 + IO_LEVEL={IO_LEVEL} + + LOGIC: + A0BAR = { A0BAR_I } + A1BAR = { A1BAR_I } + A2BAR = { A2BAR_I } + A3BAR = { A3BAR_I } + B0BAR = { B0BAR_I } + B1BAR = { B1BAR_I } + B2BAR = { B2BAR_I } + B3BAR = { B3BAR_I } + S0 = { S0_I } + S1 = { S1_I } + S2 = { S2_I } + S3 = { S3_I } + M = { M_I } + CN = { CN_I } + + TOP3 = { ~( (A3BAR & B3BAR & S3) | (A3BAR & ~B3BAR & S2) ) } + BOT3 = { ~( (~B3BAR & S1) | A3BAR | (B3BAR & S0) ) } + TOP2 = { ~( (A2BAR & B2BAR & S3) | (A2BAR & ~B2BAR & S2) ) } + BOT2 = { ~( (~B2BAR & S1) | A2BAR | (B2BAR & S0) ) } + TOP1 = { ~( (A1BAR & B1BAR & S3) | (A1BAR & ~B1BAR & S2) ) } + BOT1 = { ~( (~B1BAR & S1) | A1BAR | (B1BAR & S0) ) } + TOP0 = { ~( (A0BAR & B0BAR & S3) | (A0BAR & ~B0BAR & S2) ) } + BOT0 = { ~( (~B0BAR & S1) | A0BAR | (B0BAR & S0) ) } + MBAR = { ~M } + + F3BAR = { (TOP3 ^ BOT3) ^ ~( ( CN & MBAR & TOP2 & TOP1 & TOP0) | + (BOT0 & MBAR & TOP2 & TOP1) | + (BOT1 & MBAR & TOP2) | + (BOT2 & MBAR) ) } + F2BAR = { (TOP2 ^ BOT2) ^ ~( ( CN & MBAR & TOP1 & TOP0) | + (BOT0 & MBAR & TOP1) | + (BOT1 & MBAR) ) } + F1BAR = { (TOP1 ^ BOT1) ^ ~( ( CN & MBAR & TOP0) | + (BOT0 & MBAR) ) } + F0BAR = { (TOP0 ^ BOT0) ^ ~( CN & MBAR) } + AEQUALB = { F3BAR & F2BAR & F1BAR & F0BAR } + PBAR = { ~( (M & F3BAR & F2BAR & F1BAR & F0BAR) | + (MBAR & TOP3 & TOP2 & TOP1 & TOP0) ) } + GBAR = { ~(MBAR & ((BOT0 & TOP3 & TOP2 & TOP1) | + (BOT1 & TOP3 & TOP2) | + (BOT2 & TOP3) | + BOT3) ) } + CN+4 = { ~GBAR | (~PBAR & CN) } UAS881ADLY PINDLY (7,0,14) DPWR DGND + F0BAR F1BAR F2BAR F3BAR PBAR GBAR CN+4 + A0BAR A1BAR A2BAR A3BAR B0BAR B1BAR B2BAR B3BAR S0 S1 S2 S3 M CN + F0BAR_O F1BAR_O F2BAR_O F3BAR_O PBAR_O GBAR_O CN+4_O + IO_AS00 + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + CARRY = { CHANGED(CN,0) } + OPER = { CHANGED(A3BAR,0) | CHANGED(B3BAR,0) | + CHANGED(A2BAR,0) | CHANGED(B2BAR,0) | + CHANGED(A1BAR,0) | CHANGED(B1BAR,0) | + CHANGED(A0BAR,0) | CHANGED(B0BAR,0) } + NOTM = { M=='0 } + NINE = { S0=='1 & S1=='0 & S2=='0 & S3=='1 } + SUM = { OPER & NOTM & NINE } + DIF = { OPER & NOTM & S0=='0 & S1=='1 & S2=='1 & S3=='0 } + CHECK1 = { CN=='1 & M=='1 & NINE } + + PINDLY: + F0BAR_O F1BAR_O F2BAR_O F3BAR_O = { + CASE ( + NOTM & CARRY, DELAY(3NS,6NS, 9NS), + SUM , DELAY(2NS,5NS, 8NS), + DIF , DELAY(2NS,6NS,10NS), + DELAY(2NS,6NS,11NS) + ) + } + PBAR_O = { + CASE ( + SUM , DELAY(2NS, 6NS, 8NS), + DIF , DELAY(2NS, 6NS,10NS), + CHECK1, DELAY(2NS,10NS,15NS), + DELAY(2NS,10NS,15NS) + ) + } + GBAR_O = { + CASE ( + SUM , DELAY(2NS, 5NS, 7NS), + DIF , DELAY(2NS, 6NS, 9NS), + DELAY(2NS,6NS,9NS) + ) + } + CN+4_O = { + CASE ( + CARRY, DELAY(2NS,7NS, 9NS), + SUM , DELAY(2NS,8NS,12NS), + DIF , DELAY(2NS,8NS,16NS), + CHECK1, DELAY(2NS,12NS,18NS), + DELAY(2NS,13NS,19NS) + ) + } UAS881ADLY_OC PINDLY (1,0,13) DPWR DGND + AEQUALB + A0BAR A1BAR A2BAR A3BAR B0BAR B1BAR B2BAR B3BAR S0 S1 S2 S3 M + AEQUALB_O + IO_AS00_OC + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + PINDLY: + AEQUALB_O = { DELAY(4NS,14NS,21NS) } .ENDS *$ *------------------------------------------------------------------------- * 74AS882A LOOK-AHEAD CARRY GENERATOR * * ALS/AS LOGIC CIRCUITS DATA BOOK, 1986, TI * JLS 9-18-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES * .SUBCKT 74AS882A CN_I + P0BAR_I P1BAR_I P2BAR_I P3BAR_I P4BAR_I P5BAR_I P6BAR_I P7BAR_I + G0BAR_I G1BAR_I G2BAR_I G3BAR_I G4BAR_I G5BAR_I G6BAR_I G7BAR_I + CN+8_O CN+16_O CN+24_O CN+32_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UAS882ALOG LOGICEXP (17,5) DPWR DGND + P0BAR_I P1BAR_I P2BAR_I P3BAR_I P4BAR_I P5BAR_I P6BAR_I P7BAR_I + G0BAR_I G1BAR_I G2BAR_I G3BAR_I G4BAR_I G5BAR_I G6BAR_I G7BAR_I CN_I + CN CN+8 CN+16 CN+24 CN+32 + D0_GATE IO_AS00 + IO_LEVEL={IO_LEVEL} + + LOGIC: + P0BAR = { P0BAR_I } + P1BAR = { P1BAR_I } + P2BAR = { P2BAR_I } + P3BAR = { P3BAR_I } + P4BAR = { P4BAR_I } + P5BAR = { P5BAR_I } + P6BAR = { P6BAR_I } + P7BAR = { P7BAR_I } + G0BAR = { G0BAR_I } + G1BAR = { G1BAR_I } + G2BAR = { G2BAR_I } + G3BAR = { G3BAR_I } + G4BAR = { G4BAR_I } + G5BAR = { G5BAR_I } + G6BAR = { G6BAR_I } + G7BAR = { G7BAR_I } + CN = { CN_I } + + STEP08 = { G0BAR & G1BAR } + W08C = { ~CN & STEP08 } + W080 = { P0BAR & STEP08 } + W081 = { P1BAR & G1BAR } + STEP16 = { G2BAR & G3BAR } + W16C = { W08C & STEP16 } + W160 = { W080 & STEP16 } + W161 = { W081 & STEP16 } + W162 = { P2BAR & STEP16 } + W163 = { P3BAR & G3BAR } + STEP24 = { G4BAR & G5BAR } + W24C = { W16C & STEP24 } + W240 = { W160 & STEP24 } + W241 = { W161 & STEP24 } + W242 = { W162 & STEP24 } + W243 = { W163 & STEP24 } + W244 = { P4BAR & STEP24 } + W245 = { P5BAR & G5BAR } + STEP32 = { G6BAR & G7BAR } + W32C = { W24C & STEP32 } + W320 = { W240 & STEP32 } + W321 = { W241 & STEP32 } + W322 = { W242 & STEP32 } + W323 = { W243 & STEP32 } + W324 = { W244 & STEP32 } + W325 = { W245 & STEP32 } + W326 = { P6BAR & STEP32 } + W327 = { P7BAR & G7BAR } + + CN+8 = { ~(W08C | W080 | W081) } + CN+16 = { ~(W16C | W160 | W161 | W162 | W163) } + CN+24 = { ~(W24C | W240 | W241 | W242 | W243 | W244 | W245) } + CN+32 = { ~(W32C | W320 | W321 | W322 | W323 | W324 | W325 | W326 | W327) } * UAS882ADLY PINDLY (4,0,1) DPWR DGND + CN+8 CN+16 CN+24 CN+32 + CN + CN+8_O CN+16_O CN+24_O CN+32_O + IO_AS00 + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + CARRY = { CHANGED(CN,0) } + + PINDLY: + CN+8_O CN+16_O = { + CASE ( + CARRY & TRN_LH, DELAY(2NS,-1, 9NS), + CARRY & TRN_HL, DELAY(3NS,-1,14NS), + DELAY(2NS,-1, 7NS) + ) + } + CN+24_O = { + CASE ( + CARRY & TRN_LH, DELAY(2NS,-1, 9NS), + CARRY & TRN_HL, DELAY(3NS,-1,14NS), + TRN_LH, DELAY(2NS,-1, 7NS), + TRN_HL, DELAY(2NS,-1,10NS), + DELAY(3NS,-1,14NS) + ) + } + CN+32_O = { + CASE ( + CARRY & TRN_LH, DELAY(2NS,-1, 9NS), + CARRY & TRN_HL, DELAY(3NS,-1,14NS), + TRN_LH, DELAY(2NS,-1, 8NS), + TRN_HL, DELAY(2NS,-1,12NS), + DELAY(3NS,-1,14NS) + ) + } * .ENDS * *$ *--------- * 74AS1000A Quadruple 2-Input Positive-NAND Buffers * * The ALS/AS Data Book, 1986, TI * atl 7/28/89 Update interface and model names * .subckt 74AS1000A A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(2) DPWR DGND + A B Y + D_AS1000A IO_AS000 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_AS1000A ugate ( + tplhmn=1ns tplhmx=4ns + tphlmn=1ns tphlmx=4ns + ) *$ *--------- * 74AS1004A Hex Inverting Drivers * * The ALS/AS Data Book, 1986, TI * atl 7/28/89 Update interface and model names * .subckt 74AS1004A A Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 inv DPWR DGND + A Y + D_AS1004A IO_AS000 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_AS1004A ugate ( + tplhmn=1ns tplhmx=4ns + tphlmn=1ns tphlmx=4ns + ) *$ *--------- * 74AS1008A Quadruple 2-Input Positive-AND Buffers/Drivers * * The ALS/AS Data Book, 1986, TI * atl 7/28/89 Update interface and model names * .subckt 74AS1008A A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 and(2) DPWR DGND + A B Y + D_AS1008A IO_AS000 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_AS1008A ugate ( + tplhmn=1ns tplhmx=6ns + tphlmn=1ns tphlmx=6ns + ) *$ *--------- * 74AS1032A Quadruple 2-Input Positive-OR Buffers * * The ALS/AS Data Book, 1986, TI * atl 7/28/89 Update interface and model names * .subckt 74AS1032A A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 or(2) DPWR DGND + A B Y + D_AS1032A IO_AS000 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_AS1032A ugate ( + tplhmn=1ns tplhmx=6.3ns + tphlmn=1ns tphlmx=6.3ns + ) *$ *--------- * 74AS1034A Hex Drivers * * The ALS/AS Data Book, 1986, TI * atl 7/28/89 Update interface and model names * .subckt 74AS1034A A Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 buf DPWR DGND + A Y + D_AS1034A IO_AS000 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_AS1034A ugate ( + tplhmn=1ns tplhmx=6ns + tphlmn=1ns tphlmx=6ns + ) *$ *------------------------------------------------------------------------- * 74AS1036A Quadruple 2-Input Positive-NOR Drivers * * The ALS/AS Data Book, 1986, TI * atl 7/28/89 Update interface and model names * .subckt 74AS1036A A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nor(2) DPWR DGND + A B Y + D_AS1036A IO_AS000 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_AS1036A ugate ( + tplhmn=1ns tplhmx=4.3ns + tphlmn=1ns tphlmx=4.3ns + ) *$