* Library of 74ALS Family Digital Models * * Copyright OrCAD, Inc. 1998 All Rights Reserved. * * * $Revision: 1.3 $ * $Author: RPEREZ $ * $Date: 16 Apr 1998 14:15:06 $ * * *$ *--------- * 74ALS00A Quadruple 2-input Positive-Nand Gates * * The ALS/AS Data Book, 1986, TI * tdn 06/23/89 Update interface and model names * .subckt 74ALS00A A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(2) DPWR DGND + A B Y + D_ALS00A IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS00A ugate ( + tplhty=7ns tphlty=5ns + tplhmn=3ns tplhmx=11ns + tphlmn=2ns tphlmx=8ns + ) *$ *--------- * 74ALS01 Quadruple 2-input Positive-Nand Gates with Open-Collector Outputs * * The ALS/AS Data Book, 1986, TI * tdn 06/23/89 Update interface and model names * .subckt 74ALS01 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(2) DPWR DGND + A B Y + D_ALS01 IO_ALS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS01 ugate ( + tplhmn=23ns tplhmx=54ns + tphlmn=8ns tphlmx=28ns + ) *$ *--------- * 74ALS02 Quadruple 2-input Positive-Nor Gates * * The ALS/AS Data Book, 1986, TI * tdn 06/23/89 Update interface and model names * .subckt 74ALS02 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nor(2) DPWR DGND + A B Y + D_ALS02 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS02 ugate ( + tplhty=7ns tphlty=5ns + tplhmn=3ns tplhmx=12ns + tphlmn=3ns tphlmx=10ns + ) *$ *--------- * 74ALS03B Quadruple 2-input Positive-Nand Gates with Open-Collector Outputs * * The ALS/AS Data Book, 1986, TI * tdn 06/23/89 Update interface and model names * .subckt 74ALS03B A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(2) DPWR DGND + A B Y + D_ALS03B IO_ALS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS03B ugate ( + tplhty=35ns tphlty=8ns + tplhmn=20ns tplhmx=50ns + tphlmn=3ns tphlmx=13ns + ) *$ *--------- * 74ALS04B Hex Inverters * * The ALS/AS Data Book, 1986, TI * tdn 06/23/89 Update interface and model names * .subckt 74ALS04B A Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 inv DPWR DGND + A Y + D_ALS04B IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS04B ugate ( + tplhmn=3ns tplhmx=11ns + tphlmn=2ns tphlmx=8ns + ) *$ *--------- * 74ALS05A Hex Inverters with Open-Collector Outputs * * The ALS/AS Data Book, 1986, TI * tdn 06/23/89 Update interface and model names * .subckt 74ALS05A A Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 inv DPWR DGND + A Y + D_ALS05A IO_ALS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS05A ugate ( + tplhty=45ns tphlty=9ns + tplhmn=23ns tplhmx=54ns + tphlmn=4ns tphlmx=14ns + ) *$ *--------- * 74ALS08 Quadruple 2-input Positive-And Gates * * The ALS/AS Data Book, 1986, TI * tdn 06/23/89 Update interface and model names * .subckt 74ALS08 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 and(2) DPWR DGND + A B Y + D_ALS08 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS08 ugate ( + tplhty=8ns tphlty=6.5ns + tplhmn=4ns tplhmx=14ns + tphlmn=3ns tphlmx=10ns + ) *$ *--------- * 74ALS09 Quadruple 2-input Positive-And Gates with Open-Collector Outputs * * The ALS/AS Data Book, 1986, TI * tdn 06/23/89 Update interface and model names * .subckt 74ALS09 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 and(2) DPWR DGND + A B Y + D_ALS09 IO_ALS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS09 ugate ( + tplhmn=23ns tplhmx=54ns + tphlmn=5ns tphlmx=15ns + ) *$ *--------- * 74ALS10A Triple 3-input Positive-Nand Gates * * The ALS/AS Data Book, 1986, TI * tdn 06/23/89 Update interface and model names * .subckt 74ALS10A A B C Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(3) DPWR DGND + A B C Y + D_ALS10A IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS10A ugate ( + tplhmn=2ns tplhmx=11ns + tphlmn=2ns tphlmx=10ns + ) *$ *--------- * 74ALS11A Triple 3-input Positive-And Gates * * The ALS/AS Data Book, 1986, TI * tdn 06/23/89 Update interface and model names * .subckt 74ALS11A A B C Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 and(3) DPWR DGND + A B C Y + D_ALS11A IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS11A ugate ( + tplhmn=2ns tplhmx=13ns + tphlmn=2ns tphlmx=10ns + ) *$ *--------- * 74ALS12A Triple 3-input Positive-Nand Gates with Open-Collector Outputs * * The ALS/AS Data Book, 1986, TI * tdn 06/23/89 Update interface and model names * .subckt 74ALS12A A B C Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(3) DPWR DGND + A B C Y + D_ALS12A IO_ALS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS12A ugate ( + tplhmn=23ns tplhmx=54ns + tphlmn=5ns tphlmx=18ns + ) *$ *------------------------------------------------------------------------- * 74ALS15A Triple 3-input Positive-And Gates with Open-Collector Outputs * * The ALS/AS Data Book, 1986, TI * tdn 06/26/89 Update interface and model names * .subckt 74ALS15A A B C Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 and(3) DPWR DGND + A B C Y + D_ALS15A IO_ALS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS15A ugate ( + tplhmn=20ns tplhmx=45ns + tphlmn=6ns tphlmx=20ns + ) *$ *--------- * 74ALS20A Dual 4-input Positive-Nand Gates * * The ALS/AS Data Book, 1986, TI * tdn 06/26/89 Update interface and model names * .subckt 74ALS20A A B C D Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(4) DPWR DGND + A B C D Y + D_ALS20A IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS20A ugate ( + tplhty=7ns tphlty=6ns + tplhmn=3ns tplhmx=11ns + tphlmn=3ns tphlmx=10ns + ) *$ *--------- * 74ALS21A Dual 4-input Positive-And Gates * * The ALS/AS Data Book, 1986, TI * tdn 06/26/89 Update interface and model names * .subckt 74ALS21A A B C D Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 and(4) DPWR DGND + A B C D Y + D_ALS21A IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS21A ugate ( + tplhty=8.3ns tphlty=6.5ns + tplhmn=4ns tplhmx=15ns + tphlmn=2ns tphlmx=10ns + ) *$ *--------- * 74ALS22B Dual 4-input Positive-Nand Gates with Open-Collector Outputs * * The ALS/AS Data Book, 1986, TI * tdn 06/26/89 Update interface and model names * .subckt 74ALS22B A B C D Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(4) DPWR DGND + A B C D Y + D_ALS22B IO_ALS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS22B ugate ( + tplhty=35ns tphlty=8ns + tplhmn=23ns tplhmx=45ns + tphlmn=4ns tphlmx=18ns + ) *$ *--------- * 74ALS27 Triple 3-input Positive-Nor Gates * * The ALS/AS Data Book, 1986, TI * tdn 06/26/89 Update interface and model names * .subckt 74ALS27 A B C Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nor(3) DPWR DGND + A B C Y + D_ALS27 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS27 ugate ( + tplhmn=4ns tplhmx=15ns + tphlmn=3ns tphlmx=9ns + ) *$ *--------- * 74ALS28A Quadruple 2-input Positive-Nor Buffers * * The ALS/AS Data Book, 1986, TI * tdn 06/26/89 Update interface and model names * .subckt 74ALS28A A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nor(2) DPWR DGND + A B Y + D_ALS28A IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS28A ugate ( + tplhty=4ns tphlty=4ns + tplhmn=2ns tplhmx=8ns + tphlmn=2ns tphlmx=7ns + ) *$ *--------- * 74ALS30A 8-input Positive-Nand Gates * * The ALS/AS Data Book, 1986, TI * tdn 06/26/89 Update interface and model names * .subckt 74ALS30A A B C D E F G H Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(8) DPWR DGND + A B C D E F G H Y + D_ALS30A IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS30A ugate ( + tplhmn=3ns tplhmx=10ns + tphlmn=3ns tphlmx=12ns + ) *$ *--------- * 74ALS32 Quadruple 2-input Positive-Or Gates * * The ALS/AS Data Book, 1986, TI * tdn 06/26/89 Update interface and model names * .subckt 74ALS32 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 or(2) DPWR DGND + A B Y + D_ALS32 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS32 ugate ( + tplhty=8.8ns tphlty=6.8ns + tplhmn=3ns tplhmx=14ns + tphlmn=3ns tphlmx=12ns + ) *$ *--------- * 74ALS33A Quadruple 2-input Positive-Nor Buffers w/ Open-Collector Outputs * * The ALS/AS Data Book, 1986, TI * tdn 06/26/89 Update interface and model names * .subckt 74ALS33A A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nor(2) DPWR DGND + A B Y + D_ALS33A IO_ALS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS33A ugate ( + tplhty=18ns tphlty=7ns + tplhmn=10ns tplhmx=33ns + tphlmn=2ns tphlmx=12ns + ) *$ *------------------------------------------------------------------------- * 74ALS34 Hex Noninverters * * The ALS/AS Data Book, 1986, TI * tdn 06/26/89 Update interface and model names * .subckt 74ALS34 A Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 buf DPWR DGND + A Y + D_ALS34 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS34 ugate ( + tplhty=9.4ns tphlty=5ns + tplhmn=4ns tplhmx=15ns + tphlmn=1ns tphlmx=10ns + ) *$ *------------------------------------------------------------------------- * 74ALS35A Hex Noninverters with Open-Collector Outputs * * The ALS/AS Data Book, 1986, TI * tdn 06/26/89 Update interface and model names * .subckt 74ALS35A A Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 buf DPWR DGND + A Y + D_ALS35A IO_ALS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS35A ugate ( + tplhty=34ns tphlty=9ns + tplhmn=20ns tplhmx=50ns + tphlmn=2ns tphlmx=14ns + ) *$ *--------- * 74ALS37A Quadruple 2-input Positive-Nand Buffers * * The ALS/AS Data Book, 1986, TI * tdn 06/26/89 Update interface and model names * .subckt 74ALS37A A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(2) DPWR DGND + A B Y + D_ALS37A IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS37A ugate ( + tplhty=4ns tphlty=5ns + tplhmn=2ns tplhmx=8ns + tphlmn=2ns tphlmx=7ns + ) *$ *--------- * 74ALS38A Quadruple 2-input Positive-Nand Buffers w/ Open-Collector Outputs * * The ALS/AS Data Book, 1986, TI * tdn 06/26/89 Update interface and model names * .subckt 74ALS38A A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(2) DPWR DGND + A B Y + D_ALS38A IO_ALS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS38A ugate ( + tplhty=18ns tphlty=7ns + tplhmn=10ns tplhmx=33ns + tphlmn=2ns tphlmx=12ns + ) *$ *--------- * 74ALS40A Dual 4-input Positive-Nand Buffers * * The ALS/AS Data Book, 1986, TI * tdn 06/26/89 Update interface and model names * .subckt 74ALS40A A B C D Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(4) DPWR DGND + A B C D Y + D_ALS40A IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS40A ugate ( + tplhty=5ns tphlty=5ns + tplhmn=2ns tplhmx=8ns + tphlmn=2ns tphlmx=7ns + ) *$ *--------- * 74ALS74A Dual D-Type Positive-Edge-Triggered Flip-Flops w/ Preset & Clear * * The ALS/AS Data Book, 1986, TI * tdn 06/28/89 Update interface and model names * .subckt 74ALS74A 1CLRBAR 1D 1CLK 1PREBAR 1Q 1QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UFF1 dff(1) DPWR DGND + 1PREBAR 1CLRBAR 1CLK 1D 1Q 1QBAR + D_ALS74A IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS74A ueff ( + twpclmn=15ns twclklmn=14.5ns + twclkhmn=14.5ns tsudclkmn=15ns + tsupcclkhmn=10ns thdclkmn=0ns + tppcqlhmn=3ns tppcqlhmx=13ns + tppcqhlmn=5ns tppcqhlmx=15ns + tpclkqlhmn=5ns tpclkqlhmx=16ns + tpclkqhlmn=5ns tpclkqhlmx=18ns + ) *$ *--------- * 74ALS86 Quadruple 2-input Exclusive-Or Gates * * The ALS/AS Data Book, 1986, TI * tdn 06/29/89 Update interface and model names * .subckt 74ALS86 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(2) DPWR DGND + A B A_BUF B_BUF + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} U1 or(2) DPWR DGND + A_BUF B_BUF C + D_ALS86_1 IO_ALS00 MNTYMXDLY={MNTYMXDLY} U2 nand(2) DPWR DGND + A_BUF B_BUF D + D_ALS86_2 IO_ALS00 MNTYMXDLY={MNTYMXDLY} U3 and(2) DPWR DGND + C D Y + D_ALS86_3 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS86_1 ugate ( + tplhmn=1ns tplhmx=15ns + tphlmn=0ns tphlmx=10ns + ) .model D_ALS86_2 ugate ( + tplhmn=1ns tplhmx=15ns + tphlmn=0ns tphlmx=8ns + ) .model D_ALS86_3 ugate ( + tplhmn=2ns tplhmx=2ns + tphlmn=2ns tphlmx=2ns + ) *$ *--------- * 74ALS109A Dual J-KBar Positive-Edge-Triggered Flip-Flops w/ Set & Reset * * Philips Components, 1989 * cv 08/20/90 Created from LS * .subckt 74ALS109A CP SDBAR RDBAR J KBAR Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 jkff(1) DPWR DGND + SDBAR RDBAR CPBAR J K Q QBAR + D_ALS109A IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 inva(2) DPWR DGND + KBAR CP K CPBAR + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} .ends * .model D_ALS109A ueff ( + tppcqlhmn=1ns tppcqlhmx=8ns + tppcqhlmn=3ns tppcqhlmx=10ns + tpclkqlhmn=3ns tpclkqlhmx=14ns + tpclkqhlmn=3ns tpclkqhlmx=14ns + twclkhmn=6ns twclklmn=6ns + twpclmn=6ns tsudclkmn=6ns + tsupcclkhmn=6ns thdclkmn=0ns + ) *$ *--------- * 74ALS112A Dual J-K Negative-Edge-Triggered Flip-Flops with Set & Reset * * Philips Components, 1989 * cv 08/20/90 Created from LS * * .subckt 74ALS112A CP SDBAR RDBAR J K Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 jkff(1) DPWR DGND + SDBAR RDBAR CP J K Q QBAR + D_ALS112A IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS112A ueff ( + tppcqlhmn=3ns tppcqlhmx=15ns + tppcqhlmn=4ns tppcqhlmx=18ns + tpclkqlhmn=3ns tpclkqlhmx=15ns + tpclkqhlmn=5ns tpclkqhlmx=19ns + twclkhmn=16.5ns twclkhmx=16.5ns + twclklmx=16.5ns twclklmn=16.5ns + twpclmx=10ns twpclmn=10ns + tsudclkmx=22ns tsudclkmn=22ns + tsupcclkhmx=20ns tsupcclkhmn=20ns + thdclkmn=0ns thdclkmx=0ns + ) *$ *------------------------------------------------------------------------- * 74ALS133 13-input Positive-Nand Gates * * The ALS/AS Data Book, 1986, TI * tdn 07/05/89 Update interface and model names * .subckt 74ALS133 A B C D E F G H I J K L M Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(13) DPWR DGND + A B C D E F G H I + J K L M + Y + D_ALS133 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS133 ugate ( + tplhty=8ns tphlty=17ns + tplhmn=3ns tplhmx=11ns + tphlmn=5ns tphlmx=25ns + ) *$ *--------- * 74ALS136 Quadruple 2-input Exclusive-Or Gates with Open-Collector Outputs * * The ALS/AS Data Book, 1986, TI * tdn 07/05/89 Update interface and model names * .subckt 74ALS136 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(2) DPWR DGND + A B A_BUF B_BUF + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} U1 or(2) DPWR DGND + A_BUF B_BUF C + D_ALS136_1 IO_ALS00 MNTYMXDLY={MNTYMXDLY} U2 nand(2) DPWR DGND + A_BUF B_BUF D + D_ALS136_2 IO_ALS00 MNTYMXDLY={MNTYMXDLY} U3 and(2) DPWR DGND + C D Y + D_ALS136_3 IO_ALS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends 74ALS136 * .model D_ALS136_1 ugate ( + tplhmn=18ns tplhmx=48ns + tphlmn=1ns tphlmx=13ns + ) .model D_ALS136_2 ugate ( + tplhmn=18ns tplhmx=48ns + tphlmn=1ns tphlmx=10ns + ) .model D_ALS136_3 ugate ( + tplhmn=2ns tplhmx=2ns + tphlmn=2ns tphlmx=2ns + ) *$ *------------------------------------------------------------------------- * 74ALS137 DECODER/DEMULTIPLEXER 3-8 LINE WITH ADDRESS LATCHES * * ALS/AS LOGIC CIRCUITS DATA BOOK, 1986, TI * JLS 8-4-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES * .SUBCKT 74ALS137 G1_I G2BAR_I GLBAR_I A_I B_I C_I + Y0_O Y1_O Y2_O Y3_O Y4_O Y5_O Y6_O Y7_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 DLTCH(3) DPWR DGND + $D_HI $D_HI LATCHEN + A B C + QA QB QC + QABAR QBBAR QCBAR + D0_GFF IO_ALS00 * UALS137LOG LOGICEXP (12,16) DPWR DGND + G1_I G2BAR_I GLBAR_I A_I B_I C_I QA QB QC QABAR QBBAR QCBAR + G1 G2BAR GLBAR A B C LATCHEN ENABLE + Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 + D0_GATE IO_ALS00 + IO_LEVEL={IO_LEVEL} + + LOGIC: + G1 = { G1_I } + G2BAR = { G2BAR_I } + GLBAR = { GLBAR_I } + A = { A_I } + B = { B_I } + C = { C_I } + LATCHEN = { ~GLBAR } + ENABLE = { G1 & ~G2BAR } + Y0 = { ~(ENABLE & QCBAR & QBBAR & QABAR) } + Y1 = { ~(ENABLE & QCBAR & QBBAR & QA ) } + Y2 = { ~(ENABLE & QCBAR & QB & QABAR) } + Y3 = { ~(ENABLE & QCBAR & QB & QA ) } + Y4 = { ~(ENABLE & QC & QBBAR & QABAR) } + Y5 = { ~(ENABLE & QC & QBBAR & QA ) } + Y6 = { ~(ENABLE & QC & QB & QABAR) } + Y7 = { ~(ENABLE & QC & QB & QA ) } * UALS137DLY PINDLY (8,0,7) DPWR DGND + Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 + G1 G2BAR GLBAR A B C ENABLE + Y0_O Y1_O Y2_O Y3_O Y4_O Y5_O Y6_O Y7_O + IO_ALS00 + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + ABLE1 = { CHANGED(ENABLE,0) & CHANGED(G1,0) } + ABLE2 = { CHANGED(ENABLE,0) & CHANGED(G2BAR,0) } + ABLEL = { CHANGED(GLBAR,0) } + ADDR = { CHANGED(A,0) | CHANGED(B,0) | CHANGED(C,0) } + + PINDLY: + Y0_O Y1_O Y2_O Y3_O Y4_O Y5_O Y6_O Y7_O = { + CASE ( + ABLE2 & TRN_LH, DELAY(4NS,-1,12NS), + ABLE1 & TRN_HL, DELAY(5NS,-1,15NS), + ABLE2 & TRN_HL, DELAY(5NS,-1,15NS), + ABLE1 & TRN_LH, DELAY(5NS,-1,17NS), + ADDR & TRN_LH, DELAY(5NS,-1,20NS), + ADDR & TRN_HL, DELAY(6NS,-1,20NS), + ABLEL & TRN_HL, DELAY(7NS,-1,20NS), + ABLEL & TRN_LH, DELAY(7NS,-1,22NS), + DELAY(7NS,-1,22NS) + ) + } + + WIDTH: + NODE = GLBAR + MIN_LO = 10NS + SETUP_HOLD: + DATA(3) = A B C + CLOCK LH = GLBAR + SETUPTIME = 10NS + HOLDTIME = 5NS * .ENDS * *$ *--------- * 74ALS138 DECODER/DEMULTIPLEXER 3-8 LINE * * ALS/AS LOGIC CIRCUITS DATA BOOK, 1986, TI * JLS 8-4-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES * .SUBCKT 74ALS138 G1_I G2ABAR_I G2BBAR_I A_I B_I C_I + Y0_O Y1_O Y2_O Y3_O Y4_O Y5_O Y6_O Y7_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UALS138LOG LOGICEXP (6,12) DPWR DGND + G1_I G2ABAR_I G2BBAR_I A_I B_I C_I + A B C ENABLE + Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 + D0_GATE IO_ALS00 + IO_LEVEL={IO_LEVEL} + + LOGIC: + G1 = { G1_I } + G2ABAR = { G2ABAR_I } + G2BBAR = { G2BBAR_I } + A = { A_I } + B = { B_I } + C = { C_I } + ABAR = { ~A } + BBAR = { ~B } + CBAR = { ~C } + ENABLE = { ~G2ABAR & ~G2BBAR & G1 } + Y0 = { ~(ENABLE & CBAR & BBAR & ABAR) } + Y1 = { ~(ENABLE & CBAR & BBAR & A ) } + Y2 = { ~(ENABLE & CBAR & B & ABAR) } + Y3 = { ~(ENABLE & CBAR & B & A ) } + Y4 = { ~(ENABLE & C & BBAR & ABAR) } + Y5 = { ~(ENABLE & C & BBAR & A ) } + Y6 = { ~(ENABLE & C & B & ABAR) } + Y7 = { ~(ENABLE & C & B & A ) } * UALS138DLY PINDLY (8,0,4) DPWR DGND + Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 + ENABLE A B C + Y0_O Y1_O Y2_O Y3_O Y4_O Y5_O Y6_O Y7_O + IO_ALS00 + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + ABLE = { CHANGED(ENABLE,0) } + ADDR = { CHANGED(A,0) | CHANGED(B,0) | CHANGED(C,0) } + + PINDLY: + Y0_O Y1_O Y2_O Y3_O Y4_O Y5_O Y6_O Y7_O = { + CASE ( + ABLE & TRN_LH, DELAY(4NS,-1,17NS), + ABLE & TRN_HL, DELAY(5NS,-1,17NS), + ADDR & TRN_HL, DELAY(6NS,-1,18NS), + ADDR & TRN_LH, DELAY(6NS,-1,22NS), + DELAY(6NS,-1,22NS) + ) + } * .ENDS * *$ *-------- * 74ALS139 DECODER/DEMULTIPLEXER 2-4 LINE * * ALS/AS LOGIC CIRCUITS DATA BOOK, 1986, TI * JLS 8-1-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES * .SUBCKT 74ALS139 GBAR_I A_I B_I Y0_O Y1_O Y2_O Y3_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UALS139LOG LOGICEXP (3,7) DPWR DGND + GBAR_I A_I B_I + GBAR A B + Y0 Y1 Y2 Y3 + D0_GATE IO_ALS00 + IO_LEVEL={IO_LEVEL} + + LOGIC: + GBAR = { GBAR_I } + A = { A_I } + B = { B_I } + ABAR = { ~A } + BBAR = { ~B } + ENABLE = { ~GBAR } + Y0 = { ~(ENABLE & BBAR & ABAR ) } + Y1 = { ~(ENABLE & BBAR & A ) } + Y2 = { ~(ENABLE & B & ABAR ) } + Y3 = { ~(ENABLE & B & A ) } * UALS139DLY PINDLY (4,0,3) DPWR DGND + Y0 Y1 Y2 Y3 + GBAR A B + Y0_O Y1_O Y2_O Y3_O + IO_ALS00 + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + ABLE = { CHANGED(GBAR,0) } + ADDR = { CHANGED(A,0) | CHANGED(B,0) } + + PINDLY: + Y0_O Y1_O Y2_O Y3_O = { + CASE ( + TRN_LH, DELAY(3NS,9NS,14NS), + ADDR , DELAY(3NS,9NS,14NS), + ABLE & TRN_HL, DELAY(3NS,9NS,15NS), + DELAY(3NS,9NS,15NS) + ) + } * .ENDS * *$ *--------- * 74ALS151 MULTIPLEXER/DATA SELECTOR 8-1 LINE * * ALS/AS LOGIC CIRCUITS DATA BOOK, 1986, TI * TC 08/21/92 REMODELED USING LOGICEXP, PINDLY, & CONSTRAINT DEVICES * .SUBCKT 74ALS151 GBAR_I A_I B_I C_I D0_I D1_I D2_I D3_I D4_I D5_I D6_I D7_I + Y_O W_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UALS151LOG LOGICEXP(12,14) DPWR DGND + GBAR_I A_I B_I C_I D0_I D1_I D2_I D3_I D4_I D5_I D6_I D7_I + GBAR A B C D0 D1 D2 D3 D4 D5 D6 D7 W Y + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} + LOGIC: + GBAR = { GBAR_I } + A = { A_I } + B = { B_I } + C = { C_I } + D0 = { D0_I } + D1 = { D1_I } + D2 = { D2_I } + D3 = { D3_I } + D4 = { D4_I } + D5 = { D5_I } + D6 = { D6_I } + D7 = { D7_I } + IA = { ~A } + IB = { ~B } + IC = { ~C } + IG = { ~GBAR } + ID0 = { D0 & IA & IB & IC & IG } + ID1 = { D1 & A & IB & IC & IG } + ID2 = { D2 & IA & B & IC & IG } + ID3 = { D3 & A & B & IC & IG } + ID4 = { D4 & IA & IB & C & IG } + ID5 = { D5 & A & IB & C & IG } + ID6 = { D6 & IA & B & C & IG } + ID7 = { D7 & A & B & C & IG } + W = { ~(ID0 | ID1 | ID2 | ID3 | ID4 | ID5 | ID6 | ID7) } + Y = { ~W } * UALS151DLY PINDLY (2,0,12) DPWR DGND + W Y + GBAR A B C D0 D1 D2 D3 D4 D5 D6 D7 + W_O Y_O + IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + DATA = { CHANGED(D0,0) | CHANGED(D1,0) | CHANGED(D2,0) | CHANGED(D3,0) | + CHANGED(D4,0) | CHANGED(D5,0) | CHANGED(D6,0) | CHANGED(D7,0) } + SELECT = { CHANGED(A,0) | CHANGED(B,0) | CHANGED(C,0) } + ENABLE = { CHANGED(GBAR,0) } + PINDLY: + Y_O = { + CASE( + SELECT & TRN_HL, DELAY(8NS,-1,24NS), + ENABLE & TRN_HL, DELAY(4NS,-1,19NS), + ENABLE & TRN_LH, DELAY(4NS,-1,18NS), + SELECT & TRN_LH, DELAY(4NS,-1,18NS), + DATA & TRN_HL, DELAY(5NS,-1,15NS), + DATA & TRN_LH, DELAY(3NS,-1,10NS), + DELAY(9NS,-1,25NS) + ) + } + W_O = { + CASE( + SELECT & TRN_LH, DELAY(7NS,-1,24NS), + SELECT & TRN_HL, DELAY(7NS,-1,23NS), + ENABLE & TRN_HL, DELAY(5NS,-1,23NS), + ENABLE & TRN_LH, DELAY(5NS,-1,19NS), + DATA & TRN_HL, DELAY(4NS,-1,15NS), + DATA & TRN_LH, DELAY(3NS,-1,15NS), + DELAY(8NS,-1,25NS) + ) + } * .ENDS * *$ *--------- * 74ALS153 DUAL 4-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS * * The ALS/AS Data Book, 1986, TI * JSW 8/12/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74ALS153 G1BAR_I G2BAR_I A_I B_I 1C0_I 1C1_I 1C2_I 1C3_I + 2C0_I 2C1_I 2C2_I 2C3_I Y1_O Y2_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UALS153LOG LOGICEXP(12,14) DPWR DGND + G1BAR_I G2BAR_I A_I B_I 1C0_I 1C1_I 1C2_I 1C3_I 2C0_I 2C1_I 2C2_I 2C3_I + G1BAR G2BAR A B 1C0 1C1 1C2 1C3 2C0 2C1 2C2 2C3 Y1 Y2 + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} + LOGIC: + G1BAR = { G1BAR_I } + G2BAR = { G2BAR_I } + A = { A_I } + B = { B_I } + 1C0 = { 1C0_I } + 1C1 = { 1C1_I } + 1C2 = { 1C2_I } + 1C3 = { 1C3_I } + 2C0 = { 2C0_I } + 2C1 = { 2C1_I } + 2C2 = { 2C2_I } + 2C3 = { 2C3_I } + G1 = { ~G1BAR } + G2 = { ~G2BAR } + ABAR = { ~A } + BBAR = { ~B } + I0 = { G1 & BBAR & ABAR & 1C0 } + I1 = { G1 & BBAR & A & 1C1 } + I2 = { G1 & B & ABAR & 1C2 } + I3 = { G1 & B & A & 1C3 } + I4 = { G2 & BBAR & ABAR & 2C0 } + I5 = { G2 & BBAR & A & 2C1 } + I6 = { G2 & B & ABAR & 2C2 } + I7 = { G2 & B & A & 2C3 } + Y1 = { I0 | I1 | I2 | I3 } + Y2 = { I4 | I5 | I6 | I7 } * UALS153DLY PINDLY (2,0,12) DPWR DGND + Y1 Y2 + G1BAR G2BAR A B 1C0 1C1 1C2 1C3 2C0 2C1 2C2 2C3 + Y1_O Y2_O + IO_ALS00 + MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + BOOLEAN: + DATA1 = { (CHANGED(1C0,0) | CHANGED(1C1,0) | CHANGED(1C2,0) | + CHANGED(1C3,0)) } + DATA2 = { (CHANGED(2C0,0) | CHANGED(2C1,0) | CHANGED(2C2,0) | + CHANGED(2C3,0)) } + SELECT = { CHANGED(A,0) | CHANGED(B,0) } + PINDLY: + Y1_O = { + CASE( + SELECT, DELAY(5NS,-1,21NS), + CHANGED(G1BAR,0), DELAY(5NS,-1,18NS), + DATA1 & TRN_HL, DELAY(4NS,-1,15NS), + DATA1 & TRN_LH, DELAY(3NS,-1,10NS), + DELAY(6NS,-1,22NS) + ) + } + Y2_O = { + CASE( + SELECT, DELAY(5NS,-1,21NS), + CHANGED(G2BAR,0), DELAY(5NS,-1,18NS), + DATA2 & TRN_HL, DELAY(4NS,-1,15NS), + DATA2 & TRN_LH, DELAY(3NS,-1,10NS), + DELAY(6NS,-1,22NS) + ) + } * .ENDS * *$ *--------- * 74ALS156 DECODER/DEMULTIPLEXER 2-4 LINE WITH OPEN COLLECTOR OUTPUTS * * ALS/AS LOGIC CIRCUITS DATA BOOK, 1986, TI * JLS 7-30-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES * .SUBCKT 74ALS156 G1BAR_I G2BAR_I A_I B_I C1_I C2BAR_I + 1Y0_O 1Y1_O 1Y2_O 1Y3_O 2Y0_O 2Y1_O 2Y2_O 2Y3_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UALS156LOG LOGICEXP (6,14) DPWR DGND + G1BAR_I G2BAR_I A_I B_I C1_I C2BAR_I + G1BAR A B C1 ENABLE1 ENABLE2 + 1Y0 1Y1 1Y2 1Y3 2Y0 2Y1 2Y2 2Y3 + D0_GATE IO_ALS00 + IO_LEVEL={IO_LEVEL} + + LOGIC: + G1BAR = { G1BAR_I } + G2BAR = { G2BAR_I } + A = { A_I } + B = { B_I } + C1 = { C1_I } + C2BAR = { C2BAR_I } + ABAR = { ~A } + BBAR = { ~B } + ENABLE1 = { ~G1BAR & C1 } + ENABLE2 = { ~G2BAR & ~C2BAR } + + 1Y0 = { ~(ENABLE1 & BBAR & ABAR) } + 1Y1 = { ~(ENABLE1 & BBAR & A ) } + 1Y2 = { ~(ENABLE1 & B & ABAR) } + 1Y3 = { ~(ENABLE1 & B & A ) } + + 2Y0 = { ~(ENABLE2 & BBAR & ABAR) } + 2Y1 = { ~(ENABLE2 & BBAR & A ) } + 2Y2 = { ~(ENABLE2 & B & ABAR) } + 2Y3 = { ~(ENABLE2 & B & A ) } * UALS156DLY PINDLY (8,0,6) DPWR DGND + 1Y0 1Y1 1Y2 1Y3 2Y0 2Y1 2Y2 2Y3 + G1BAR A B C1 ENABLE1 ENABLE2 + 1Y0_O 1Y1_O 1Y2_O 1Y3_O 2Y0_O 2Y1_O 2Y2_O 2Y3_O + IO_ALS00_OC + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + ABLE1 = { CHANGED(G1BAR,0) & CHANGED(ENABLE1,0) } + ABLE2 = { CHANGED(ENABLE2,0) } + ADDR = { CHANGED(A,0) | CHANGED(B,0) } + ADDRC1 = { CHANGED(C1,0) & CHANGED(ENABLE1,0) } + + PINDLY: + 1Y0_O 1Y1_O 1Y2_O 1Y3_O = { + CASE ( + ABLE1 & TRN_LH, DELAY(13NS,24NS,38NS), + ABLE1 & TRN_HL, DELAY( 6NS,13NS,22NS), + ADDR & TRN_LH, DELAY(13NS,30NS,55NS), + ADDR & TRN_HL, DELAY( 6NS,12NS,25NS), + ADDRC1 & TRN_LH, DELAY(18NS,38NS,50NS), + ADDRC1 & TRN_HL, DELAY( 6NS,12NS,23NS), + DELAY(18NS,38NS,55NS) + ) + } + 2Y0_O 2Y1_O 2Y2_O 2Y3_O = { + CASE ( + ABLE2 & TRN_LH, DELAY(13NS,24NS,38NS), + ABLE2 & TRN_HL, DELAY( 6NS,13NS,22NS), + ADDR & TRN_LH, DELAY(13NS,30NS,55NS), + ADDR & TRN_HL, DELAY( 6NS,12NS,25NS), + DELAY(13NS,30NS,55NS) + ) + } * .ENDS * *$ *--------- * 74ALS157 QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS * * The ALS/AS Data Book, 1986, TI * JSW 8/25/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74ALS157 GBAR_I 1A_I 1B_I 2A_I 2B_I 3A_I 3B_I 4A_I 4B_I SEL_I + Y1_O Y2_O Y3_O Y4_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UALS157LOG LOGICEXP(10,14) DPWR DGND + GBAR_I 1A_I 1B_I 2A_I 2B_I 3A_I 3B_I 4A_I 4B_I SEL_I + GBAR 1A 1B 2A 2B 3A 3B 4A 4B SEL Y1 Y2 Y3 Y4 + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} + LOGIC: + GBAR = { GBAR_I } + 1A = { 1A_I } + 1B = { 1B_I } + 2A = { 2A_I } + 2B = { 2B_I } + 3A = { 3A_I } + 3B = { 3B_I } + 4A = { 4A_I } + 4B = { 4B_I } + SEL = { SEL_I } + SEL1 = { ~GBAR & ~SEL } + SEL2 = { ~GBAR & SEL } + Y1 = { (1A & SEL1) | (1B & SEL2) } + Y2 = { (2A & SEL1) | (2B & SEL2) } + Y3 = { (3A & SEL1) | (3B & SEL2) } + Y4 = { (4A & SEL1) | (4B & SEL2) } * UALS157DLY PINDLY (4,0,10) DPWR DGND + Y1 Y2 Y3 Y4 + GBAR 1A 1B 2A 2B 3A 3B 4A 4B SEL + Y1_O Y2_O Y3_O Y4_O + IO_ALS00 + MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + BOOLEAN: + DATA = { CHANGED(1A,0) | CHANGED(1B,0) | CHANGED(2A,0) | CHANGED(2B,0) | + CHANGED(3A,0) | CHANGED(3B,0) | CHANGED(4A,0) | CHANGED(4B,0) } + SELECT = { CHANGED(SEL,0) } + ENABLE = { CHANGED(GBAR,0) } + PINDLY: + Y1_O Y2_O Y3_O Y4_O = { + CASE( + SELECT & TRN_LH, DELAY(7NS,15NS,24NS), + ENABLE & TRN_LH, DELAY(7NS,14NS,20NS), + DATA & TRN_LH, DELAY(4NS,9NS,14NS), + ENABLE & TRN_HL, DELAY(4NS,10NS,13NS), + SELECT & TRN_HL, DELAY(4NS,9NS,13NS), + DATA & TRN_HL, DELAY(2NS,6NS,12NS), + DELAY(8NS,16NS,25NS) + ) + } * .ENDS * *$ *------------------------------------------------------------------------- * 74ALS158 DUAL 4-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS * * The ALS/AS Data Book, 1986, TI * JSW 8/25/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74ALS158 GBAR_I 1A_I 1B_I 2A_I 2B_I 3A_I 3B_I 4A_I 4B_I SEL_I + Y1_O Y2_O Y3_O Y4_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UALS158LOG LOGICEXP(10,14) DPWR DGND + GBAR_I 1A_I 1B_I 2A_I 2B_I 3A_I 3B_I 4A_I 4B_I SEL_I + GBAR 1A 1B 2A 2B 3A 3B 4A 4B SEL Y1 Y2 Y3 Y4 + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} + LOGIC: + GBAR = { GBAR_I } + 1A = { 1A_I } + 1B = { 1B_I } + 2A = { 2A_I } + 2B = { 2B_I } + 3A = { 3A_I } + 3B = { 3B_I } + 4A = { 4A_I } + 4B = { 4B_I } + SEL = { SEL_I } + SEL1 = { ~GBAR & ~SEL } + SEL2 = { ~GBAR & SEL } + Y1 = { ~((1A & SEL1) | (1B & SEL2)) } + Y2 = { ~((2A & SEL1) | (2B & SEL2)) } + Y3 = { ~((3A & SEL1) | (3B & SEL2)) } + Y4 = { ~((4A & SEL1) | (4B & SEL2)) } * UALS158DLY PINDLY (4,0,10) DPWR DGND + Y1 Y2 Y3 Y4 + GBAR 1A 1B 2A 2B 3A 3B 4A 4B SEL + Y1_O Y2_O Y3_O Y4_O + IO_ALS00 + MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + BOOLEAN: + DATA = { CHANGED(1A,0) | CHANGED(1B,0) | CHANGED(2A,0) | CHANGED(2B,0) | + CHANGED(3A,0) | CHANGED(3B,0) | CHANGED(4A,0) | CHANGED(4B,0) } + SELECT = { CHANGED(SEL,0) } + ENABLE = { CHANGED(GBAR,0) } + PINDLY: + Y1_O Y2_O Y3_O Y4_O = { + CASE( + ENABLE, DELAY(5NS,13NS,18NS), + SELECT, DELAY(5NS,13NS,18NS), + DATA & TRN_LH, DELAY(4NS,9NS,15NS), + DATA & TRN_HL, DELAY(2NS,5NS,8NS), + DELAY(6NS,14NS,19NS) + ) + } * .ENDS * *$ *--------- * 74ALS160B Synchronous 4-bit Decade Counters with asynchronous clear * * ALS/AS LOGIC DATA BOOK, 1986, TI * JSW 7/1/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74ALS160B CLK_I ENP_I ENT_I CLRBAR_I LOADBAR_I A_I B_I C_I D_I + QA_O QB_O QC_O QD_O RCO_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UALS160BLOG LOGICEXP(13,15) DPWR DGND + CLK_I ENP_I ENT_I CLRBAR_I LOADBAR_I A_I B_I C_I D_I QA QB QC QD + CLK ENP ENT CLRBAR LOADBAR A B C D RCO DA DB DC DD EN + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} + LOGIC: + CLK = { CLK_I } ;Buffering + ENP = { ENP_I } + ENT = { ENT_I } + CLRBAR = { CLRBAR_I } + LOADBAR = { LOADBAR_I } + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + LOAD = { ~LOADBAR } ;Logic expressions + EN = { ENP & ENT & LOADBAR } + DA = { ((LOADBAR & QA) ^ EN) | (A & LOAD) } + DB = { (~(EN & QA) & LOADBAR & QB) | (~(LOADBAR & QB) & EN & QA + & ~QD) | (B & LOAD) } + DC = { ((LOADBAR & QC) ^ (EN & QA & QB)) | (C & LOAD) } + DD = { (~(EN & QA) & LOADBAR & QD) | (~(LOADBAR & QD) & EN & QC + & QB & QA) | (D & LOAD) } + RCO = { ENT & QA & QD } * UDFF DFF(4) DPWR DGND $D_HI CLRBAR CLK DA DB DC DD + QA QB QC QD QABAR QBBAR QCBAR QDBAR D0_EFF IO_ALS00 * UALS160BDLY PINDLY (5,0,10) DPWR DGND + RCO QA QB QC QD + CLK ENT CLRBAR ENP LOADBAR A B C D EN + RCO_O QA_O QB_O QC_O QD_O + IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + CLOCK = { CHANGED_LH(CLK,0) } + CNTENT = { CHANGED(ENT,0) } + CLEAR = { CHANGED_HL(CLRBAR,0) } + PINDLY: + QA_O QB_O QC_O QD_O = { + CASE( + CLOCK & TRN_LH, DELAY(4NS,-1,15NS), + CLOCK & TRN_HL, DELAY(6NS,-1,20NS), + CLEAR, DELAY(8NS,-1,24NS), + DELAY(6NS,-1,24NS) + ) + } + RCO_O = { + CASE( + CNTENT, DELAY(3NS,-1,13NS), + CLOCK, DELAY(5NS,-1,20NS), + CLEAR, DELAY(11NS,-1,23NS), + DELAY(5NS,-1,23NS) + ) + } + FREQ: + NODE = CLK + MAXFREQ = 40MEG + WIDTH: + NODE = CLK + MIN_LO = 12.5NS + MIN_HI = 12.5NS + WIDTH: + NODE = CLRBAR + MIN_LO = 15NS + SETUP_HOLD: + DATA(1) = LOADBAR + CLOCK LH = CLK + SETUPTIME = 15NS + WHEN = { CLRBAR!='0 } + SETUP_HOLD: + DATA(2) = ENP ENT + CLOCK LH = CLK + SETUPTIME = 15NS + WHEN = { CLRBAR!='0 & (LOADBAR!='0 ^ CHANGED(LOADBAR,0)) + & CHANGED(EN,15NS) } + SETUP_HOLD: + DATA(4) = A B C D + CLOCK LH = CLK + SETUPTIME = 15NS + WHEN = { (LOADBAR!='1 ^ CHANGED(LOADBAR,0)) & CLRBAR!='0 } + SETUP_HOLD: + DATA(1) = CLRBAR + CLOCK LH = CLK + RELEASETIME_LH = 10NS * .ENDS * *$ *--------- * 74ALS161B Synchronous 4-bit Binary Counter with Direct Clear * * THE ALS/AS DATA BOOK, 1986, TI * tc 07/01/92 Remodeled using LOGICEXP, PINDLY & CONSTRAINT devices * .SUBCKT 74ALS161B CLK_I ENP_I ENT_I CLRBAR_I LOADBAR_I A_I B_I C_I D_I + QA_O QB_O QC_O QD_O RCO_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 DFF(4) DPWR DGND $D_HI CLRBAR CLK + DA DB DC DD QA QB QC QD $D_NC $D_NC $D_NC $D_NC + D0_EFF IO_ALS00 * UALS161BLOG LOGICEXP(13,15) DPWR DGND + CLK_I ENP_I ENT_I CLRBAR_I LOADBAR_I A_I B_I C_I D_I QA QB QC QD + CLK ENP ENT CLRBAR LOADBAR A B C D RCO DA DB DC DD IEN + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} + LOGIC: + CLK = { CLK_I } + ENP = { ENP_I } + ENT = { ENT_I } + CLRBAR = { CLRBAR_I } + LOADBAR = { LOADBAR_I } + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + ILD = { ~LOADBAR } + IEN = { ENP & ENT & LOADBAR } + IA = { (LOADBAR & QA) ^ IEN } + IB = { (LOADBAR & QB) ^ (IEN & QA) } + IC = { (LOADBAR & QC) ^ (IEN & QA & QB) } + ID = { (LOADBAR & QD) ^ (IEN & QA & QB & QC) } + RCO = { ENT & QA & QB & QC & QD } + DA = { IA | (ILD & A) } + DB = { IB | (ILD & B) } + DC = { IC | (ILD & C) } + DD = { ID | (ILD & D) } * UALS161BDLY PINDLY (5,0,10) DPWR DGND + RCO QA QB QC QD + CLK ENT CLRBAR ENP LOADBAR A B C D IEN + RCO_O QA_O QB_O QC_O QD_O + IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + CLOCK = { CHANGED_LH(CLK,0) } + CLEAR = { CHANGED_HL(CLRBAR,0) } + PINDLY: + QA_O QB_O QC_O QD_O = { + CASE( + CLOCK & TRN_LH, DELAY(4NS,-1,15NS), + CLOCK & TRN_HL, DELAY(6NS,-1,20NS), + DELAY(8NS,-1,24NS) + ) + } + RCO_O = { + CASE( + CHANGED(ENT,0), DELAY(3NS,-1,13NS), + CLOCK, DELAY(5NS,-1,20NS), + DELAY(11NS,-1,23NS) + ) + } + FREQ: + NODE = CLK + MAXFREQ = 40MEG + WIDTH: + NODE = CLK + MIN_LO = 12.5NS + MIN_HI = 12.5NS + WIDTH: + NODE = CLRBAR + MIN_LO = 15NS + SETUP_HOLD: + DATA(4) = A B C D + CLOCK LH = CLK + SETUPTIME = 15NS + WHEN = { (LOADBAR!='1 ^ CHANGED(LOADBAR,0)) & CLRBAR!='0 } + SETUP_HOLD: + DATA(2) = ENP ENT + CLOCK LH = CLK + SETUPTIME = 15NS + WHEN = { (LOADBAR!='0 ^ CHANGED(LOADBAR,0)) & CLRBAR!='0 & + CHANGED(IEN,15NS) } + SETUP_HOLD: + DATA(1) = LOADBAR + CLOCK LH = CLK + SETUPTIME = 15NS + WHEN = { CLRBAR!='0 } + SETUP_HOLD: + DATA(1) = CLRBAR + CLOCK LH = CLK + RELEASETIME_LH = 10NS * .ENDS * *$ *--------- * 74ALS162B Synchronous 4-bit Decade Counters with asynchronous clear * * ALS/AS LOGIC CIRCUITS DATA BOOK, 1986, TI * JSW 7/1/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74ALS162B CLK_I ENP_I ENT_I CLRBAR_I LOADBAR_I A_I B_I C_I D_I + QA_O QB_O QC_O QD_O RCO_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UALS162BLOG LOGICEXP(13,15) DPWR DGND + CLK_I ENP_I ENT_I CLRBAR_I LOADBAR_I A_I B_I C_I D_I QA QB QC QD + CLK ENP ENT CLRBAR LOADBAR A B C D RCO DA DB DC DD EN + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} + LOGIC: + CLK = { CLK_I } ;Buffering + ENP = { ENP_I } + ENT = { ENT_I } + CLRBAR = { CLRBAR_I } + LOADBAR = { LOADBAR_I } + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + LOADB = { LOADBAR & CLRBAR } ;Logic expressions + LOAD = { ~LOADBAR & CLRBAR } + EN = { ENP & ENT & LOADBAR & CLRBAR } + DA = { ((LOADB & QA) ^ EN) | (A & LOAD) } + DB = { (~(EN & QA) & LOADB & QB) | (~(LOADB & QB) & EN & QA + & ~QD) | (B & LOAD) } + DC = { ((LOADB & QC) ^ (EN & QA & QB)) | (C & LOAD) } + DD = { (~(EN & QA) & LOADB & QD) | (~(LOADB & QD) & EN & QC + & QB & QA) | (D & LOAD) } + RCO = { ENT & QA & QD } * UDFF DFF(4) DPWR DGND $D_HI $D_HI CLK DA DB DC DD + QA QB QC QD QABAR QBBAR QCBAR QDBAR D0_EFF IO_ALS00 * UALS162BDLY PINDLY (5,0,10) DPWR DGND + RCO QA QB QC QD + CLK LOADBAR ENT ENP CLRBAR A B C D EN + RCO_O QA_O QB_O QC_O QD_O + IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + CLOCK = { CHANGED_LH(CLK,0) } + CNTENT = { CHANGED(ENT,0) } + PINDLY: + QA_O QB_O QC_O QD_O = { + CASE( + CLOCK & TRN_LH, DELAY(4NS,-1,15NS), + CLOCK & TRN_HL, DELAY(6NS,-1,20NS), + DELAY(6NS,-1,20NS) + ) + } + RCO_O = { + CASE( + CNTENT, DELAY(3NS,-1,13NS), + CLOCK, DELAY(5NS,-1,20NS), + DELAY(5NS,-1,20NS) + ) + } + BOOLEAN: + NOTCLEAR = { CLRBAR!='0 ^ CHANGED(CLRBAR,0) } + FREQ: + NODE = CLK + MAXFREQ = 40MEG + WIDTH: + NODE = CLK + MIN_LO = 12.5NS + MIN_HI = 12.5NS + WIDTH: + NODE = CLRBAR + MIN_LO = 15NS + SETUP_HOLD: + DATA(1) = LOADBAR + CLOCK LH = CLK + SETUPTIME = 15NS + WHEN = { NOTCLEAR } + SETUP_HOLD: + DATA(2) = ENP ENT + CLOCK LH = CLK + SETUPTIME = 15NS + WHEN = { CHANGED(EN,15NS) & (LOADBAR!='0 ^ CHANGED(LOADBAR,0)) & + NOTCLEAR } + SETUP_HOLD: + DATA(4) = A B C D + CLOCK LH = CLK + SETUPTIME = 15NS + WHEN = { (LOADBAR!='1 ^ CHANGED(LOADBAR,0)) & NOTCLEAR } + SETUP_HOLD: + DATA(1) = CLRBAR + CLOCK LH = CLK + SETUPTIME_HI = 10NS + SETUP_HOLD: + DATA(1) = CLRBAR + CLOCK LH = CLK + SETUPTIME_LO = 15NS * .ENDS * *$ *--------- * 74ALS163B Synchronous 4-bit Binary Counter with Direct Clear * * THE ALS/AS DATA BOOK, 1986, TI * tc 07/08/92 Remodeled using LOGICEXP, PINDLY & CONSTRAINT Devices * .SUBCKT 74ALS163B CLK_I ENP_I ENT_I CLRBAR_I LOADBAR_I A_I B_I C_I D_I + QA_O QB_O QC_O QD_O RCO_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 DFF(4) DPWR DGND $D_HI $D_HI CLK + DA DB DC DD QA QB QC QD $D_NC $D_NC $D_NC $D_NC + D0_EFF IO_ALS00 * UALS163BLOG LOGICEXP(13,15) DPWR DGND + CLK_I ENP_I ENT_I CLRBAR_I LOADBAR_I A_I B_I C_I D_I QA QB QC QD + CLK ENP ENT CLRBAR LOADBAR A B C D RCO DA DB DC DD IEN + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} + LOGIC: + CLK = { CLK_I } + ENP = { ENP_I } + ENT = { ENT_I } + CLRBAR = { CLRBAR_I } + LOADBAR = { LOADBAR_I } + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + ILD = { ~LOADBAR & CLRBAR } + IEN = { (ENP & ENT & LOADBAR) & CLRBAR } + ILC = { LOADBAR & CLRBAR } + IA = { (ILC & QA) ^ IEN } + IB = { (ILC & QB) ^ (IEN & QA) } + IC = { (ILC & QC) ^ (IEN & QA & QB) } + ID = { (ILC & QD) ^ (IEN & QA & QB & QC) } + RCO = { ENT & QA & QB & QC & QD } + DA = { IA | (ILD & A) } + DB = { IB | (ILD & B) } + DC = { IC | (ILD & C) } + DD = { ID | (ILD & D) } * UALS163BDLY PINDLY (5,0,10) DPWR DGND + RCO QA QB QC QD + CLK ENT ENP CLRBAR LOADBAR A B C D IEN + RCO_O QA_O QB_O QC_O QD_O + IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + CLOCK = { CHANGED_LH(CLK,0) } + PINDLY: + QA_O QB_O QC_O QD_O = { + CASE( + CLOCK & TRN_LH, DELAY(4NS,-1,15NS), + CLOCK & TRN_HL, DELAY(6NS,-1,20NS), + DELAY(6NS,-1,20NS) + ) + } + RCO_O = { + CASE( + CHANGED(ENT,0), DELAY(3NS,-1,13NS), + CLOCK, DELAY(5NS,-1,20NS), + DELAY(5NS,-1,20NS) + ) + } + BOOLEAN: + NOTCLEAR = { CLRBAR!='0 ^ CHANGED(CLRBAR,0) } + FREQ: + NODE = CLK + MAXFREQ = 40MEG + WIDTH: + NODE = CLK + MIN_LO = 12.5NS + MIN_HI = 12.5NS + SETUP_HOLD: + DATA(4) = A B C D + CLOCK LH = CLK + SETUPTIME = 15NS + WHEN = { (LOADBAR!='1 ^ CHANGED(LOADBAR,0)) & NOTCLEAR } + SETUP_HOLD: + DATA(2) = ENP ENT + CLOCK LH = CLK + SETUPTIME = 15NS + WHEN = { (LOADBAR!='0 ^ CHANGED(LOADBAR,0)) & NOTCLEAR & CHANGED(IEN,15NS) } + SETUP_HOLD: + DATA(1) = LOADBAR + CLOCK LH = CLK + SETUPTIME = 15NS + WHEN = { NOTCLEAR } + SETUP_HOLD: + DATA(1) = CLRBAR + CLOCK LH = CLK + SETUPTIME_LO = 15NS + SETUPTIME_HI = 10NS * .ENDS * *$ *--------- *74ALS164 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS * * THE SETUP AND HOLD SPECIFICATIONS FOR 74ALS164 IS NOT GIVEN IN THE TI BOOK * SO ALL SPECIFICATIONS (INCLUDING PROPAGATION DELAY) ARE TAKEN FROM THE BOOK * BELOW. * * THE ALS LOGIC SERIES, 1989, PHILIPS SEMICONDUCTORS * KN 7-31-92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * * .SUBCKT 74ALS164 CLRBAR_I CLK_I A_I B_I QA_O QB_O QC_O QD_O QE_O QF_O QG_O + QH_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 BUFA(4) DPWR DGND + CLRBAR_I CLK_I A_I B_I CLRBAR CLK A B + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} * U2 AND(2) DPWR DGND + A B IN + D0_GATE IO_ALS00 * U3 DFF(8) DPWR DGND + $D_HI CLRBAR CLK + IN QA QB QC QD QE QF QG + QA QB QC QD QE QF QG QH + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D0_EFF IO_ALS00 * UALS164DLY PINDLY (8,0,4) DPWR DGND + QA QB QC QD QE QF QG QH + CLRBAR CLK A B + QA_O QB_O QC_O QD_O QE_O QF_O QG_O QH_O + IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + PINDLY: + QA_O QB_O QC_O QD_O QE_O QF_O QG_O QH_O = { + CASE( + CHANGED_LH(CLK,0) & TRN_LH, DELAY(3NS,-1,12NS), + CHANGED_HL(CLRBAR,0) & TRN_HL, DELAY(2NS,-1,10NS), + CHANGED_LH(CLK,0) & TRN_HL, DELAY(4NS,-1,12NS), + DELAY(5NS,-1,13NS) ;DEFAULT + ) + } + + FREQ: + NODE = CLK + MAXFREQ = 50MEG + + WIDTH: + NODE = CLK + MIN_HIGH = 10NS + MIN_LOW = 10NS + + WIDTH: + NODE = CLRBAR + MIN_LOW = 10NS + + SETUP_HOLD: + CLOCK LH = CLK + DATA(2) A B + SETUPTIME = 10NS + WHEN = { CLRBAR != '0 } + + SETUP_HOLD: + DATA(1) CLRBAR + CLOCK LH = CLK + RELEASETIME_LH = 6NS * .ENDS * *$ *--------- * 74ALS165 8-BIT PARALLEL IN/SERIAL OUT SHIFT REGISTERS * * DM54ALS165/DM74ALS165, 1989, NATIONAL SEMICONDUCTOR * NH 7/27/92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74ALS165 SH/LDBAR_I CLK_INH_I CLK_I SER_I A_I B_I C_I D_I E_I F_I G_I H_I + QH_O QHBAR_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UALS165LOG LOGICEXP(12,29) DPWR DGND + SH/LDBAR_I CLK_INH_I CLK_I SER_I A_I B_I C_I D_I E_I F_I G_I H_I + SH/LDBAR CLK_INH CLK SER A B C D E F G H SA SB SC SD SE SF SG SH + RA RB RC RD RE RF RG RH CK + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} + + LOGIC: + + SH/LDBAR = { SH/LDBAR_I } + CLK_INH = { CLK_INH_I } + CLK = { CLK_I } + SER = { SER_I } + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + E = { E_I } + F = { F_I } + G = { G_I } + H = { H_I } + * INTERMEDIATE TERM + LOAD = { ~SH/LDBAR } + + SA = { ~(LOAD & A) } + SB = { ~(LOAD & B) } + SC = { ~(LOAD & C) } + SD = { ~(LOAD & D) } + SE = { ~(LOAD & E) } + SF = { ~(LOAD & F) } + SG = { ~(LOAD & G) } + SH = { ~(LOAD & H) } + + RA = { ~(LOAD & SA) } + RB = { ~(LOAD & SB) } + RC = { ~(LOAD & SC) } + RD = { ~(LOAD & SD) } + RE = { ~(LOAD & SE) } + RF = { ~(LOAD & SF) } + RG = { ~(LOAD & SG) } + RH = { ~(LOAD & SH) } + + CK = { (CLK_INH & SH/LDBAR) | (CLK & SH/LDBAR) } * U1 DFF(1) DPWR DGND SA RA CK SER QA $D_NC + D0_EFF IO_ALS00 * U2 DFF(1) DPWR DGND SB RB CK QA QB $D_NC + D0_EFF IO_ALS00 * U3 DFF(1) DPWR DGND SC RC CK QB QC $D_NC + D0_EFF IO_ALS00 * U4 DFF(1) DPWR DGND SD RD CK QC QD $D_NC + D0_EFF IO_ALS00 * U5 DFF(1) DPWR DGND SE RE CK QD QE $D_NC + D0_EFF IO_ALS00 * U6 DFF(1) DPWR DGND SF RF CK QE QF $D_NC + D0_EFF IO_ALS00 * U7 DFF(1) DPWR DGND SG RG CK QF QG $D_NC + D0_EFF IO_ALS00 * U8 DFF(1) DPWR DGND SH RH CK QG QH QHBAR + D0_EFF IO_ALS00 * UALS165DLY PINDLY (2,0,12) DPWR DGND + QH QHBAR + SH/LDBAR CLK H CLK_INH SER A B C D E F G + QH_O QHBAR_O + IO_ALS00 + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + LMODE = { SH/LDBAR=='0 } + SMODE = { SH/LDBAR=='1 } + CH_H = { CHANGED(H,0) } + CLOCK = { CHANGED_LH(CLK,0) } + LOAD = { CHANGED_HL(SH/LDBAR,0) } + + PINDLY: + QH_O = { + CASE( + CLOCK & SMODE & TRN_LH, DELAY(3NS,7NS,13NS), + CH_H & LMODE & TRN_LH, DELAY(3NS,7NS,13NS), + CLOCK & SMODE & TRN_HL, DELAY(3NS,9NS,14NS), + CH_H & LMODE & TRN_HL, DELAY(3NS,9NS,16NS), + LOAD & TRN_LH, DELAY(4NS,13NS,20NS), + LOAD & TRN_HL, DELAY(4NS,14NS,22NS), + DELAY(5NS,15NS,23NS) ;DEFAULT + ) + } + + QHBAR_O = { + CASE( + CLOCK & SMODE & TRN_LH, DELAY(3NS,7NS,13NS), + CLOCK & SMODE & TRN_HL, DELAY(3NS,9NS,14NS), + CH_H & LMODE & TRN_LH, DELAY(2NS,8NS,15NS), + CH_H & LMODE & TRN_HL, DELAY(3NS,9NS,16NS), + LOAD & TRN_LH, DELAY(4NS,13NS,20NS), + LOAD & TRN_HL, DELAY(4NS,14NS,22NS), + DELAY(5NS,15NS,23NS) ;DEFAULT + ) + } + + FREQ: + NODE = CLK + MAXFREQ = 45MEG + + WIDTH: + NODE = CLK + MIN_LO = 11NS + MIN_HI = 11NS + + WIDTH: + NODE = SH/LDBAR + MIN_LO = 12NS + + SETUP_HOLD: + DATA(1) = CLK_INH + CLOCK LH = CLK + SETUPTIME_LO = 11NS + MESSAGE = "CLOCK ENABLE SETUP TIME IS NOT MET" + + SETUP_HOLD: + DATA(1) = SH/LDBAR + CLOCK LH = CLK + SETUPTIME_HI = 10NS + + SETUP_HOLD: + DATA(1) = SER + CLOCK LH = CLK + SETUPTIME = 10NS + HOLDTIME = 4NS + WHEN = { (SH/LDBAR!='0 ^ CHANGED(SH/LDBAR,0)) } + + SETUP_HOLD: + DATA(8) = A B C D E F G H + CLOCK LH = SH/LDBAR + SETUPTIME = 10NS + HOLDTIME = 4NS * .ENDS * *$ *--------- * 74ALS166 PARALLEL LOAD 8-BIT SHIFT REGISTERS * * DM54ALS166/DM74ALS166, NATIONAL SEMICONDUCTOR, 1989 * NH 7-21-92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74ALS166 CLRBAR_I SH/LDBAR_I CLK_INH_I CLK_I SER_I A_I B_I C_I D_I E_I + F_I G_I H_I QH_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UALS166LOG LOGICEXP(20,30) DPWR DGND + CLRBAR_I SH/LDBAR_I CLK_INH_I CLK_I SER_I A_I B_I C_I D_I E_I F_I G_I H_I + QA QB QC QD QE QF QG + CLRBAR SH/LDBAR CLK_INH CLK SER A B C D E F G H JA JB JC JD JE JF JG JH + KA KB KC KD KE KF KG KH CK + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} + + LOGIC: + CLRBAR = { CLRBAR_I } + SH/LDBAR = { SH/LDBAR_I } + CLK_INH = { CLK_INH_I } + CLK = { CLK_I } + SER = { SER_I } + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + E = { E_I } + F = { F_I } + G = { G_I } + H = { H_I } + * INTERMEDIATE TERM + LOAD = { ~SH/LDBAR } + + KA = { ~((SH/LDBAR & SER) | (LOAD & A)) } + KB = { ~((SH/LDBAR & QA) | (LOAD & B)) } + KC = { ~((SH/LDBAR & QB) | (LOAD & C)) } + KD = { ~((SH/LDBAR & QC) | (LOAD & D)) } + KE = { ~((SH/LDBAR & QD) | (LOAD & E)) } + KF = { ~((SH/LDBAR & QE) | (LOAD & F)) } + KG = { ~((SH/LDBAR & QF) | (LOAD & G)) } + KH = { ~((SH/LDBAR & QG) | (LOAD & H)) } + JA = { ~KA } + JB = { ~KB } + JC = { ~KC } + JD = { ~KD } + JE = { ~KE } + JF = { ~KF } + JG = { ~KG } + JH = { ~KH } + CK = { ~(CLK | CLK_INH) } * U1 JKFF(8) DPWR DGND $D_HI CLRBAR CK + JA JB JC JD JE JF JG JH KA KB KC KD KE KF KG KH + QA QB QC QD QE QF QG QH $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D0_EFF IO_ALS00 * UALS166DLY PINDLY (1,0,13) DPWR DGND + QH + CLRBAR CLK SH/LDBAR CLK_INH SER A B C D E F G H + QH_O + IO_ALS00 + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + PINDLY: + QH_O = { + CASE( + CHANGED_LH(CLK,0) & TRN_LH, DELAY(2NS,7NS,13NS), + CHANGED_LH(CLK,0) & TRN_HL, DELAY(3NS,9NS,14NS), + CHANGED_HL(CLRBAR,0) & TRN_HL, DELAY(4NS,13NS,19NS), + DELAY(5NS,14NS,20NS); DEFAULT + ) + } + + BOOLEAN: + ACTIVE_MODE = { CLRBAR!='0 & CLK_INH!='1 } + + FREQ: + NODE = CLK + MAXFREQ = 45MEG + + WIDTH: + NODE = CLK + MIN_HI = 10NS + MIN_LO = 10NS + + WIDTH: + NODE = CLRBAR + MIN_LO = 9NS + + SETUP_HOLD: + DATA(1) SH/LDBAR + CLOCK LH = CLK + SETUPTIME = 18NS + WHEN = { ACTIVE_MODE } + + SETUP_HOLD: + DATA(8) A B C D E F G H + CLOCK LH = CLK + SETUPTIME = 7NS + HOLDTIME = 3NS + WHEN = { ACTIVE_MODE & (SH/LDBAR!='1 ^ CHANGED(SH/LDBAR,0)) } + + SETUP_HOLD: + DATA(1) SER + CLOCK LH = CLK + SETUPTIME = 7NS + HOLDTIME = 3NS + WHEN = { ACTIVE_MODE & (SH/LDBAR!='0 ^ CHANGED(SH/LDBAR,0)) } + + SETUP_HOLD: + DATA(1) CLRBAR + CLOCK LH = CLK + RELEASETIME_LH = 11NS + + SETUP_HOLD: + DATA(1) CLK_INH + CLOCK LH = CLK + SETUPTIME_LO = 10NS * .ENDS * *$ *------------------------------------------------------------------------- * 74ALS168B Synchronous 4-bit Up/Down Decade Counters * * The ALS/AS Data Book, 1986, TI * JSW 7/27/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74ALS168B CLK_I U/DBAR_I ENPBAR_I ENTBAR_I LOADBAR_I + A_I B_I C_I D_I QA_O QB_O QC_O QD_O RCOBAR_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UALS168BLOG LOGICEXP(17,15) DPWR DGND + CLK_I U/DBAR_I ENPBAR_I ENTBAR_I LOADBAR_I A_I B_I C_I D_I + QA QB QC QD QABAR QBBAR QCBAR QDBAR + CLK U/DBAR ENPBAR ENTBAR LOADBAR A B C D RCOBAR DA DB DC DD EN + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} + LOGIC: + CLK = { CLK_I } + ENPBAR = { ENPBAR_I } + ENTBAR = { ENTBAR_I } + U/DBAR = { U/DBAR_I } + LOADBAR = { LOADBAR_I } + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + UD = { ~U/DBAR } + LOAD = { ~LOADBAR } + EN = { ~ENTBAR & ~ENPBAR & LOADBAR } + IA4 = { ~((QABAR & U/DBAR) | (QA & UD)) } + IB4 = { ~((QBBAR & U/DBAR) | (QB & UD)) } + IC4 = { ~((QCBAR & U/DBAR) | (QC & UD)) } + ID4 = { ~((QDBAR & U/DBAR) | (QD & UD)) } + IB5 = { ~(U/DBAR & ID4) } + IC5 = { ~(QCBAR & UD & QDBAR) } + IA1 = { A & LOAD } + IA2 = { EN ^ ( LOADBAR & QA) } + IB1 = { B & LOAD } + IB2 = { ~(EN & IA4) & LOADBAR & QB } + IB3 = { IA4 & EN & IC5 & IB5 & QBBAR } + IC1 = { C & LOAD } + IC2 = { ~(EN & IA4 & IB4) & LOADBAR & QC } + IC3 = { ~(QC & LOADBAR) & EN & IA4 & IB4 & IC5 } + ID1 = { D & LOAD } + ID2 = { ~(EN & IA4) & LOADBAR & QD } + ID3 = { ~(QD & LOADBAR) & EN & IA4 & IB4 & IC4 } + DA = { IA1 | IA2 } + DB = { IB1 | IB2 | IB3 } + DC = { IC1 | IC2 | IC3 } + DD = { ID1 | ID2 | ID3 } + RCOBAR = { ~((U/DBAR & IA4 & ID4 & ~ENTBAR) | (~ENTBAR & UD & + IA4 & IB4 & IC4 & ID4)) } * UDFF DFF(4) DPWR DGND $D_HI $D_HI CLK DA DB DC DD + QA QB QC QD QABAR QBBAR QCBAR QDBAR D0_EFF IO_ALS00 * UALS168BDLY PINDLY (5,0,10) DPWR DGND + RCOBAR QA QB QC QD + CLK ENPBAR ENTBAR U/DBAR LOADBAR A B C D EN + RCOBAR_O QA_O QB_O QC_O QD_O + IO_ALS00 + MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + BOOLEAN: + CLOCK = { CHANGED_LH(CLK,0) } + CNTENT = { CHANGED(ENTBAR,0) } + PINDLY: + RCOBAR_O = { + CASE( + CNTENT & TRN_LH, DELAY(2NS,-1,13NS), + CNTENT & TRN_HL, DELAY(3NS,-1,16NS), + CHANGED(U/DBAR,0), DELAY(5NS,-1,19NS), + CLOCK & TRN_LH, DELAY(3NS,-1,20NS), + CLOCK & TRN_HL, DELAY(6NS,-1,20NS), + DELAY(6NS,-1,20NS) + ) + } + QA_O QB_O QC_O QD_O = { + CASE( + CLOCK & TRN_LH, DELAY(2NS,-1,15NS), + CLOCK & TRN_HL, DELAY(5NS,-1,20NS), + DELAY(5NS,-1,20NS) + ) + } + FREQ: + NODE = CLK + MAXFREQ = 40MEG + WIDTH: + NODE = CLK + MIN_LOW = 12.5NS + MIN_HIGH = 12.5NS + SETUP_HOLD: + DATA(4) = A B C D + CLOCK LH = CLK + SETUPTIME = 15NS + WHEN = { LOADBAR!='1 ^ CHANGED(LOADBAR,0) } + SETUP_HOLD: + DATA(2) = ENPBAR ENTBAR + CLOCK LH = CLK + SETUPTIME = 15NS + WHEN = { CHANGED(EN,15NS) & (LOADBAR!='0 ^ CHANGED(LOADBAR,0)) } + SETUP_HOLD: + DATA(1) = LOADBAR + CLOCK LH = CLK + SETUPTIME = 15NS + SETUP_HOLD: + DATA(1) = U/DBAR + CLOCK LH = CLK + SETUPTIME = 15NS + WHEN = { EN!='0 ^ CHANGED(EN,0) } * .ENDS * *$ *--------- * 74ALS169B Synchronous 4-Bit Up/Down Binary Counter * * ALS/AS LOGIC DATA BOOK, 1986, TI * tc 07/21/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74ALS169B CLK_I U/DBAR_I ENPBAR_I ENTBAR_I LOADBAR_I A_I B_I C_I D_I + QA_O QB_O QC_O QD_O RCOBAR_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 DFF(4) DPWR DGND $D_HI $D_HI CLK + DA DB DC DD QA QB QC QD QABAR QBBAR QCBAR QDBAR + D0_EFF IO_ALS00 * UALS169BLOG LOGICEXP(17,15) DPWR DGND + CLK_I U/DBAR_I ENPBAR_I ENTBAR_I LOADBAR_I A_I B_I C_I D_I QA QB QC QD + QABAR QBBAR QCBAR QDBAR + CLK U/DBAR ENPBAR ENTBAR LOADBAR A B C D DA DB DC DD RCOBAR IEN + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} + LOGIC: + CLK = { CLK_I } + U/DBAR = { U/DBAR_I } + ENPBAR = { ENPBAR_I } + ENTBAR = { ENTBAR_I } + LOADBAR = { LOADBAR_I } + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + ILD = { ~LOADBAR } + IEN = { ~(ENPBAR | ENTBAR | ILD) } + UP = { U/DBAR } + DN = { ~U/DBAR } + IA1 = { (QA & LOADBAR) ^ IEN } + IA2 = { ~((UP & QABAR) | (DN & QA)) } + IB1 = { (QB & LOADBAR) ^ (IEN & IA2) } + IB2 = { ~((UP & QBBAR) | (DN & QB)) } + IC1 = { (QC & LOADBAR) ^ (IEN & IA2 & IB2) } + IC2 = { ~((UP & QCBAR) | (DN & QC)) } + ID1 = { (QD & LOADBAR) ^ (IEN & IA2 & IB2 & IC2) } + ID2 = { ~((UP & QDBAR) | (DN & QD)) } + DA = { IA1 | (ILD & A) } + DB = { IB1 | (ILD & B) } + DC = { IC1 | (ILD & C) } + DD = { ID1 | (ILD & D) } + IR1 = { UP & ~ENTBAR & IA2 & IB2 & IC2 & ID2 } + IR2 = { DN & ~ENTBAR & IA2 & IB2 & IC2 & ID2 } + RCOBAR = { ~(IR1 | IR2) } * UALS169BDLY PINDLY (5,0,10) DPWR DGND + QA QB QC QD RCOBAR + CLK ENTBAR U/DBAR ENPBAR LOADBAR A B C D IEN + QA_O QB_O QC_O QD_O RCOBAR_O + IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + CLOCK = { CHANGED_LH(CLK,0) } + PINDLY: + QA_O QB_O QC_O QD_O = { + CASE( + CLOCK & TRN_LH, DELAY(2NS,-1,15NS), + DELAY(5NS,-1,20NS) + ) + } + RCOBAR_O = { + CASE( + CHANGED(ENTBAR,0) & TRN_LH, DELAY(2NS,-1,13NS), + CHANGED(ENTBAR,0) & TRN_HL, DELAY(3NS,-1,16NS), + CHANGED(U/DBAR,0), DELAY(5NS,-1,19NS), + CLOCK & TRN_LH, DELAY(3NS,-1,20NS), + CLOCK & TRN_HL, DELAY(6NS,-1,20NS), + DELAY(6NS,-1,20NS) + ) + } + BOOLEAN: + NOTLOADING = { LOADBAR!='0 ^ CHANGED(LOADBAR,0) } + ENABLE = { (ENPBAR!='1 ^ CHANGED(ENPBAR,0)) & + (ENTBAR!='1 ^ CHANGED(ENTBAR,0)) } + FREQ: + NODE = CLK + MAXFREQ = 40MEG + WIDTH: + NODE = CLK + MIN_LO = 12.5NS + MIN_HI = 12.5NS + SETUP_HOLD: + DATA(4) = A B C D + CLOCK LH = CLK + SETUPTIME = 15NS + WHEN = { LOADBAR!='1 ^ CHANGED(LOADBAR,0) } + SETUP_HOLD: + DATA(2) = ENPBAR ENTBAR + CLOCK LH = CLK + SETUPTIME = 15NS + WHEN = { NOTLOADING & CHANGED(IEN,15NS) } + SETUP_HOLD: + DATA(1) = LOADBAR + CLOCK LH = CLK + SETUPTIME = 15NS + SETUP_HOLD: + DATA(1) = U/DBAR + CLOCK LH = CLK + SETUPTIME = 15NS + WHEN = { NOTLOADING & ENABLE } * .ENDS * *$ *---------- * 74ALS174 HEX D-TYPE FLIP-FLOPS WITH CLEAR * * The ALS/AS Logic Data Book, 1986, TI * tvh 06/27/89 Update interface and model names * .subckt 74ALS174 CLRBAR CLK D1 D2 D3 D4 D5 D6 Q1 Q2 Q3 Q4 Q5 Q6 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UD dff(6) DPWR DGND + $D_HI CLRBAR CLK + D1 D2 D3 D4 D5 D6 + Q1 Q2 Q3 Q4 Q5 Q6 + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D_ALS174 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS174 ueff ( + TWCLKLMN=10NS TWCLKHMN=10NS + TWPCLMN=10NS TSUDCLKMN=10NS + TSUPCCLKHMN=6NS TPPCQHLMN=8NS + TPPCQHLMX=23NS TPCLKQLHMN=3NS + TPCLKQLHMX=15NS TPCLKQHLMN=5NS + TPCLKQHLMX=17NS + ) *$ *---------- * 74ALS175 QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR * * The ALS/AS Logic Data Book, 1986, TI * tvh 06/27/89 Update interface and model names * .subckt 74ALS175 CLRBAR CLK D1 D2 D3 D4 Q1 Q2 Q3 Q4 Q1BAR Q2BAR Q3BAR Q4BAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UD dff(4) DPWR DGND + $D_HI CLRBAR CLK + D1 D2 D3 D4 + Q1 Q2 Q3 Q4 Q1BAR Q2BAR Q3BAR Q4BAR + D_ALS175 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS175 ueff ( + TWCLKLMN=10NS TWCLKHMN=10NS + TWPCLMN=10NS TSUDCLKMN=10NS + TSUPCCLKHMN=6NS TPPCQLHMN=5NS + TPPCQLHMX=18NS TPPCQHLMN=8NS + TPPCQHLMX=23NS TPCLKQLHMN=3NS + TPCLKQLHMX=15NS TPCLKQHLMN=5NS + TPCLKQHLMX=17NS + ) *$ *--------- * 74ALS190 Synchronous 4-bit Up/Down Decade Counters * * The ALS/AS Data Book, 1986, TI * JSW 7/15/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74ALS190 CLK_I DUBAR_I CTENBAR_I LOADBAR_I A_I B_I C_I D_I + RCOBAR_O MXMNOUT_O QA_O QB_O QC_O QD_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UALS190 LOGICEXP (12,22) DPWR DGND + CLK_I DUBAR_I CTENBAR_I LOADBAR_I A_I B_I C_I D_I QABAR QBBAR QCBAR QDBAR + CLK DUBAR CTENBAR LOADBAR A B C D MXMNOUT RCOBAR + SA RA DA SB RB DB SC RC DC SD RD DD + D0_GATE IO_ALS00 + IO_LEVEL={IO_LEVEL} + + LOGIC: + CLK = { CLK_I } + DUBAR = { DUBAR_I } + CTENBAR = { CTENBAR_I } + LOADBAR = { LOADBAR_I } + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + DU = { ~DUBAR } + LOAD = { ~LOADBAR } + CTEN = { ~CTENBAR } + CTD = { DUBAR & CTEN } + CTU = { DU & CTEN } + MXMNOUT = { (~QABAR & ~QDBAR & DU) | (QABAR & QBBAR & QCBAR & + QDBAR & DUBAR) } + RCOBAR = { ~(MXMNOUT & CTEN & ~CLK) } + SA = { ~(A & LOAD) } + RA = { ~(~A & LOAD) } + DA = { ~QABAR ^ CTEN } + SB = { ~(B & LOAD) } + RB = { ~(~B & LOAD) } + I1DB = { ~QABAR & QDBAR } + I2DB = { QABAR & ~(QBBAR & QCBAR & QDBAR) } + I3DB = { I1DB ^ ~QBBAR } + I4DB = { I2DB ^ ~QBBAR } + I5DB = { I3DB & CTU } + I6DB = { CTENBAR & ~QBBAR } + I7DB = { I4DB & CTD } + DB = { I5DB | I6DB | I7DB } + SC = { ~(C & LOAD) } + RC = { ~(~C & LOAD) } + I1DC = { ~QABAR & ~QBBAR } + I2DC = { QABAR & QBBAR & ~(QBBAR & QCBAR & QDBAR) } + I3DC = { I1DC ^ ~QCBAR } + I4DC = { I2DC ^ ~QCBAR } + I5DC = { I3DC & CTU } + I6DC = { CTENBAR & ~QCBAR } + I7DC = { I4DC & CTD } + DC = { I5DC | I6DC | I7DC } + SD = { ~(D & LOAD) } + RD = { ~(~D & LOAD) } + I1DD = { QABAR & ~QDBAR } + I2DD = { ~QABAR & ~QBBAR & ~QCBAR & QDBAR } + I3DD = { QABAR & QBBAR & QCBAR } + I4DD = { I1DD | I2DD } + I5DD = { I3DD ^ ~QDBAR } + I6DD = { I4DD & CTU } + I7DD = { ~QDBAR & CTENBAR } + I8DD = { I5DD & CTD } + DD = { I6DD | I7DD | I8DD } * UDA DFF(1) DPWR DGND SA RA CLK DA QA QABAR D0_EFF IO_ALS00 UDB DFF(1) DPWR DGND SB RB CLK DB QB QBBAR D0_EFF IO_ALS00 UDC DFF(1) DPWR DGND SC RC CLK DC QC QCBAR D0_EFF IO_ALS00 UDD DFF(1) DPWR DGND SD RD CLK DD QD QDBAR D0_EFF IO_ALS00 * UALS190DLY PINDLY (6,0,8) DPWR DGND + QA QB QC QD RCOBAR MXMNOUT + A B C D CLK DUBAR CTENBAR LOADBAR + QA_O QB_O QC_O QD_O RCOBAR_O MXMNOUT_O + IO_ALS00 + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + ABCD = { (CHANGED(A,0) | CHANGED(B,0) | CHANGED(C,0) | CHANGED(D,0)) + & LOADBAR!='1 } + PINDLY: + QA_O QB_O QC_O QD_O = { + CASE( + CHANGED_LH(CLK,0), DELAY(3NS,-1,18NS), + CHANGED_HL(LOADBAR,0), DELAY(8NS,-1,30NS), + ABCD, DELAY(4NS,-1,21NS), + DELAY(8NS,-1,30NS) + ) + } + RCOBAR_O = { + CASE( + CHANGED(CTENBAR,0), DELAY(4NS,-1,18NS), + CHANGED(CLK,0), DELAY(5NS,-1,20NS), + CHANGED(DUBAR,0) & TRN_HL, DELAY(10na,-1,28NS), + CHANGED(DUBAR,0) & TRN_LH, DELAY(15NS,-1,37NS), + DELAY(15NS,-1,37NS) + ) + } + MXMNOUT_O = { + CASE( + CHANGED(DUBAR,0), DELAY(8NS,-1,25NS), + CHANGED_LH(CLK,0), DELAY(8NS,-1,31NS), + DELAY(8NS,-1,31NS) + ) + } + FREQ: + NODE = CLK + MAXFREQ = 25MEG + WIDTH: + NODE = CLK + MIN_LO = 20NS + MIN_HI = 20NS + WIDTH: + NODE = LOADBAR + MIN_LO = 20NS + SETUP_HOLD: + DATA(1) CTENBAR + CLOCK LH = CLK + SETUPTIME = 20NS + WHEN = { LOADBAR!='0 } + SETUP_HOLD: + DATA(1) DUBAR + CLOCK LH = CLK + SETUPTIME = 20NS + WHEN = { LOADBAR!='0 & (CTENBAR!='1 ^ CHANGED(CTENBAR,0)) } + SETUP_HOLD: + DATA(1) = LOADBAR + CLOCK LH = CLK + RELEASETIME_LH = 20NS + SETUP_HOLD: + DATA(4) = A B C D + CLOCK LH = LOADBAR + SETUPTIME = 20NS + HOLDTIME = 5NS * .ENDS * *$ *--------- * 74ALS191 Synchronous 4-bit Up/Down Binary Counters * * THE ALS/AS LOGIC CIRCUITS DATA BOOK, 1986, TI * tc 7/23/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74ALS191 CLK_I DUBAR_I CTENBAR_I LOADBAR_I A_I B_I C_I D_I + RCOBAR_O MXMNOUT_O QA_O QB_O QC_O QD_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 DFF(1) DPWR DGND SA RA CLK DA QA QABAR + D0_EFF IO_ALS00 U2 DFF(1) DPWR DGND SB RB CLK DB QB QBBAR + D0_EFF IO_ALS00 U3 DFF(1) DPWR DGND SC RC CLK DC QC QCBAR + D0_EFF IO_ALS00 U4 DFF(1) DPWR DGND SD RD CLK DD QD QDBAR + D0_EFF IO_ALS00 * UALS191LOG LOGICEXP (12,22) DPWR DGND + CLK_I DUBAR_I CTENBAR_I LOADBAR_I A_I B_I C_I D_I QABAR QBBAR QCBAR QDBAR + CLK DUBAR CTENBAR LOADBAR A B C D MXMNOUT RCOBAR SA RA DA SB RB DB + SC RC DC SD RD DD + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} + LOGIC: + CLK = { CLK_I } + DUBAR = { DUBAR_I } + CTENBAR = { CTENBAR_I } + LOADBAR = { LOADBAR_I } + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + IEN1 = { ~(~DUBAR | CTENBAR) } + IEN2 = { ~(DUBAR | CTENBAR) } + ILD = { ~LOADBAR } + IQA = { ~QABAR } + IQB = { ~QBBAR } + IQC = { ~QCBAR } + IQD = { ~QDBAR } + IM1 = { ~(IQA & IQB & IQC & IQD & ~DUBAR) } + IM2 = { ~(QABAR & QBBAR & QCBAR & QDBAR & DUBAR) } + IB1 = { ~(IEN2 & (IQA ^ IQB)) } + IB2 = { ~((IQB ^ QABAR) & IEN1) } + IC1 = { ~(IEN2 & ((IQA & IQB) ^ IQC)) } + IC2 = { ~((IQC ^ (QABAR & QBBAR)) & IEN1) } + ID1 = { ~(IEN2 & ((IQA & IQB & IQC) ^ IQD)) } + ID2 = { ~((IQD ^ (QABAR & QBBAR & QCBAR)) & IEN1) } + SA = { ~(A & ILD) } + RA = { ~(~A & ILD) } + SB = { ~(B & ILD) } + RB = { ~(~B & ILD) } + SC = { ~(C & ILD) } + RC = { ~(~C & ILD) } + SD = { ~(D & ILD) } + RD = { ~(~D & ILD) } + DA = { ~CTENBAR ^ IQA } + DB = { ~(IB1 & IB2 & ~(CTENBAR & IQB)) } + DC = { ~(IC1 & IC2 & ~(CTENBAR & IQC)) } + DD = { ~(ID1 & ID2 & ~(CTENBAR & IQD)) } + MXMNOUT = { ~(IM1 & IM2) } + RCOBAR = { ~(MXMNOUT & ~CTENBAR & ~CLK) } * UALS191DLY PINDLY (6,0,8) DPWR DGND + QA QB QC QD RCOBAR MXMNOUT + A B C D CLK DUBAR CTENBAR LOADBAR + QA_O QB_O QC_O QD_O RCOBAR_O MXMNOUT_O + IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + CLOCK = { CHANGED_LH(CLK,0) } + DATA = { (CHANGED(A,0) | CHANGED(B,0) | CHANGED(C,0) | CHANGED(D,0)) + & LOADBAR!='1 } + PINDLY: + QA_O QB_O QC_O QD_O = { + CASE( + CLOCK, DELAY(3NS,-1,18NS), + DATA, DELAY(4NS,-1,21NS), + CHANGED_HL(LOADBAR,0), DELAY(8NS,-1,30NS), + DELAY(8NS,-1,30NS) + ) + } + RCOBAR_O = { + CASE( + CHANGED(CTENBAR,0), DELAY(4NS,-1,18NS), + CHANGED(CLK,0), DELAY(5NS,-1,20NS), + CHANGED(DUBAR,0) & TRN_HL, DELAY(10NS,-1,28NS), + CHANGED(DUBAR,0) & TRN_LH, DELAY(15NS,-1,37NS), + DELAY(15NS,-1,37NS) + ) + } + MXMNOUT_O = { + CASE( + CHANGED(DUBAR,0), DELAY(8NS,-1,25NS), + CLOCK, DELAY(8NS,-1,31NS), + DELAY(8NS,-1,31NS) + ) + } + FREQ: + NODE = CLK + MAXFREQ = 30MEG + WIDTH: + NODE = CLK + MIN_LO = 16.5NS + MIN_HI = 16.5NS + WIDTH: + NODE = LOADBAR + MIN_LO = 20NS + SETUP_HOLD: + DATA(1) = DUBAR + CLOCK LH = CLK + SETUPTIME = 20NS + WHEN = { LOADBAR!='0 & (CTENBAR!='1 ^ CHANGED(CTENBAR,0)) } + SETUP_HOLD: + DATA(1) = CTENBAR + CLOCK LH = CLK + SETUPTIME = 20NS + WHEN = { LOADBAR!='0 } + SETUP_HOLD: + DATA(1) = LOADBAR + CLOCK LH = CLK + RELEASETIME_LH = 20NS + SETUP_HOLD: + DATA(4) = A B C D + CLOCK LH = LOADBAR + SETUPTIME = 20NS + HOLDTIME = 5NS * .ENDS * *$ *--------- * 74ALS192 Synchronous 4-bit Up/Down Decade Counters (Dual clock w/ clear) * * ALS,AS LOGIC CIRCUITS DATA BOOK, 1986, TI * JSW 7/27/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74ALS192 UP_I DOWN_I CLR_I LOADBAR_I A_I B_I C_I D_I + QA_O QB_O QC_O QD_O BOBAR_O COBAR_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 DFF(1) DPWR DGND SA RA MCLK QABAR QA QABAR + D0_EFF IO_ALS00 U2 DFF(1) DPWR DGND SB RB MCLK DB QB QBBAR + D0_EFF IO_ALS00 U3 DFF(1) DPWR DGND SC RC MCLK DC QC QCBAR + D0_EFF IO_ALS00 U4 DFF(1) DPWR DGND SD RD MCLK DD QD QDBAR + D0_EFF IO_ALS00 U5 SRFF(1) DPWR DGND UP DOWN $D_HI $D_LO $D_LO IU ID + D0_GFF IO_ALS00 * UALS192LOG LOGICEXP (14,22) DPWR DGND + UP_I DOWN_I CLR_I LOADBAR_I A_I B_I C_I D_I QABAR QBBAR QCBAR QDBAR IU ID + UP DOWN CLR LOADBAR A B C D BOBAR COBAR MCLK + SA RA SB RB SC RC SD RD DB DC DD + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} + LOGIC: + UP = { UP_I } + DOWN = { DOWN_I } + CLR = { CLR_I } + LOADBAR = { LOADBAR_I } + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + ICL = { ~CLR } + ILD = { ~LOADBAR } + MCLK = { UP & DOWN } + IN1 = { ~(QBBAR & QCBAR & QDBAR) } + IQA = { ~QABAR } + IQB = { ~QBBAR } + IQC = { ~QCBAR } + IQD = { ~QDBAR } + IB1 = { IU & ((IQA & QDBAR) ^ IQB) } + IB2 = { (IQB ^ (QABAR & IN1)) & ID } + IC1 = { IU & ((IQA & IQB) ^ IQC) } + IC2 = { (IQC ^ (QABAR & QBBAR & IN1)) & ID } + ID1 = { IU & ((QDBAR & IQC & IQB & IQA) | (QABAR & IQD)) } + ID2 = { (IQD ^ (QABAR & QBBAR & QCBAR)) & ID } + DB = { IB1 | IB2 } + DC = { IC1 | IC2 } + DD = { ID1 | ID2 } + SA = { ~(A & ICL & ILD) } + RA = { ~(~A & ILD) & ICL } + SB = { ~(B & ICL & ILD) } + RB = { ~(~B & ILD) & ICL } + SC = { ~(C & ICL & ILD) } + RC = { ~(~C & ILD) & ICL } + SD = { ~(D & ICL & ILD) } + RD = { ~(~D & ILD) & ICL } + COBAR = { ~(IQA & IQD & ~UP) } + BOBAR = { ~(QABAR & QBBAR & QCBAR & QDBAR & ~DOWN) } * UALS192DLY PINDLY (6,0,8) DPWR DGND + QA QB QC QD BOBAR COBAR + UP DOWN LOADBAR CLR A B C D + QA_O QB_O QC_O QD_O BOBAR_O COBAR_O + IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + UPDN = { (CHANGED_LH(UP,0) | CHANGED_LH(DOWN,0)) & LOADBAR!='0 + & CLR!='1 } + CLEAR = { CHANGED_LH(CLR,0) } + LOAD = { CHANGED_HL(LOADBAR,0) } + PINDLY: + QA_O QB_O QC_O QD_O = { + CASE( + UPDN & TRN_HL, DELAY(4NS,-1,17NS), + CLEAR, DELAY(5NS,-1,17NS), + UPDN & TRN_LH, DELAY(4NS,-1,19NS), + LOAD & TRN_HL, DELAY(8NS,-1,28NS), + LOAD & TRN_LH, DELAY(8NS,-1,30NS), + DELAY(8NS,-1,30NS) + ) + } + BOBAR_O = { + CASE( + CHANGED(DOWN,0) & TRN_LH, DELAY(4NS,-1,16NS), + CLEAR, DELAY(5NS,-1,17NS), + CHANGED(DOWN,0) & TRN_HL, DELAY(5NS,-1,18NS), + LOAD & TRN_HL, DELAY(8NS,-1,28NS), + LOAD & TRN_LH, DELAY(8NS,-1,30NS), + DELAY(8NS,-1,30NS) + ) + } + COBAR_O = { + CASE( + CHANGED(UP,0) & TRN_LH, DELAY(4NS,-1,16NS), + CLEAR, DELAY(5NS,-1,17NS), + CHANGED(UP,0) & TRN_HL, DELAY(5NS,-1,18NS), + LOAD & TRN_HL, DELAY(8NS,-1,28NS), + LOAD & TRN_LH, DELAY(8NS,-1,30NS), + DELAY(8NS,-1,30NS) + ) + } + FREQ: + NODE = UP + MAXFREQ = 25MEG + FREQ: + NODE = DOWN + MAXFREQ = 25MEG + WIDTH: + NODE = UP + MIN_LO = 20NS + MIN_HI = 20NS + WIDTH: + NODE = DOWN + MIN_LO = 20NS + MIN_HI = 20NS + WIDTH: + NODE = LOADBAR + MIN_LO = 20NS + WHEN = { CLR!='1 } + WIDTH: + NODE = CLR + MIN_HI = 10NS + SETUP_HOLD: + DATA(4) = A B C D + CLOCK LH = LOADBAR + SETUPTIME = 20NS + HOLDTIME = 5NS + WHEN = { CLR!='1 } + SETUP_HOLD: + DATA(1) = CLR + CLOCK LH = UP + RELEASETIME_HL = 20NS + SETUP_HOLD: + DATA(1) = CLR + CLOCK LH = DOWN + RELEASETIME_HL = 20NS + SETUP_HOLD: + DATA(1) = LOADBAR + CLOCK LH = UP + RELEASETIME_LH = 20NS + WHEN = { CLR!='1 } + SETUP_HOLD: + DATA(1) = LOADBAR + CLOCK LH = DOWN + RELEASETIME_LH = 20NS + WHEN = { CLR!='1 } * .ENDS * *$ *--------- * 74ALS193 Synchronous 4-bit Up/Down Binary Counters (Dual clock w/ clear) * * ALS,AS LOGIC CIRCUITS DATA BOOK, 1986, TI * tc 7/27/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74ALS193 UP_I DOWN_I CLR_I LOADBAR_I A_I B_I C_I D_I + QA_O QB_O QC_O QD_O BOBAR_O COBAR_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 DFF(1) DPWR DGND SA RA MCLK QABAR QA QABAR + D0_EFF IO_ALS00 U2 DFF(1) DPWR DGND SB RB MCLK DB QB QBBAR + D0_EFF IO_ALS00 U3 DFF(1) DPWR DGND SC RC MCLK DC QC QCBAR + D0_EFF IO_ALS00 U4 DFF(1) DPWR DGND SD RD MCLK DD QD QDBAR + D0_EFF IO_ALS00 U5 SRFF(1) DPWR DGND UP DOWN $D_HI $D_LO $D_LO IU ID + D0_GFF IO_ALS00 * UALS193LOG LOGICEXP (14,22) DPWR DGND + UP_I DOWN_I CLR_I LOADBAR_I A_I B_I C_I D_I QABAR QBBAR QCBAR QDBAR IU ID + UP DOWN CLR LOADBAR A B C D BOBAR COBAR MCLK + SA RA SB RB SC RC SD RD DB DC DD + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} + LOGIC: + UP = { UP_I } + DOWN = { DOWN_I } + CLR = { CLR_I } + LOADBAR = { LOADBAR_I } + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + ICL = { ~CLR } + ILD = { ~LOADBAR } + MCLK = { UP & DOWN } + IQA = { ~QABAR } + IQB = { ~QBBAR } + IQC = { ~QCBAR } + IQD = { ~QDBAR } + IB1 = { IU & (IQA ^ IQB) } + IB2 = { (IQB ^ QABAR) & ID } + IC1 = { IU & ((IQA & IQB) ^ IQC) } + IC2 = { (IQC ^ (QABAR & QBBAR)) & ID } + ID1 = { IU & ((IQA & IQB & IQC) ^ IQD) } + ID2 = { (IQD ^ (QABAR & QBBAR & QCBAR)) & ID } + DB = { IB1 | IB2 } + DC = { IC1 | IC2 } + DD = { ID1 | ID2 } + SA = { ~(A & ICL & ILD) } + RA = { ~(~A & ILD) & ICL } + SB = { ~(B & ICL & ILD) } + RB = { ~(~B & ILD) & ICL } + SC = { ~(C & ICL & ILD) } + RC = { ~(~C & ILD) & ICL } + SD = { ~(D & ICL & ILD) } + RD = { ~(~D & ILD) & ICL } + COBAR = { ~(IQA & IQB & IQC & IQD & ~UP) } + BOBAR = { ~(QABAR & QBBAR & QCBAR & QDBAR & ~DOWN) } * UALS193DLY PINDLY (6,0,8) DPWR DGND + QA QB QC QD BOBAR COBAR + UP DOWN LOADBAR CLR A B C D + QA_O QB_O QC_O QD_O BOBAR_O COBAR_O + IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + UPDN = { (CHANGED_LH(UP,0) | CHANGED_LH(DOWN,0)) & LOADBAR!='0 + & CLR!='1 } + CLEAR = { CHANGED_LH(CLR,0) } + LOAD = { CHANGED_HL(LOADBAR,0) } + PINDLY: + QA_O QB_O QC_O QD_O = { + CASE( + UPDN & TRN_HL, DELAY(4NS,-1,17NS), + CLEAR, DELAY(5NS,-1,17NS), + UPDN & TRN_LH, DELAY(4NS,-1,19NS), + LOAD & TRN_HL, DELAY(8NS,-1,28NS), + LOAD & TRN_LH, DELAY(8NS,-1,30NS), + DELAY(8NS,-1,30NS) + ) + } + BOBAR_O = { + CASE( + CHANGED(DOWN,0) & TRN_LH, DELAY(4NS,-1,16NS), + CLEAR, DELAY(5NS,-1,17NS), + CHANGED(DOWN,0) & TRN_HL, DELAY(5NS,-1,18NS), + LOAD & TRN_HL, DELAY(8NS,-1,28NS), + LOAD & TRN_LH, DELAY(8NS,-1,30NS), + DELAY(8NS,-1,30NS) + ) + } + COBAR_O = { + CASE( + CHANGED(UP,0) & TRN_LH, DELAY(4NS,-1,16NS), + CLEAR, DELAY(5NS,-1,17NS), + CHANGED(UP,0) & TRN_HL, DELAY(5NS,-1,18NS), + LOAD & TRN_HL, DELAY(8NS,-1,28NS), + LOAD & TRN_LH, DELAY(8NS,-1,30NS), + DELAY(8NS,-1,30NS) + ) + } + FREQ: + NODE = UP + MAXFREQ = 30MEG + FREQ: + NODE = DOWN + MAXFREQ = 30MEG + WIDTH: + NODE = UP + MIN_LO = 16.5NS + MIN_HI = 16.5NS + WIDTH: + NODE = DOWN + MIN_LO = 16.5NS + MIN_HI = 16.5NS + WIDTH: + NODE = LOADBAR + MIN_LO = 20NS + WHEN = { CLR!='1 } + WIDTH: + NODE = CLR + MIN_HI = 10NS + SETUP_HOLD: + DATA(4) = A B C D + CLOCK LH = LOADBAR + SETUPTIME = 20NS + HOLDTIME = 5NS + WHEN = { CLR!='1 } + SETUP_HOLD: + DATA(1) = CLR + CLOCK LH = UP + RELEASETIME_HL = 20NS + SETUP_HOLD: + DATA(1) = CLR + CLOCK LH = DOWN + RELEASETIME_HL = 20NS + SETUP_HOLD: + DATA(1) = LOADBAR + CLOCK LH = UP + RELEASETIME_LH = 20NS + WHEN = { CLR!='1 } + SETUP_HOLD: + DATA(1) = LOADBAR + CLOCK LH = DOWN + RELEASETIME_LH = 20NS + WHEN = { CLR!='1 } * .ENDS * *$ *--------------------------------------------------------------------------- * 74ALS230 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS * * The ALS/AS Logic Data Book, 1986, TI * tvh 06/30/89 Update interface and model names * .subckt 74ALS230 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 1GBAR 2GBAR 1Y1 1Y2 1Y3 1Y4 + 2Y1 2Y2 2Y3 2Y4 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * DtoA switching time delay is greater than some of the gate delay. * UA inva(2) DPWR DGND + 1GBAR 2GBAR G1 G2 + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} U1 inv3a(4) DPWR DGND + 1A1 1A2 1A3 1A4 G1 1Y1 1Y2 1Y3 1Y4 + D_ALS230_1 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 buf3a(4) DPWR DGND + 2A1 2A2 2A3 2A4 G2 2Y1 2Y2 2Y3 2Y4 + D_ALS230_2 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS230_1 utgate ( + tplhmn=2ns tplhmx=9ns + tplhty=5ns tphlmn=2ns + tphlmx=9ns tphlty=5ns + tpzhmn=4ns tpzhmx=14ns + tpzhty=9ns tpzlmn=5ns + tpzlmx=18ns tpzlty=10ns + tphzmn=2ns tphzmx=10ns + tphzty=5ns tplzmn=3ns + tplzmx=12ns tplzty=6ns + ) .model D_ALS230_2 utgate ( + tplhmn=2ns tplhmx=9ns + tplhty=5ns tphlmn=2ns + tphlmx=9ns tphlty=5ns + tpzhmn=5ns tpzhmx=16ns + tpzhty=11ns tpzlmn=5ns + tpzlmx=19ns tpzlty=12ns + tphzmn=2ns tphzmx=10ns + tphzty=6ns tplzmn=3ns + tplzmx=13ns tplzty=7ns + ) *$ *--------------------------------------------------------------------------- * 74ALS231 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS * * The ALS/AS Logic Data Book, 1986, TI * tvh 06/30/89 Update interface and model names * .subckt 74ALS231 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 G1BAR G2 1Y1 1Y2 1Y3 1Y4 2Y1 + 2Y2 2Y3 2Y4 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * DtoA switching time delay is greater than some of the gate delay. * UA inv DPWR DGND + G1BAR G1 + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} U1 inv3a(4) DPWR DGND + 1A1 1A2 1A3 1A4 G1 1Y1 1Y2 1Y3 1Y4 + D_ALS231_1 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 inv3a(4) DPWR DGND + 2A1 2A2 2A3 2A4 G2 2Y1 2Y2 2Y3 2Y4 + D_ALS231_2 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS231_1 utgate ( + tplhmn=2ns tplhmx=9ns + tplhty=5ns tphlmn=2ns + tphlmx=9ns tphlty=5ns + tpzhmn=4ns tpzhmx=14ns + tpzhty=9ns tpzlmn=5ns + tpzlmx=18ns tpzlty=10ns + tphzmn=2ns tphzmx=10ns + tphzty=5ns tplzmn=3ns + tplzmx=12ns tplzty=6ns + ) .model D_ALS231_2 utgate ( + tplhmn=2ns tplhmx=9ns + tplhty=5ns tphlmn=2ns + tphlmx=9ns tphlty=5ns + tpzhmn=5ns tpzhmx=16ns + tpzhty=11ns tpzlmn=5ns + tpzlmx=19ns tpzlty=12ns + tphzmn=2ns tphzmx=10ns + tphzty=6ns tplzmn=3ns + tplzmx=13ns tplzty=7ns + ) *$ *--------- * 74ALS240A OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS * * The ALS/AS Logic Data Book, 1986, TI * tvh 06/30/89 Update interface and model names * .subckt 74ALS240A 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 G1BAR G2BAR 1Y1 1Y2 1Y3 1Y4 + 2Y1 2Y2 2Y3 2Y4 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * DtoA switching time delay is greater than some of the gate delay. * UAB inva(2) DPWR DGND + G1BAR G2BAR G1 G2 + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} U1 inv3a(4) DPWR DGND + 1A1 1A2 1A3 1A4 G1 1Y1 1Y2 1Y3 1Y4 + D_ALS240A IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 inv3a(4) DPWR DGND + 2A1 2A2 2A3 2A4 G2 2Y1 2Y2 2Y3 2Y4 + D_ALS240A IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS240A utgate ( + tplhmn=2ns tplhmx=9ns + tplhty=6ns tphlmn=2ns + tphlmx=9ns tphlty=5ns + tpzhmn=5ns tpzhmx=13ns + tpzhty=9ns tpzlmn=5ns + tpzlmx=18ns tpzlty=10ns + tphzmn=2ns tphzmx=10ns + tphzty=6ns tplzmn=3ns + tplzmx=12ns tplzty=7ns + ) *$ *--------- * 74ALS241A OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS * * The ALS/AS Logic Data Book, 1986, TI * tvh 06/30/89 Update interface and model names * jgt 09/08/92 Bug Fix: changed inverters to Buffers * .subckt 74ALS241A 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 G1BAR G2 1Y1 1Y2 1Y3 1Y4 + 2Y1 2Y2 2Y3 2Y4 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * DtoA switching time delay is greater than some of the gate delay. * UA inv DPWR DGND + G1BAR G1 + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} U1 buf3a(4) DPWR DGND + 1A1 1A2 1A3 1A4 G1 1Y1 1Y2 1Y3 1Y4 + D_ALS241A IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 buf3a(4) DPWR DGND + 2A1 2A2 2A3 2A4 G2 2Y1 2Y2 2Y3 2Y4 + D_ALS241A IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS241A utgate ( + tplhmn=3ns tplhmx=11ns + tphlmn=3ns tphlmx=10ns + tpzhmn=7ns tpzhmx=21ns + tpzlmn=7ns tpzlmx=21ns + tphzmn=2ns tphzmx=10ns + tplzmn=3ns tplzmx=15ns + ) * *$ *-------------------------------------------------------------------------- * 74ALS242B OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS * * The ALS/AS Logic Data Book, 1986, TI * tvh 06/30/89 Update interface and model names * .subckt 74ALS242B A1 A2 A3 A4 GABBAR GBA B1 B2 B3 B4 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * DtoA switching time delay is greater than some of the gate delay. * UA inv DPWR DGND + GABBAR GAB + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} U1 inv3a(4) DPWR DGND + A1 A2 A3 A4 GAB B1 B2 B3 B4 + D_ALS242B IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 inv3a(4) DPWR DGND + B1 B2 B3 B4 GBA A1 A2 A3 A4 + D_ALS242B IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS242B utgate ( + tplhmn=2ns tplhmx=11ns + tplhty=5ns tphlmn=2ns + tphlmx=10ns tphlty=5ns + tpzhmn=4ns tpzhmx=18ns + tpzhty=10ns tpzlmn=7ns + tpzlmx=21ns tpzlty=11ns + tphzmn=2ns tphzmx=14ns + tphzty=6ns tplzmn=2ns + tplzmx=12ns tplzty=5ns + ) *$ *-------------------------------------------------------------------------- * 74ALS243A OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS * * The ALS/AS Logic Data Book, 1986, TI * tvh 06/30/89 Update interface and model names * .subckt 74ALS243A A1 A2 A3 A4 GABBAR GBA B1 B2 B3 B4 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UA inv DPWR DGND + GABBAR GAB + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} U1 buf3a(4) DPWR DGND + A1 A2 A3 A4 GAB B1 B2 B3 B4 + D_ALS243A IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 buf3a(4) DPWR DGND + B1 B2 B3 B4 GBA A1 A2 A3 A4 + D_ALS243A IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS243A utgate ( + tplhmn=4ns tplhmx=11ns + tphlmn=4ns tphlmx=11ns + tpzhmn=7ns tpzhmx=20ns + tpzlmn=7ns tpzlmx=20ns + tphzmn=2ns tphzmx=14ns + tplzmn=3ns tplzmx=22ns + ) *$ *--------- * 74ALS244A OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS * * The ALS/AS Logic Data Book, 1986, TI * tvh 06/30/89 Update interface and model names * .subckt 74ALS244A 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 G1BAR G2BAR 1Y1 1Y2 1Y3 1Y4 + 2Y1 2Y2 2Y3 2Y4 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * DtoA switching time delay is greater than some of the gate delay. * UAB inva(2) DPWR DGND + G1BAR G2BAR G1 G2 + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} U1 buf3a(4) DPWR DGND + 1A1 1A2 1A3 1A4 G1 1Y1 1Y2 1Y3 1Y4 + D_ALS244A IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 buf3a(4) DPWR DGND + 2A1 2A2 2A3 2A4 G2 2Y1 2Y2 2Y3 2Y4 + D_ALS244A IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS244A utgate ( + tplhmn=3ns tplhmx=10ns + tphlmn=3ns tphlmx=10ns + tpzhmn=7ns tpzhmx=20ns + tpzlmn=7ns tpzlmx=20ns + tphzmn=2ns tphzmx=10ns + tplzmn=3ns tplzmx=13ns + ) *$ *--------- * 74ALS245A OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS * * ALS/AS LOGIC CIRCUITS DATA BOOK, 1986, TI * JLS 9-2-92 UPDATE TIMING * .SUBCKT 74ALS245A DIR_I GBAR_I + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 BUFA(2) DPWR DGND + DIR_I GBAR_I + DIR GBAR + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} U2 INV DPWR DGND + DIR DIRBAR + D0_GATE IO_ALS00 U3 NORA(2,2) DPWR DGND + DIRBAR GBAR DIR GBAR + ENABLEAB ENABLEBA + D0_GATE IO_ALS00 * U4 BUF3A(8) DPWR DGND + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + ENABLEAB + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + D_ALS245A IO_ALS00 + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U5 BUF3A(8) DPWR DGND + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + ENABLEBA + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + D_ALS245A IO_ALS00 + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} * .MODEL D_ALS245A UTGATE ( + TPLHMN=3NS TPLHMX=10NS + TPHLMN=3NS TPHLMX=10NS + TPZHMN=5NS TPZHMX=20NS + TPZLMN=5NS TPZLMX=20NS + TPHZMN=2NS TPHZMX=10NS + TPLZMN=4NS TPLZMX=15NS + ) * .ENDS * *$ *--------- * 74ALS251 MULTIPLEXER/DATA SELECTOR 8-1 LINE WITH 3-STATE OUTPUTS * * ALS/AS LOGIC CIRCUITS DATA BOOK, 1986, TI * TC 08/24/92 REMODELED USING LOGICEXP, PINDLY, & CONSTRAINT DEVICES * .SUBCKT 74ALS251 GBAR_I A_I B_I C_I D0_I D1_I D2_I D3_I D4_I D5_I D6_I D7_I + Y_O W_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UALS251LOG LOGICEXP(12,14) DPWR DGND + GBAR_I A_I B_I C_I D0_I D1_I D2_I D3_I D4_I D5_I D6_I D7_I + GBAR A B C D0 D1 D2 D3 D4 D5 D6 D7 W Y + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} + LOGIC: + GBAR = { GBAR_I } + A = { A_I } + B = { B_I } + C = { C_I } + D0 = { D0_I } + D1 = { D1_I } + D2 = { D2_I } + D3 = { D3_I } + D4 = { D4_I } + D5 = { D5_I } + D6 = { D6_I } + D7 = { D7_I } + IA = { ~A } + IB = { ~B } + IC = { ~C } + ID0 = { D0 & IA & IB & IC } + ID1 = { D1 & A & IB & IC } + ID2 = { D2 & IA & B & IC } + ID3 = { D3 & A & B & IC } + ID4 = { D4 & IA & IB & C } + ID5 = { D5 & A & IB & C } + ID6 = { D6 & IA & B & C } + ID7 = { D7 & A & B & C } + W = { ~(ID0 | ID1 | ID2 | ID3 | ID4 | ID5 | ID6 | ID7) } + Y = { ~W } * UALS251DLY PINDLY (2,1,11) DPWR DGND + W Y + GBAR + A B C D0 D1 D2 D3 D4 D5 D6 D7 + W_O Y_O + IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + DATA = { CHANGED(D0,0) | CHANGED(D1,0) | CHANGED(D2,0) | CHANGED(D3,0) | + CHANGED(D4,0) | CHANGED(D5,0) | CHANGED(D6,0) | CHANGED(D7,0) } + SELECT = { CHANGED(A,0) | CHANGED(B,0) | CHANGED(C,0) } + TRISTATE: + ENABLE LO GBAR + Y_O = { + CASE( + SELECT & TRN_HL, DELAY(8NS,-1,24NS), + SELECT & TRN_LH, DELAY(5NS,-1,18NS), + TRN_Z$, DELAY(3NS,-1,15NS), + DATA & TRN_HL, DELAY(3NS,-1,15NS), + DATA & TRN_LH, DELAY(2NS,-1,10NS), + TRN_HZ, DELAY(2NS,-1,10NS), + TRN_LZ, DELAY(1NS,-1,10NS), + DELAY(9NS,-1,25NS) + ) + } + W_O = { + CASE( + SELECT & TRN_LH, DELAY(8NS,-1,24NS), + SELECT & TRN_HL, DELAY(7NS,-1,23NS), + DATA, DELAY(3NS,-1,15NS), + TRN_Z$, DELAY(3NS,-1,15NS), + TRN_HZ, DELAY(2NS,-1,10NS), + TRN_LZ, DELAY(1NS,-1,10NS), + DELAY(9NS,-1,25NS) + ) + } * .ENDS * *$ *--------- * 74ALS253 DUAL 1-OF-4 DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS * * The ALS/AS Data Book, 1986, TI * JSW 8/24/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74ALS253 G1BAR_I G2BAR_I A_I B_I 1C0_I 1C1_I 1C2_I 1C3_I + 2C0_I 2C1_I 2C2_I 2C3_I Y1_O Y2_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UALS253LOG LOGICEXP(12,14) DPWR DGND + G1BAR_I G2BAR_I A_I B_I 1C0_I 1C1_I 1C2_I 1C3_I 2C0_I 2C1_I 2C2_I 2C3_I + G1BAR G2BAR A B 1C0 1C1 1C2 1C3 2C0 2C1 2C2 2C3 Y1 Y2 + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} + LOGIC: + G1BAR = { G1BAR_I } + G2BAR = { G2BAR_I } + A = { A_I } + B = { B_I } + 1C0 = { 1C0_I } + 1C1 = { 1C1_I } + 1C2 = { 1C2_I } + 1C3 = { 1C3_I } + 2C0 = { 2C0_I } + 2C1 = { 2C1_I } + 2C2 = { 2C2_I } + 2C3 = { 2C3_I } + G1 = { ~G1BAR } + G2 = { ~G2BAR } + ABAR = { ~A } + BBAR = { ~B } + I0 = { G1 & BBAR & ABAR & 1C0 } + I1 = { G1 & BBAR & A & 1C1 } + I2 = { G1 & B & ABAR & 1C2 } + I3 = { G1 & B & A & 1C3 } + I4 = { G2 & BBAR & ABAR & 2C0 } + I5 = { G2 & BBAR & A & 2C1 } + I6 = { G2 & B & ABAR & 2C2 } + I7 = { G2 & B & A & 2C3 } + Y1 = { I0 | I1 | I2 | I3 } + Y2 = { I4 | I5 | I6 | I7 } * UALS253DLY PINDLY (2,2,10) DPWR DGND + Y1 Y2 + G1BAR G2BAR + A B 1C0 1C1 1C2 1C3 2C0 2C1 2C2 2C3 + Y1_O Y2_O + IO_ALS00 + MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + BOOLEAN: + DATA1 = { (CHANGED(1C0,0) | CHANGED(1C1,0) | CHANGED(1C2,0) | + CHANGED(1C3,0)) } + DATA2 = { (CHANGED(2C0,0) | CHANGED(2C1,0) | CHANGED(2C2,0) | + CHANGED(2C3,0)) } + SELECT = { CHANGED(A,0) | CHANGED(B,0) } + TRISTATE: + ENABLE LO G1BAR + Y1_O = { + CASE( + TRN_ZH, DELAY(3NS,-1,14NS), + TRN_ZL, DELAY(4NS,-1,16NS), + TRN_HZ, DELAY(2NS,-1,10NS), + TRN_LZ, DELAY(2NS,-1,14NS), + SELECT, DELAY(5NS,-1,21NS), + DATA1 & TRN_LH, DELAY(2NS,-1,10NS), + DATA1 & TRN_HL, DELAY(3NS,-1,14NS), + DELAY(6NS,-1,22NS) + ) + } + TRISTATE: + ENABLE LO G2BAR + Y2_O = { + CASE( + TRN_ZH, DELAY(3NS,-1,14NS), + TRN_ZL, DELAY(4NS,-1,16NS), + TRN_HZ, DELAY(2NS,-1,10NS), + TRN_LZ, DELAY(2NS,-1,14NS), + SELECT, DELAY(5NS,-1,21NS), + DATA2 & TRN_LH, DELAY(2NS,-1,10NS), + DATA2 & TRN_HL, DELAY(3NS,-1,14NS), + DELAY(6NS,-1,22NS) + ) + } * .ENDS * *$ *--------- * 74ALS257 QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS * WITH 3-STATE OUTPUTS * * The ALS/AS Data Book, 1986, TI * JSW 8/25/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74ALS257 GBAR_I 1A_I 1B_I 2A_I 2B_I 3A_I 3B_I 4A_I 4B_I SEL_I + Y1_O Y2_O Y3_O Y4_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UALS257LOG LOGICEXP(10,14) DPWR DGND + GBAR_I 1A_I 1B_I 2A_I 2B_I 3A_I 3B_I 4A_I 4B_I SEL_I + GBAR 1A 1B 2A 2B 3A 3B 4A 4B SEL Y1 Y2 Y3 Y4 + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} + LOGIC: + GBAR = { GBAR_I } + 1A = { 1A_I } + 1B = { 1B_I } + 2A = { 2A_I } + 2B = { 2B_I } + 3A = { 3A_I } + 3B = { 3B_I } + 4A = { 4A_I } + 4B = { 4B_I } + SEL = { SEL_I } + SELBAR = { ~SEL } + Y1 = { (1A & SELBAR) | (1B & SEL) } + Y2 = { (2A & SELBAR) | (2B & SEL) } + Y3 = { (3A & SELBAR) | (3B & SEL) } + Y4 = { (4A & SELBAR) | (4B & SEL) } * UALS257DLY PINDLY (4,1,9) DPWR DGND + Y1 Y2 Y3 Y4 + GBAR + 1A 1B 2A 2B 3A 3B 4A 4B SEL + Y1_O Y2_O Y3_O Y4_O + IO_ALS00 + MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + BOOLEAN: + DATA = { CHANGED(1A,0) | CHANGED(1B,0) | CHANGED(2A,0) | CHANGED(2B,0) | + CHANGED(3A,0) | CHANGED(3B,0) | CHANGED(4A,0) | CHANGED(4B,0) } + SELECT = { CHANGED(SEL,0) } + TRISTATE: + ENABLE LO = GBAR + Y1_O Y2_O Y3_O Y4_O = { + CASE( + TRN_ZH, DELAY(4NS,-1,16NS), + TRN_ZL, DELAY(5NS,-1,18NS), + TRN_HZ, DELAY(2NS,-1,10NS), + TRN_LZ, DELAY(4NS,-1,15NS), + SELECT & TRN_LH, DELAY(7NS,-1,18NS), + SELECT & TRN_HL, DELAY(6NS,-1,22NS), + DATA & TRN_LH, DELAY(2NS,-1,10NS), + DATA & TRN_HL, DELAY(2NS,-1,12NS), + DELAY(8NS,-1,23NS) + ) + } * .ENDS * *$ *--------- * 74ALS258 QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS * WITH 3-STATE OUTPUTS * * The ALS/AS Data Book, 1986, TI * JSW 8/25/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74ALS258 GBAR_I 1A_I 1B_I 2A_I 2B_I 3A_I 3B_I 4A_I 4B_I SEL_I + Y1_O Y2_O Y3_O Y4_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UALS258LOG LOGICEXP(10,14) DPWR DGND + GBAR_I 1A_I 1B_I 2A_I 2B_I 3A_I 3B_I 4A_I 4B_I SEL_I + GBAR 1A 1B 2A 2B 3A 3B 4A 4B SEL Y1 Y2 Y3 Y4 + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} + LOGIC: + GBAR = { GBAR_I } + 1A = { 1A_I } + 1B = { 1B_I } + 2A = { 2A_I } + 2B = { 2B_I } + 3A = { 3A_I } + 3B = { 3B_I } + 4A = { 4A_I } + 4B = { 4B_I } + SEL = { SEL_I } + SELBAR = { ~SEL } + Y1 = { ~((1A & SELBAR) | (1B & SEL)) } + Y2 = { ~((2A & SELBAR) | (2B & SEL)) } + Y3 = { ~((3A & SELBAR) | (3B & SEL)) } + Y4 = { ~((4A & SELBAR) | (4B & SEL)) } * UALS258DLY PINDLY (4,1,9) DPWR DGND + Y1 Y2 Y3 Y4 + GBAR + 1A 1B 2A 2B 3A 3B 4A 4B SEL + Y1_O Y2_O Y3_O Y4_O + IO_ALS00 + MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + BOOLEAN: + DATA = { CHANGED(1A,0) | CHANGED(1B,0) | CHANGED(2A,0) | CHANGED(2B,0) | + CHANGED(3A,0) | CHANGED(3B,0) | CHANGED(4A,0) | CHANGED(4B,0) } + SELECT = { CHANGED(SEL,0) } + TRISTATE: + ENABLE LO = GBAR + Y1_O Y2_O Y3_O Y4_O = { + CASE( + SELECT & TRN_LH, DELAY(8NS,-1,20NS), + SELECT & TRN_HL, DELAY(5NS,-1,25NS), + TRN_Z$, DELAY(5NS,-1,18NS), + TRN_HZ, DELAY(2NS,-1,10NS), + TRN_LZ, DELAY(5NS,-1,18NS), + DATA & TRN_LH, DELAY(2NS,-1,8NS), + DATA & TRN_HL, DELAY(2NS,-1,7NS), + DELAY(9NS,-1,26NS) + ) + } * .ENDS * *$ *---------- * 74ALS259 8-BIT ADDRESSABLE LATCHES * * The ALS/AS Data Book, 1986, TI * tvh 09/11/89 Update interface and model names * .subckt 74ALS259 CLRBAR GBAR D S0 S1 S2 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 bufa(3) DPWR DGND + CLRBAR GBAR D RB GB DATA + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} U2 bufa(3) DPWR DGND + S0 S1 S2 SA SB SC + D_ALS259_1 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U3 inva(3) DPWR DGND + SA SB SC AB BB CB + D0_GATE IO_ALS00 U4 nanda(3,8) DPWR DGND + AB BB CB + SA BB CB + AB SB CB + SA SB CB + AB BB SC + SA BB SC + AB SB SC + SA SB SC + T0 T1 T2 T3 T4 T5 T6 T7 + D0_GATE IO_ALS00 U5 nora(2,8) DPWR DGND + GB T0 + GB T1 + GB T2 + GB T3 + GB T4 + GB T5 + GB T6 + GB T7 + G0 G1 G2 G3 G4 G5 G6 G7 + D0_GATE IO_ALS00 U6 ora(2,8) DPWR DGND + G0 RB + G1 RB + G2 RB + G3 RB + G4 RB + G5 RB + G6 RB + G7 RB + R0 R1 R2 R3 R4 R5 R6 R7 + D0_GATE IO_ALS00 U7 dltch(1) DPWR DGND + $D_HI R0 G0 DATA Q0 $D_NC + D_ALS259_2 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U8 dltch(1) DPWR DGND + $D_HI R1 G1 DATA Q1 $D_NC + D_ALS259_2 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U9 dltch(1) DPWR DGND + $D_HI R2 G2 DATA Q2 $D_NC + D_ALS259_2 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U10 dltch(1) DPWR DGND + $D_HI R3 G3 DATA Q3 $D_NC + D_ALS259_2 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U11 dltch(1) DPWR DGND + $D_HI R4 G4 DATA Q4 $D_NC + D_ALS259_2 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U12 dltch(1) DPWR DGND + $D_HI R5 G5 DATA Q5 $D_NC + D_ALS259_2 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U13 dltch(1) DPWR DGND + $D_HI R6 G6 DATA Q6 $D_NC + D_ALS259_2 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U14 dltch(1) DPWR DGND + $D_HI R7 G7 DATA Q7 $D_NC + D_ALS259_2 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS259_1 ugate ( + TPLHTY=2NS TPLHMX=2NS + TPHLTY=2NS TPHLMX=2NS + ) .model D_ALS259_2 ugff ( + TWGHMN=15NS TWPCLMN=10NS + TSUDGMN=15NS TPPCQHLMN=2NS + TPPCQHLTY=8NS TPPCQHLMX=12NS + TPDQLHMN=4NS TPDQLHTY=10NS + TPDQLHMX=19NS TPDQHLMN=2NS + TPDQHLTY=8NS TPDQHLMX=12NS + TPGQLHMN=4NS TPGQLHTY=13NS + TPGQLHMX=20NS TPGQHLMN=2NS + TPGQHLTY=8NS TPGQHLMX=13NS + ) *$ *---------- * 74ALS273 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR * * The ALS/AS Logic Data Book, 1986, TI * tvh 07/5/89 Update interface and model names * .subckt 74ALS273 CLRBAR CLK D1 D2 D3 D4 D5 D6 D7 D8 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UD dff(8) DPWR DGND + $D_HI CLRBAR CLK + D1 D2 D3 D4 D5 D6 D7 D8 + Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D_ALS273 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS273 ueff ( + TWCLKLMN=14NS TWCLKHMN=14NS + TWPCLMN=10NS TSUDCLKMN=10NS + TSUPCCLKHMN=15NS TPPCQHLMN=4NS + TPPCQHLMX=18NS TPCLKQLHMN=2NS + TPCLKQLHMX=12NS TPCLKQHLMN=3NS + TPCLKQHLMX=15NS + ) *$ *--------- * 74ALS280 PARITY GENERATOR/CHECKER ODD/EVEN 9-BIT * * ALS/AS LOGIC CIRCUITS DATA BOOK, 1986, TI * JLS 8-25-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES * .SUBCKT 74ALS280 A_I B_I C_I D_I E_I F_I G_I H_I I_I + EOUT_O OOUT_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UALS280LOG LOGICEXP (9,2) DPWR DGND + A_I B_I C_I D_I E_I F_I G_I H_I I_I + EOUT OOUT + D0_GATE IO_ALS00 + IO_LEVEL={IO_LEVEL} + + LOGIC: + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + E = { E_I } + F = { F_I } + G = { G_I } + H = { H_I } + I = { I_I } + + ABC = { (A & ~B & ~C) | (~A & B & ~C) | (~A & ~B & C) | (A & B & C) } + DEF = { (D & ~E & ~F) | (~D & E & ~F) | (~D & ~E & F) | (D & E & F) } + GHI = { (G & ~H & ~I) | (~G & H & ~I) | (~G & ~H & I) | (G & H & I) } + EOUT = { (~ABC & DEF & GHI) | (ABC & ~DEF & GHI) | (ABC & DEF & ~GHI) | + (~ABC & ~DEF & ~GHI) } + OOUT = { ~EOUT } * UALS280DLY PINDLY (2,0,0) DPWR DGND + EOUT OOUT + + EOUT_O OOUT_O + IO_ALS00 + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + PINDLY: + EOUT_O = { DELAY(3NS,12NS,20NS) } + OOUT_O = { + CASE ( + TRN_LH, DELAY(3NS,12NS,20NS), + DELAY(4NS,13NS,22NS) + ) + } * .ENDS * *$ *--------- * 74ALS299 8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS WITH 3-STATE OUTPUTS * * THE HIGH-SPEED CMOS LOGIC DATABOOK, 89, TI * KN 7-22-92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74ALS299 CLK_I CLRBAR_I S1_I S0_I G1BAR_I G2BAR_I SL_I SR_I + A/QA_B B/QB_B C/QC_B D/QD_B E/QE_B F/QF_B G/QG_B H/QH_B QAP_O QHP_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UALS299LOG LOGICEXP(32,25) DPWR DGND + CLK_I CLRBAR_I S1_I S0_I G1BAR_I G2BAR_I SL_I SR_I + A/QA_B B/QB_B C/QC_B D/QD_B E/QE_B F/QF_B G/QG_B H/QH_B ; BUFFERING + LA/QA LB/QB LC/QC LD/QD LE/QE LF/QF LG/QG LH/QH + A/QA B/QB C/QC D/QD E/QE F/QF G/QG H/QH + + CLK CLRBAR S1 S0 G1BAR G2BAR SL SR + A/QA B/QB C/QC D/QD E/QE F/QF G/QG H/QH + D1A D1B D1C D1D D1E D1F D1G D1H OE + D0_GATE IO_ALS00 + IO_LEVEL={IO_LEVEL} + LOGIC: * BUFFERING: + + CLK = { CLK_I } + CLRBAR = { CLRBAR_I } + S1 = { S1_I } + S0 = { S0_I } + G1BAR = { G1BAR_I } + G2BAR = { G2BAR_I } + SL = { SL_I } + SR = { SR_I } + A/QA = { A/QA_B } + B/QB = { B/QB_B } + C/QC = { C/QC_B } + D/QD = { D/QD_B } + E/QE = { E/QE_B } + F/QF = { F/QF_B } + G/QG = { G/QG_B } + H/QH = { H/QH_B } + * INTERMEDIATE TERMS: + S0S1 = { S0 & S1 } + S0/S1 = { S0 & ~S1 } + /S0S1 = { ~S0 & S1 } + /S0/S1 = { ~S0 & ~S1 } + * OUTPUTS: + D1A = { (S0/S1 & SR ) | (/S0S1 & LB/QB) | + (S0S1 & A/QA) | (/S0/S1 & LA/QA) } + D1B = { (S0/S1 & LA/QA) | (/S0S1 & LC/QC) | + (S0S1 & B/QB) | (/S0/S1 & LB/QB) } + D1C = { (S0/S1 & LB/QB) | (/S0S1 & LD/QD) | + (S0S1 & C/QC) | (/S0/S1 & LC/QC) } + D1D = { (S0/S1 & LC/QC) | (/S0S1 & LE/QE) | + (S0S1 & D/QD) | (/S0/S1 & LD/QD) } + D1E = { (S0/S1 & LD/QD) | (/S0S1 & LF/QF) | + (S0S1 & E/QE) | (/S0/S1 & LE/QE) } + D1F = { (S0/S1 & LE/QE) | (/S0S1 & LG/QG) | + (S0S1 & F/QF) | (/S0/S1 & LF/QF) } + D1G = { (S0/S1 & LF/QF) | (/S0S1 & LH/QH) | + (S0S1 & G/QG) | (/S0/S1 & LG/QG) } + D1H = { (S0/S1 & LG/QG) | (/S0S1 & SL ) | + (S0S1 & H/QH) | (/S0/S1 & LH/QH) } + OE = { G1BAR | G2BAR | (S1 & S0) } * U1 DFF(8) DPWR DGND $D_HI CLRBAR CLK + D1A D1B D1C D1D D1E D1F D1G D1H + LA/QA LB/QB LC/QC LD/QD LE/QE LF/QF LG/QG LH/QH + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D0_EFF IO_ALS00 * UALS299DLY PINDLY (10,1,17) DPWR DGND + LA/QA LB/QB LC/QC LD/QD LE/QE LF/QF LG/QG LH/QH LA/QA LH/QH + OE + G1BAR G2BAR CLK CLRBAR S1 S0 S0 A/QA B/QB C/QC D/QD E/QE F/QF G/QG H/QH SR SL + A/QA_B B/QB_B C/QC_B D/QD_B E/QE_B F/QF_B G/QG_B H/QH_B QAP_O QHP_O + IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + ENABLE1 = { G1BAR != '1 & G2BAR != '1 } + ENABLE2 = { S1 != '1 | S0 != '1 } + DISABLE1 = { G1BAR != '0 | G2BAR != '0 } + DISABLE2 = { S1 != '0 & S0 != '0 } + + PINDLY: + QAP_O QHP_O = { + CASE( + CHANGED_LH(CLK,0) & TRN_LH, DELAY(5NS,-1,15NS), + CHANGED_LH(CLK,0) & TRN_HL, DELAY(8NS,-1,18NS), + CHANGED_HL(CLRBAR,0) & TRN_HL, DELAY(6NS,-1,22NS), + DELAY(9NS,-1,23NS) ;DEFAULT + ) + } + + TRISTATE: + ENABLE LO OE + A/QA_B B/QB_B C/QC_B D/QD_B E/QE_B F/QF_B G/QG_B H/QH_B = { + CASE( + ENABLE1 & TRN_ZH, DELAY(6NS,-1,16NS), + ENABLE2 & TRN_ZH, DELAY(7NS,-1,17NS), + ENABLE1 & TRN_ZL, DELAY(8NS,-1,22NS), + ENABLE2 & TRN_ZL, DELAY(8NS,-1,22NS), + DISABLE1 & TRN_HZ, DELAY(1NS,-1,8NS), + DISABLE2 & TRN_HZ, DELAY(1NS,-1,12NS), + DISABLE1 & TRN_LZ, DELAY(5NS,-1,15NS), + DISABLE2 & TRN_LZ, DELAY(8NS,-1,25NS), + CHANGED_LH(CLK,0) & TRN_LH, DELAY(4NS,-1,13NS), + CHANGED_LH(CLK,0) & TRN_HL, DELAY(7NS,-1,19NS), + CHANGED_HL(CLRBAR,0) & TRN_HL, DELAY(6NS,-1,22NS), + DELAY(9NS,-1,23NS) ;DEFAULT + ) + } + + FREQ: + NODE = CLK + MAXFREQ = 30MEG + + WIDTH: + NODE = CLK + MIN_HI = 16.5NS + MIN_LO = 16.5NS + + WIDTH: + NODE = CLRBAR + MIN_LO = 10NS + + SETUP_HOLD: + DATA(2) = S1 S0 + CLOCK LH = CLK + SETUPTIME = 20NS + WHEN = { CLRBAR!='0 } + + SETUP_HOLD: + DATA(8) = A/QA B/QB C/QC D/QD E/QE F/QF G/QG H/QH + CLOCK LH = CLK + SETUPTIME_HI = 16NS + SETUPTIME_LO = 6NS + WHEN = { CLRBAR!='0 + & (S1!='0 ^ CHANGED(S1,0)) + & (S0!='0 ^ CHANGED(S0,0)) } + + SETUP_HOLD: + DATA(1) = SL + CLOCK LH = CLK + SETUPTIME_HI = 16NS + SETUPTIME_LO = 6NS + WHEN = { CLRBAR!='0 + & (S1!='0 ^ CHANGED(S1,0)) + & (S0!='1 ^ CHANGED(S0,0)) } + + SETUP_HOLD: + DATA(1) = SR + CLOCK LH = CLK + SETUPTIME_HI = 16NS + SETUPTIME_LO = 6NS + WHEN = { CLRBAR!='0 + & (S1!='1 ^ CHANGED(S1,0)) + & (S0!='0 ^ CHANGED(S0,0)) } + + SETUP_HOLD: + DATA(1) = CLRBAR + CLOCK LH = CLK + RELEASETIME_LH = 15NS * .ENDS * *$ *--------- * 74ALS323 8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS * * THE ALS/AS LOGIC CIRCUITS DATABOOK, 86, TI * KN 7-22-92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74ALS323 CLK_I CLRBAR_I S1_I S0_I G1BAR_I G2BAR_I SL_I SR_I + A/QA_B B/QB_B C/QC_B D/QD_B E/QE_B F/QF_B G/QG_B H/QH_B QAP_O QHP_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UALS323LOG LOGICEXP(32,25) DPWR DGND + CLK_I CLRBAR_I S1_I S0_I G1BAR_I G2BAR_I SL_I SR_I + A/QA_B B/QB_B C/QC_B D/QD_B E/QE_B F/QF_B G/QG_B H/QH_B ; BUFFERING + LA/QA LB/QB LC/QC LD/QD LE/QE LF/QF LG/QG LH/QH + A/QA B/QB C/QC D/QD E/QE F/QF G/QG H/QH + + CLK CLRBAR S1 S0 G1BAR G2BAR SL SR + A/QA B/QB C/QC D/QD E/QE F/QF G/QG H/QH + D1A D1B D1C D1D D1E D1F D1G D1H OE + D0_GATE IO_ALS00 + IO_LEVEL={IO_LEVEL} + LOGIC: + * BUFFERING: + CLK = { CLK_I } + CLRBAR = { CLRBAR_I } + S1 = { S1_I } + S0 = { S0_I } + G1BAR = { G1BAR_I } + G2BAR = { G2BAR_I } + SL = { SL_I } + SR = { SR_I } + A/QA = { A/QA_B } + B/QB = { B/QB_B } + C/QC = { C/QC_B } + D/QD = { D/QD_B } + E/QE = { E/QE_B } + F/QF = { F/QF_B } + G/QG = { G/QG_B } + H/QH = { H/QH_B } + * INTERMEDIATE TERMS: + SA = { ~(S0 | ~CLRBAR) } + SB = { ~(SA | ~CLRBAR) } + + S0S1 = { SB & S1 } + S0/S1 = { SB & ~S1 } + /S0S1 = { SA & S1 } + /S0/S1 = { SA & ~S1 } + * OUTPUTS: + D1A = { (S0/S1 & SR ) | (/S0S1 & LB/QB) | (S0S1 & A/QA) + | (/S0/S1 & LA/QA) } + D1B = { (S0/S1 & LA/QA) | (/S0S1 & LC/QC) | (S0S1 & B/QB) + | (/S0/S1 & LB/QB) } + D1C = { (S0/S1 & LB/QB) | (/S0S1 & LD/QD) | (S0S1 & C/QC) + | (/S0/S1 & LC/QC) } + D1D = { (S0/S1 & LC/QC) | (/S0S1 & LE/QE) | (S0S1 & D/QD) + | (/S0/S1 & LD/QD) } + D1E = { (S0/S1 & LD/QD) | (/S0S1 & LF/QF) | (S0S1 & E/QE) + | (/S0/S1 & LE/QE) } + D1F = { (S0/S1 & LE/QE) | (/S0S1 & LG/QG) | (S0S1 & F/QF) + | (/S0/S1 & LF/QF) } + D1G = { (S0/S1 & LF/QF) | (/S0S1 & LH/QH) | (S0S1 & G/QG) + | (/S0/S1 & LG/QG) } + D1H = { (S0/S1 & LG/QG) | (/S0S1 & SL ) | (S0S1 & H/QH) + | (/S0/S1 & LH/QH) } + OE = { G1BAR | G2BAR | (S1 & S0) } * U1 DFF(8) DPWR DGND $D_HI CLRBAR CLK + D1A D1B D1C D1D D1E D1F D1G D1H + LA/QA LB/QB LC/QC LD/QD LE/QE LF/QF LG/QG LH/QH + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D0_EFF IO_ALS00 * UALS323DLY PINDLY (10,1,17) DPWR DGND + LA/QA LB/QB LC/QC LD/QD LE/QE LF/QF LG/QG LH/QH LA/QA LH/QH + OE + G1BAR G2BAR CLK CLRBAR S1 S0 S0 A/QA B/QB C/QC D/QD E/QE F/QF G/QG H/QH SR SL + A/QA_B B/QB_B C/QC_B D/QD_B E/QE_B F/QF_B G/QG_B H/QH_B QAP_O QHP_O + IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + ENABLE1 = { G1BAR!='1 & G2BAR!='1 } + ENABLE2 = { S1!='1 | S0!='1 } + DISABLE1 = { G1BAR!='0 | G2BAR!='0 } + DISABLE2 = { S1!='0 & S0!='0 } + CLOCK = { CHANGED_LH(CLK,0) } + + PINDLY: + QAP_O QHP_O = { + CASE( + CLOCK & TRN_LH, DELAY(5NS,-1,15NS), + CLOCK & TRN_HL, DELAY(8NS,-1,18NS), + CHANGED(CLRBAR,0) & TRN_HL, DELAY(6NS,-1,22NS), + DELAY(9NS,-1,23NS) ;DEFAULT + ) + } + + TRISTATE: + ENABLE LO OE + A/QA_B B/QB_B C/QC_B D/QD_B E/QE_B F/QF_B G/QG_B H/QH_B = { + CASE( + ENABLE1 & TRN_ZH, DELAY(6NS,-1,16NS), + ENABLE2 & TRN_ZH, DELAY(7NS,-1,17NS), + ENABLE1 & TRN_ZL, DELAY(8NS,-1,22NS), + ENABLE2 & TRN_ZL, DELAY(8NS,-1,22NS), + DISABLE1 & TRN_HZ, DELAY(1NS,-1,8NS), + DISABLE2 & TRN_HZ, DELAY(1NS,-1,12NS), + DISABLE1 & TRN_LZ, DELAY(5NS,-1,15NS), + DISABLE2 & TRN_LZ, DELAY(8NS,-1,25NS), + CLOCK & TRN_LH, DELAY(4NS,-1,13NS), + CLOCK & TRN_HL, DELAY(7NS,-1,19NS), + CHANGED(CLRBAR,0) & TRN_HL, DELAY(6NS,-1,22NS), + DELAY(9NS,-1,26NS) ;DEFAULT + ) + } + + FREQ: + NODE = CLK + MAXFREQ = 30MEG + + WIDTH: + NODE = CLK + MIN_HI = 16.5NS + MIN_LO = 16.5NS + + SETUP_HOLD: + DATA(1) = CLRBAR + CLOCK LH = CLK + SETUPTIME_LO = 20NS + SETUPTIME_HI = 16NS + + SETUP_HOLD: + DATA(2) = S1 S0 + CLOCK LH = CLK + SETUPTIME = 20NS + WHEN = { CLRBAR!='0 } + + SETUP_HOLD: + DATA(8) = A/QA B/QB C/QC D/QD E/QE F/QF G/QG H/QH + CLOCK LH = CLK + SETUPTIME_HI = 16NS + SETUPTIME_LO = 6NS + WHEN = { CLRBAR!='0 + & (S1!='0 ^ CHANGED(S1,0)) & (S0!='0 ^ CHANGED(S0,0)) } + + SETUP_HOLD: + DATA(1) = SL + CLOCK LH = CLK + SETUPTIME_HI = 16NS + SETUPTIME_LO = 6NS + WHEN = { CLRBAR!='0 + & (S1!='0 ^ CHANGED(S1,0)) & (S0!='1 ^ CHANGED(S0,0)) } + + SETUP_HOLD: + DATA(1) = SR + CLOCK LH = CLK + SETUPTIME_HI = 16NS + SETUPTIME_LO = 6NS + WHEN = { CLRBAR!='0 + & (S1!='1 ^ CHANGED(S1,0)) & (S0!='0 ^ CHANGED(S0,0)) } * .ENDS * *$ *------------------------------------------------------------------------- * 74ALS352 DUAL 4-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS * * The ALS/AS Data Book, 1986, TI * JSW 8/24/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74ALS352 G1BAR_I G2BAR_I A_I B_I 1C0_I 1C1_I 1C2_I 1C3_I + 2C0_I 2C1_I 2C2_I 2C3_I Y1_O Y2_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UALS352LOG LOGICEXP(12,14) DPWR DGND + G1BAR_I G2BAR_I A_I B_I 1C0_I 1C1_I 1C2_I 1C3_I 2C0_I 2C1_I 2C2_I 2C3_I + G1BAR G2BAR A B 1C0 1C1 1C2 1C3 2C0 2C1 2C2 2C3 Y1 Y2 + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} + LOGIC: + G1BAR = { G1BAR_I } + G2BAR = { G2BAR_I } + A = { A_I } + B = { B_I } + 1C0 = { 1C0_I } + 1C1 = { 1C1_I } + 1C2 = { 1C2_I } + 1C3 = { 1C3_I } + 2C0 = { 2C0_I } + 2C1 = { 2C1_I } + 2C2 = { 2C2_I } + 2C3 = { 2C3_I } + G1 = { ~G1BAR } + G2 = { ~G2BAR } + ABAR = { ~A } + BBAR = { ~B } + I0 = { G1 & BBAR & ABAR & 1C0 } + I1 = { G1 & BBAR & A & 1C1 } + I2 = { G1 & B & ABAR & 1C2 } + I3 = { G1 & B & A & 1C3 } + I4 = { G2 & BBAR & ABAR & 2C0 } + I5 = { G2 & BBAR & A & 2C1 } + I6 = { G2 & B & ABAR & 2C2 } + I7 = { G2 & B & A & 2C3 } + Y1 = { ~(I0 | I1 | I2 | I3) } + Y2 = { ~(I4 | I5 | I6 | I7) } * UALS352DLY PINDLY (2,0,12) DPWR DGND + Y1 Y2 + G1BAR G2BAR A B 1C0 1C1 1C2 1C3 2C0 2C1 2C2 2C3 + Y1_O Y2_O + IO_ALS00 + MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + BOOLEAN: + DATA1 = { (CHANGED(1C0,0) | CHANGED(1C1,0) | CHANGED(1C2,0) | + CHANGED(1C3,0)) } + DATA2 = { (CHANGED(2C0,0) | CHANGED(2C1,0) | CHANGED(2C2,0) | + CHANGED(2C3,0)) } + SELECT = { CHANGED(A,0) | CHANGED(B,0) } + PINDLY: + Y1_O = { + CASE( + SELECT & TRN_LH, DELAY(5NS,-1,24NS), + SELECT & TRN_HL, DELAY(5NS,-1,21NS), + CHANGED(G1BAR,0) & TRN_HL, DELAY(4NS,-1,20NS), + CHANGED(G1BAR,0) & TRN_LH, DELAY(4NS,-1,18NS), + DATA1 & TRN_LH, DELAY(3NS,-1,18NS), + DATA1 & TRN_HL, DELAY(2NS,-1,13NS), + DELAY(6NS,-1,25NS) + ) + } + Y2_O = { + CASE( + SELECT & TRN_LH, DELAY(5NS,-1,24NS), + SELECT & TRN_HL, DELAY(5NS,-1,21NS), + CHANGED(G2BAR,0) & TRN_HL, DELAY(4NS,-1,20NS), + CHANGED(G2BAR,0) & TRN_LH, DELAY(4NS,-1,18NS), + DATA2 & TRN_LH, DELAY(3NS,-1,18NS), + DATA2 & TRN_HL, DELAY(2NS,-1,13NS), + DELAY(6NS,-1,25NS) + ) + } * .ENDS * *$ *------------------------------------------------------------------------- * 74ALS353 DUAL 1-OF-4 DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS * * The ALS/AS Data Book, 1986, TI * JSW 8/24/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74ALS353 G1BAR_I G2BAR_I A_I B_I 1C0_I 1C1_I 1C2_I 1C3_I + 2C0_I 2C1_I 2C2_I 2C3_I Y1_O Y2_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UALS353LOG LOGICEXP(12,14) DPWR DGND + G1BAR_I G2BAR_I A_I B_I 1C0_I 1C1_I 1C2_I 1C3_I 2C0_I 2C1_I 2C2_I 2C3_I + G1BAR G2BAR A B 1C0 1C1 1C2 1C3 2C0 2C1 2C2 2C3 Y1 Y2 + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} + LOGIC: + G1BAR = { G1BAR_I } + G2BAR = { G2BAR_I } + A = { A_I } + B = { B_I } + 1C0 = { 1C0_I } + 1C1 = { 1C1_I } + 1C2 = { 1C2_I } + 1C3 = { 1C3_I } + 2C0 = { 2C0_I } + 2C1 = { 2C1_I } + 2C2 = { 2C2_I } + 2C3 = { 2C3_I } + G1 = { ~G1BAR } + G2 = { ~G2BAR } + ABAR = { ~A } + BBAR = { ~B } + I0 = { G1 & BBAR & ABAR & 1C0 } + I1 = { G1 & BBAR & A & 1C1 } + I2 = { G1 & B & ABAR & 1C2 } + I3 = { G1 & B & A & 1C3 } + I4 = { G2 & BBAR & ABAR & 2C0 } + I5 = { G2 & BBAR & A & 2C1 } + I6 = { G2 & B & ABAR & 2C2 } + I7 = { G2 & B & A & 2C3 } + Y1 = { ~(I0 | I1 | I2 | I3) } + Y2 = { ~(I4 | I5 | I6 | I7) } * UALS353DLY PINDLY (2,2,10) DPWR DGND + Y1 Y2 + G1BAR G2BAR + A B 1C0 1C1 1C2 1C3 2C0 2C1 2C2 2C3 + Y1_O Y2_O + IO_ALS00 + MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + BOOLEAN: + DATA1 = { (CHANGED(1C0,0) | CHANGED(1C1,0) | CHANGED(1C2,0) | + CHANGED(1C3,0)) } + DATA2 = { (CHANGED(2C0,0) | CHANGED(2C1,0) | CHANGED(2C2,0) | + CHANGED(2C3,0)) } + SELECT = { CHANGED(A,0) | CHANGED(B,0) } + TRISTATE: + ENABLE LO G1BAR + Y1_O = { + CASE( + TRN_ZH, DELAY(3NS,-1,13NS), + TRN_ZL, DELAY(2NS,-1,16NS), + TRN_HZ, DELAY(2NS,-1,10NS), + TRN_LZ, DELAY(2NS,-1,14NS), + SELECT & TRN_LH, DELAY(5NS,-1,24NS), + SELECT & TRN_HL, DELAY(5NS,-1,21NS), + DATA1 & TRN_LH, DELAY(4NS,-1,18NS), + DATA1 & TRN_HL, DELAY(3NS,-1,13NS), + DELAY(6NS,-1,25NS) + ) + } + TRISTATE: + ENABLE LO G2BAR + Y2_O = { + CASE( + TRN_ZH, DELAY(3NS,-1,13NS), + TRN_ZL, DELAY(2NS,-1,16NS), + TRN_HZ, DELAY(2NS,-1,10NS), + TRN_LZ, DELAY(2NS,-1,14NS), + SELECT & TRN_LH, DELAY(5NS,-1,24NS), + SELECT & TRN_HL, DELAY(5NS,-1,21NS), + DATA2 & TRN_LH, DELAY(4NS,-1,18NS), + DATA2 & TRN_HL, DELAY(3NS,-1,13NS), + DELAY(6NS,-1,25NS) + ) + } * .ENDS * *$ *---------- * 74ALS373 Octal D-Type Transparent Latches with 3-STATE Outputs * * The ALS/AS Data Book, 1986, TI * atl 7/18/89 Update interface and model names * .subckt 74ALS373 OCBAR C 1D 2D 3D 4D 5D 6D 7D 8D 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UA inv DPWR DGND + OCBAR OC + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} U1 dltch(8) DPWR DGND + $D_HI $D_HI C + 1D 2D 3D 4D 5D 6D 7D 8D + 1QI 2QI 3QI 4QI 5QI 6QI 7QI 8QI + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D_ALS373_1 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 buf3a(8) DPWR DGND + 1QI 2QI 3QI 4QI 5QI 6QI 7QI 8QI + OC + 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q + D_ALS373_2 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS373_1 ugff ( + tpgqlhmn=4ns tpgqlhmx=10ns + tpgqhlmn=3ns tpgqhlmx=7ns + twghmn=10ns tsudgmn=10ns + thdgmn=7ns + ) .model D_ALS373_2 utgate ( + tplhmn=2ns tplhmx=12ns + tphlmn=4ns tphlmx=16ns + tpzhmn=6ns tpzhmx=18ns + tpzlmn=5ns tpzlmx=20ns + tphzmn=2ns tphzmx=10ns + tplzmn=2ns tplzmx=12ns + ) *$ *---------- * 74ALS374 Octal D-Type Edge-Triggered Flip-Flops with 3-STATE Outputs * * The ALS/AS Data Book, 1986, TI * atl 7/18/89 Update interface and model names * .subckt 74ALS374 OCBAR CLK D1 D2 D3 D4 D5 D6 D7 D8 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UOC inv DPWR DGND + OCBAR OC + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} UD dff(8) DPWR DGND + $D_HI $D_HI CLK + D1 D2 D3 D4 D5 D6 D7 D8 + SQ1 SQ2 SQ3 SQ4 SQ5 SQ6 SQ7 SQ8 + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D_ALS374_1 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UQS buf3a(8) DPWR DGND + SQ1 SQ2 SQ3 SQ4 SQ5 SQ6 SQ7 SQ8 + OC + Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 + D_ALS374_2 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS374_1 ueff ( + twclklmn=14ns twclkhmn=14ns + tsudclkmn=10ns + ) .model D_ALS374_2 utgate ( + tplhmn=3ns tplhmx=12ns + tphlmn=5ns tphlmx=16ns + tpzhmn=5ns tpzhmx=17ns + tpzlmn=7ns tpzlmx=18ns + tphzmn=2ns tphzmx=10ns + tplzmn=3ns tplzmx=18ns + ) *$ *--------- * 74ALS377 Octal D-TYPE Flip-Flops with Clock Enable * * 1989 Signetics, Updated 8-29-90 * .subckt 74ALS377 OEBAR CP D0 D1 D2 D3 D4 D5 D6 D7 O0 O1 O2 O3 O4 O5 O6 O7 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UINV inva(4) DPWR DGND + OEBAR CP OE CPBAR OE CPBAR IN1 CP2 + D0_GATE IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UA0 ao(2,2) DPWR DGND + OE D0 IN1 QBUF0 DD0 + D0_GATE IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UA1 ao(2,2) DPWR DGND + OE D1 IN1 QBUF1 DD1 + D0_GATE IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UA2 ao(2,2) DPWR DGND + OE D2 IN1 QBUF2 DD2 + D0_GATE IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UA3 ao(2,2) DPWR DGND + OE D3 IN1 QBUF3 DD3 + D0_GATE IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UA4 ao(2,2) DPWR DGND + OE D4 IN1 QBUF4 DD4 + D0_GATE IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UA5 ao(2,2) DPWR DGND + OE D5 IN1 QBUF5 DD5 + D0_GATE IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UA6 ao(2,2) DPWR DGND + OE D6 IN1 QBUF6 DD6 + D0_GATE IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UA7 ao(2,2) DPWR DGND + OE D7 IN1 QBUF7 DD7 + D0_GATE IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U20 dff(8) DPWR DGND + $D_HI $D_HI CP2 + DD0 DD1 DD2 DD3 DD4 DD5 DD6 DD7 + QBUF0 QBUF1 QBUF2 QBUF3 QBUF4 QBUF5 QBUF6 QBUF7 + $D_NC $D_NC $DNC $D_NC $D_NC $D_NC $D_NC $D_NC + D_ALS377_1 IO_ALS00 U30 bufa(8) DPWR DGND + QBUF0 QBUF1 QBUF2 QBUF3 QBUF4 QBUF5 QBUF6 QBUF7 + O0 O1 O2 O3 O4 O5 O6 O7 + D0_GATE IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS377_1 ueff ( + tpclkqlhmn=2ns tpclkqlhmx=12ns + tpclkqhlmn=2ns tpclkqhlmx=15ns + tsudclkmn=10ns thdclkmn=0ns + twclklmn=14ns twclkhmn=14ns + ) *$ *------------------------------------------------------------------------- * 74ALS465A Octal Buffers with 3-STATE Outputs * * The ALS/AS Data Book, 1986, TI * atl 7/18/89 Update interface and model names * .subckt 74ALS465A A1 A2 A3 A4 A5 A6 A7 A8 G1BAR G2BAR Y1 Y2 Y3 Y4 Y5 Y6 Y7 + Y8 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UA nor(2) DPWR DGND + G1BAR G2BAR E + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} UB buf3a(8) DPWR DGND + A1 A2 A3 A4 A5 A6 A7 A8 + E + Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 + D_ALS465A IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS465A utgate ( + tplhmn=2ns tplhmx=13ns + tphlmn=4ns tphlmx=12ns + tpzhmn=4ns tpzhmx=23ns + tpzlmn=5ns tpzlmx=25ns + tphzmn=2ns tphzmx=10ns + tplzmn=3ns tplzmx=18ns + ) *$ *------------------------------------------------------------------------- * 74ALS466A Octal Buffers with 3-STATE Outputs * * The ALS/AS Data Book, 1986, TI * atl 7/18/89 Update interface and model names * .subckt 74ALS466A A1 A2 A3 A4 A5 A6 A7 A8 G1BAR G2BAR Y1 Y2 Y3 Y4 Y5 Y6 Y7 + Y8 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UA nor(2) DPWR DGND + G1BAR G2BAR E + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} UB inv3a(8) DPWR DGND + A1 A2 A3 A4 A5 A6 A7 A8 + E + Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 + D_ALS466A IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS466A utgate ( + tplhmn=3ns tplhmx=12ns + tphlmn=2ns tphlmx=9ns + tpzhmn=4ns tpzhmx=16ns + tpzlmn=7ns tpzlmx=23ns + tphzmn=2ns tphzmx=10ns + tplzmn=2ns tplzmx=17ns + ) *$ *------------------------------------------------------------------------- * 74ALS467A Octal Buffers with 3-STATE Outputs * * The ALS/AS Data Book, 1986, TI * atl 06/27/89 Update interface and model names * .subckt 74ALS467A 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 G1BAR G2 1Y1 1Y2 1Y3 1Y4 + 2Y1 2Y2 2Y3 2Y4 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UA inv DPWR DGND + G1BAR G1 + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} UB buf3a(4) DPWR DGND + 1A1 1A2 1A3 1A4 G1 1Y1 1Y2 1Y3 1Y4 + D_ALS467A IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UC buf3a(4) DPWR DGND + 2A1 2A2 2A3 2A4 G2 2Y1 2Y2 2Y3 2Y4 + D_ALS467A IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS467A utgate ( + tplhmn=2ns tplhmx=13ns + tphlmn=4ns tphlmx=12ns + tpzhmn=4ns tpzhmx=23ns + tpzlmn=5ns tpzlmx=25ns + tphzmn=2ns tphzmx=10ns + tplzmn=3ns tplzmx=18ns + ) *$ *------------------------------------------------------------------------- * 74ALS468A Octal Buffers with 3-STATE Outputs * * The ALS/AS Data Book, 1986, TI * atl 7/18/89 Update interface and model names * .subckt 74ALS468A 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 G1BAR G2BAR 1Y1 1Y2 1Y3 1Y4 + 2Y1 2Y2 2Y3 2Y4 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UINV inva(2) DPWR DGND + G1BAR G2BAR G1 G2 + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} U1 inv3a(4) DPWR DGND + 1A1 1A2 1A3 1A4 G1 1Y1 1Y2 1Y3 1Y4 + D_ALS468A IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 inv3a(4) DPWR DGND + 2A1 2A2 2A3 2A4 G2 2Y1 2Y2 2Y3 2Y4 + D_ALS468A IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS468A utgate ( + tplhmn=3ns tplhmx=12ns + tphlmn=2ns tphlmx=9ns + tpzhmn=4ns tpzhmx=16ns + tpzlmn=7ns tpzlmx=23ns + tphzmn=2ns tphzmx=10ns + tplzmn=2ns tplzmx=17ns + ) *$ *------------------------------------------------------------------------- * 74ALS518 8-BIT IDENTITY COMPARATORS WITH OPEN-COLLECTOR OUTPUTS * * ALS/AS LOGIC CIRCUITS DATA BOOK, 1986, TI * NH 8/21/92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74ALS518 P7_I P6_I P5_I P4_I P3_I P2_I P1_I P0_I Q7_I Q6_I Q5_I Q4_I + Q3_I Q2_I Q1_I Q0_I GBAR_I PEQ_O + OPTIONAL: DPWR = $G_DPWR DGND = $G_DGND + PARAMS: MNTYMXDLY = 0 IO_LEVEL = 0 * UALS518LOG LOGICEXP(17,18) DPWR DGND + P7_I P6_I P5_I P4_I P3_I P2_I P1_I P0_I + Q7_I Q6_I Q5_I Q4_I Q3_I Q2_I Q1_I Q0_I GBAR_I + P7 P6 P5 P4 P3 P2 P1 P0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 GBAR PEQ + D0_GATE IO_ALS00 IO_LEVEL = {IO_LEVEL} + + LOGIC: + P7 = { P7_I } + P6 = { P6_I } + P5 = { P5_I } + P4 = { P4_I } + P3 = { P3_I } + P2 = { P2_I } + P1 = { P1_I } + P0 = { P0_I } + Q7 = { Q7_I } + Q6 = { Q6_I } + Q5 = { Q5_I } + Q4 = { Q4_I } + Q3 = { Q3_I } + Q2 = { Q2_I } + Q1 = { Q1_I } + Q0 = { Q0_I } + GBAR = { GBAR_I } + + PEQ7 = { ~(~P7 ^ ~Q7) } + PEQ6 = { ~(~P6 ^ ~Q6) } + PEQ5 = { ~(~P5 ^ ~Q5) } + PEQ4 = { ~(~P4 ^ ~Q4) } + PEQ3 = { ~(~P3 ^ ~Q3) } + PEQ2 = { ~(~P2 ^ ~Q2) } + PEQ1 = { ~(~P1 ^ ~Q1) } + PEQ0 = { ~(~P0 ^ ~Q0) } + + PEQ = { (PEQ7 & PEQ6 & PEQ5 & PEQ4 & PEQ3 & PEQ2 & PEQ1 & PEQ0 & ~GBAR) } * UALS518DLY PINDLY (1,0,17) DPWR DGND + PEQ + GBAR P7 P6 P5 P4 P3 P2 P1 P0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 + PEQ_O + IO_ALS00_OC MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + + PINDLY: + PEQ_O = { + CASE( + TRN_HL, DELAY(3NS,-1,15NS), + TRN_LH, DELAY(15NS,-1,33NS), + DELAY(16NS,-1,34NS) + ) + } * .ENDS * *$ *------------------------------------------------------------------------- * 74ALS519 8-BIT IDENTITY COMPARATORS WITH OPEN-COLLECTOR OUTPUTS * * ALS/AS LOGIC CIRCUITS DATA BOOK, 1986, TI * NH 8/21/92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74ALS519 P7_I P6_I P5_I P4_I P3_I P2_I P1_I P0_I Q7_I Q6_I Q5_I Q4_I + Q3_I Q2_I Q1_I Q0_I GBAR_I PEQ_O + OPTIONAL: DPWR = $G_DPWR DGND = $G_DGND + PARAMS: MNTYMXDLY = 0 IO_LEVEL = 0 * UALS519LOG LOGICEXP(17,18) DPWR DGND + P7_I P6_I P5_I P4_I P3_I P2_I P1_I P0_I + Q7_I Q6_I Q5_I Q4_I Q3_I Q2_I Q1_I Q0_I GBAR_I + P7 P6 P5 P4 P3 P2 P1 P0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 GBAR PEQ + D0_GATE IO_ALS00 IO_LEVEL = {IO_LEVEL} + + LOGIC: + P7 = { P7_I } + P6 = { P6_I } + P5 = { P5_I } + P4 = { P4_I } + P3 = { P3_I } + P2 = { P2_I } + P1 = { P1_I } + P0 = { P0_I } + Q7 = { Q7_I } + Q6 = { Q6_I } + Q5 = { Q5_I } + Q4 = { Q4_I } + Q3 = { Q3_I } + Q2 = { Q2_I } + Q1 = { Q1_I } + Q0 = { Q0_I } + GBAR = { GBAR_I } + + PEQ7 = { ~(~P7 ^ ~Q7) } + PEQ6 = { ~(~P6 ^ ~Q6) } + PEQ5 = { ~(~P5 ^ ~Q5) } + PEQ4 = { ~(~P4 ^ ~Q4) } + PEQ3 = { ~(~P3 ^ ~Q3) } + PEQ2 = { ~(~P2 ^ ~Q2) } + PEQ1 = { ~(~P1 ^ ~Q1) } + PEQ0 = { ~(~P0 ^ ~Q0) } + + PEQ = { (PEQ7 & PEQ6 & PEQ5 & PEQ4 & PEQ3 & PEQ2 & PEQ1 & PEQ0 & ~GBAR) } * UALS519DLY PINDLY (1,0,17) DPWR DGND + PEQ + GBAR P7 P6 P5 P4 P3 P2 P1 P0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 + PEQ_O + IO_ALS00_OC MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + + PINDLY: + PEQ_O = { + CASE( + TRN_HL, DELAY(3NS,-1,15NS), + TRN_LH, DELAY(15NS,-1,33NS), + DELAY(16NS,-1,34NS) + ) + } * .ENDS * *$ *--------- * 74ALS520 8-BIT IDENTITY COMPARATORS * * ALS/AS LOGIC CIRCUITS DATA BOOK, 1986, TI * NH 8/24/92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74ALS520 P7_I P6_I P5_I P4_I P3_I P2_I P1_I P0_I Q7_I Q6_I Q5_I Q4_I + Q3_I Q2_I Q1_I Q0_I GBAR_I PEQBAR_O + OPTIONAL: DPWR = $G_DPWR DGND = $G_DGND + PARAMS: MNTYMXDLY = 0 IO_LEVEL = 0 * UALS520LOG LOGICEXP(17,18) DPWR DGND + P7_I P6_I P5_I P4_I P3_I P2_I P1_I P0_I + Q7_I Q6_I Q5_I Q4_I Q3_I Q2_I Q1_I Q0_I GBAR_I + P7 P6 P5 P4 P3 P2 P1 P0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 GBAR PEQBAR + D0_GATE IO_ALS00 IO_LEVEL = {IO_LEVEL} + + LOGIC: + P7 = { P7_I } + P6 = { P6_I } + P5 = { P5_I } + P4 = { P4_I } + P3 = { P3_I } + P2 = { P2_I } + P1 = { P1_I } + P0 = { P0_I } + Q7 = { Q7_I } + Q6 = { Q6_I } + Q5 = { Q5_I } + Q4 = { Q4_I } + Q3 = { Q3_I } + Q2 = { Q2_I } + Q1 = { Q1_I } + Q0 = { Q0_I } + GBAR = { GBAR_I } + + PEQ7 = { ~(~P7 ^ ~Q7) } + PEQ6 = { ~(~P6 ^ ~Q6) } + PEQ5 = { ~(~P5 ^ ~Q5) } + PEQ4 = { ~(~P4 ^ ~Q4) } + PEQ3 = { ~(~P3 ^ ~Q3) } + PEQ2 = { ~(~P2 ^ ~Q2) } + PEQ1 = { ~(~P1 ^ ~Q1) } + PEQ0 = { ~(~P0 ^ ~Q0) } + + PEQBAR = { ~(PEQ7 & PEQ6 & PEQ5 & PEQ4 & PEQ3 & PEQ2 & PEQ1 & PEQ0 & ~GBAR) } * UALS520DLY PINDLY (1,0,17) DPWR DGND + PEQBAR + GBAR P7 P6 P5 P4 P3 P2 P1 P0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 + PEQBAR_O + IO_ALS00 MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + + BOOLEAN: + ANY_CH_P = { CHANGED(P7,0) | CHANGED(P6,0) | CHANGED(P5,0) | CHANGED(P4,0) | + CHANGED(P3,0) | CHANGED(P2,0) | CHANGED(P1,0) | CHANGED(P0,0) } + ANY_CH_Q = { CHANGED(Q7,0) | CHANGED(Q6,0) | CHANGED(Q5,0) | CHANGED(Q4,0) | + CHANGED(Q3,0) | CHANGED(Q2,0) | CHANGED(Q1,0) | CHANGED(Q0,0) } + ENABLE = { GBAR!='1 } + + PINDLY: + PEQBAR_O = { + CASE( + CHANGED(GBAR,0) & TRN_LH, DELAY(2NS,-1,12NS), + CHANGED(GBAR,0) & TRN_HL, DELAY(5NS,-1,22NS), + (ANY_CH_P | ANY_CH_Q) & ENABLE & TRN_LH, DELAY(3NS,-1,12NS), + (ANY_CH_P | ANY_CH_Q) & ENABLE & TRN_HL, DELAY(5NS,-1,20NS), + DELAY(6NS,-1,23NS) + ) + } * .ENDS * *$ *--------- * 74ALS521 8-BIT IDENTITY COMPARATORS * * ALS/AS LOGIC CIRCUITS DATA BOOK, 1986, TI * NH 8/24/92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74ALS521 P7_I P6_I P5_I P4_I P3_I P2_I P1_I P0_I Q7_I Q6_I Q5_I Q4_I + Q3_I Q2_I Q1_I Q0_I GBAR_I PEQBAR_O + OPTIONAL: DPWR = $G_DPWR DGND = $G_DGND + PARAMS: MNTYMXDLY = 0 IO_LEVEL = 0 * UALS521LOG LOGICEXP(17,18) DPWR DGND + P7_I P6_I P5_I P4_I P3_I P2_I P1_I P0_I + Q7_I Q6_I Q5_I Q4_I Q3_I Q2_I Q1_I Q0_I GBAR_I + P7 P6 P5 P4 P3 P2 P1 P0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 GBAR PEQBAR + D0_GATE IO_ALS00 IO_LEVEL = {IO_LEVEL} + + LOGIC: + P7 = { P7_I } + P6 = { P6_I } + P5 = { P5_I } + P4 = { P4_I } + P3 = { P3_I } + P2 = { P2_I } + P1 = { P1_I } + P0 = { P0_I } + Q7 = { Q7_I } + Q6 = { Q6_I } + Q5 = { Q5_I } + Q4 = { Q4_I } + Q3 = { Q3_I } + Q2 = { Q2_I } + Q1 = { Q1_I } + Q0 = { Q0_I } + GBAR = { GBAR_I } + + PEQ7 = { ~(~P7 ^ ~Q7) } + PEQ6 = { ~(~P6 ^ ~Q6) } + PEQ5 = { ~(~P5 ^ ~Q5) } + PEQ4 = { ~(~P4 ^ ~Q4) } + PEQ3 = { ~(~P3 ^ ~Q3) } + PEQ2 = { ~(~P2 ^ ~Q2) } + PEQ1 = { ~(~P1 ^ ~Q1) } + PEQ0 = { ~(~P0 ^ ~Q0) } + + PEQBAR = { ~(PEQ7 & PEQ6 & PEQ5 & PEQ4 & PEQ3 & PEQ2 & PEQ1 & PEQ0 & ~GBAR) } * UALS521DLY PINDLY (1,0,17) DPWR DGND + PEQBAR + GBAR P7 P6 P5 P4 P3 P2 P1 P0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 + PEQBAR_O + IO_ALS00 MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + + BOOLEAN: + ANY_CH_P = { CHANGED(P7,0) | CHANGED(P6,0) | CHANGED(P5,0) | CHANGED(P4,0) | + CHANGED(P3,0) | CHANGED(P2,0) | CHANGED(P1,0) | CHANGED(P0,0) } + ANY_CH_Q = { CHANGED(Q7,0) | CHANGED(Q6,0) | CHANGED(Q5,0) | CHANGED(Q4,0) | + CHANGED(Q3,0) | CHANGED(Q2,0) | CHANGED(Q1,0) | CHANGED(Q0,0) } + ENABLE = { GBAR!='1 } + + PINDLY: + PEQBAR_O = { + CASE( + CHANGED(GBAR,0) & TRN_LH, DELAY(2NS,-1,12NS), + CHANGED(GBAR,0) & TRN_HL, DELAY(5NS,-1,22NS), + (ANY_CH_P | ANY_CH_Q) & ENABLE & TRN_LH, DELAY(3NS,-1,12NS), + (ANY_CH_P | ANY_CH_Q) & ENABLE & TRN_HL, DELAY(5NS,-1,20NS), + DELAY(6NS,-1,23NS) + ) + } * .ENDS * *$ *------------------------------------------------------------------------- * 74ALS522 8-BIT IDENTITY COMPARATORS WITH OPEN-COLLECTOR OUTPUTS * * ALS/AS LOGIC CIRCUITS DATA BOOK, 1986, TI * NH 8/24/92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74ALS522 P7_I P6_I P5_I P4_I P3_I P2_I P1_I P0_I Q7_I Q6_I Q5_I Q4_I + Q3_I Q2_I Q1_I Q0_I GBAR_I PEQBAR_O + OPTIONAL: DPWR = $G_DPWR DGND = $G_DGND + PARAMS: MNTYMXDLY = 0 IO_LEVEL = 0 * UALS522LOG LOGICEXP(17,18) DPWR DGND + P7_I P6_I P5_I P4_I P3_I P2_I P1_I P0_I + Q7_I Q6_I Q5_I Q4_I Q3_I Q2_I Q1_I Q0_I GBAR_I + P7 P6 P5 P4 P3 P2 P1 P0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 GBAR PEQBAR + D0_GATE IO_ALS00 IO_LEVEL = {IO_LEVEL} + + LOGIC: + P7 = { P7_I } + P6 = { P6_I } + P5 = { P5_I } + P4 = { P4_I } + P3 = { P3_I } + P2 = { P2_I } + P1 = { P1_I } + P0 = { P0_I } + Q7 = { Q7_I } + Q6 = { Q6_I } + Q5 = { Q5_I } + Q4 = { Q4_I } + Q3 = { Q3_I } + Q2 = { Q2_I } + Q1 = { Q1_I } + Q0 = { Q0_I } + GBAR = { GBAR_I } + + PEQ7 = { ~(~P7 ^ ~Q7) } + PEQ6 = { ~(~P6 ^ ~Q6) } + PEQ5 = { ~(~P5 ^ ~Q5) } + PEQ4 = { ~(~P4 ^ ~Q4) } + PEQ3 = { ~(~P3 ^ ~Q3) } + PEQ2 = { ~(~P2 ^ ~Q2) } + PEQ1 = { ~(~P1 ^ ~Q1) } + PEQ0 = { ~(~P0 ^ ~Q0) } + + PEQBAR = { ~(PEQ7 & PEQ6 & PEQ5 & PEQ4 & PEQ3 & PEQ2 & PEQ1 & PEQ0 & ~GBAR) } * UALS522DLY PINDLY (1,0,17) DPWR DGND + PEQBAR + GBAR P7 P6 P5 P4 P3 P2 P1 P0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 + PEQBAR_O + IO_ALS00_OC MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + + BOOLEAN: + ANY_CH_P = { CHANGED(P7,0) | CHANGED(P6,0) | CHANGED(P5,0) | CHANGED(P4,0) | + CHANGED(P3,0) | CHANGED(P2,0) | CHANGED(P1,0) | CHANGED(P0,0) } + ANY_CH_Q = { CHANGED(Q7,0) | CHANGED(Q6,0) | CHANGED(Q5,0) | CHANGED(Q4,0) | + CHANGED(Q3,0) | CHANGED(Q2,0) | CHANGED(Q1,0) | CHANGED(Q0,0) } + ENABLE = { GBAR!='1 } + + PINDLY: + PEQBAR_O = { + CASE( + CHANGED(GBAR,0) & TRN_HL, DELAY(8NS,-1,23NS), + CHANGED(GBAR,0) & TRN_LH, DELAY(8NS,-1,25NS), + (ANY_CH_P | ANY_CH_Q) & ENABLE & TRN_HL, DELAY(5NS,-1,23NS), + (ANY_CH_P | ANY_CH_Q) & ENABLE & TRN_LH, DELAY(10NS,-1,25NS), + DELAY(11NS,-1,26NS) + ) + } * .ENDS * *$ *---------- * 74ALS533 Octal D-TYPE Transparent Latches with 3-STATE Outputs * * The ALS/AS Data Book, 1986, TI * atl 7/19/89 Update interface and model names * .subckt 74ALS533 OCBAR C 1D 2D 3D 4D 5D 6D 7D 8D 1QBAR 2QBAR 3QBAR 4QBAR 5QBAR + 6QBAR 7QBAR 8QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U0 inv DPWR DGND + OCBAR OC + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} U1 dltch(8) DPWR DGND + $D_HI $D_HI C + 1D 2D 3D 4D 5D 6D 7D 8D + 1QI 2QI 3QI 4QI 5QI 6QI 7QI 8QI + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D_ALS533_1 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 inv3a(8) DPWR DGND + 1QI 2QI 3QI 4QI 5QI 6QI 7QI 8QI + OC + 1QBAR 2QBAR 3QBAR 4QBAR 5QBAR 6QBAR 7QBAR 8QBAR + D_ALS533_2 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS533_1 ugff ( + tpgqlhmn=0ns tpgqlhmx=5ns + tpgqhlmn=1ns tpgqhlmx=4ns + twghmn=15ns tsudgmn=15ns + thdgmn=7ns + ) .model D_ALS533_2 utgate ( + tplhmn=4ns tplhmx=19ns + tphlmn=4ns tphlmx=13ns + tpzhmn=4ns tpzhmx=17ns + tpzlmn=4ns tpzlmx=18ns + tphzmn=2ns tphzmx=10ns + tplzmn=3ns tplzmx=16ns + ) *$ *---------- * 74ALS534 Octal D-TYPE Edge-Triggered Flip-Flops with 3-STATE Outputs * * The ALS/AS Data Book, 1986, TI * atl 7/19/89 Update interface and model names * .subckt 74ALS534 OCBAR CLK 1D 2D 3D 4D 5D 6D 7D 8D 1QBAR 2QBAR 3QBAR 4QBAR + 5QBAR 6QBAR 7QBAR 8QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UOC inv DPWR DGND + OCBAR OC + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} UDFF dff(8) DPWR DGND + $D_HI $D_HI CLK + 1D 2D 3D 4D 5D 6D 7D 8D + 1QQ 2QQ 3QQ 4QQ 5QQ 6QQ 7QQ 8QQ + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D_ALS534_1 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UOCQ inv3a(8) DPWR DGND + 1QQ 2QQ 3QQ 4QQ 5QQ 6QQ 7QQ 8QQ + OC + 1QBAR 2QBAR 3QBAR 4QBAR 5QBAR 6QBAR 7QBAR 8QBAR + D_ALS534_2 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS534_1 ueff ( + twclklmn=14ns twclkhmn=14ns + tsudclkmn=10ns + ) .model D_ALS534_2 utgate ( + tplhmn=3ns tplhmx=12ns + tphlmn=5ns tphlmx=16ns + tpzhmn=5ns tpzhmx=17ns + tpzlmn=7ns tpzlmx=18ns + tphzmn=2ns tphzmx=10ns + tplzmn=2ns tplzmx=14ns + ) *$ *---------- * 74ALS540 Octal Buffers and Line Drivers with 3-STATE Outputs * * The ALS/AS Data Book, 1986, TI * atl 7/19/89 Update interface and model names * .subckt 74ALS540 A1 A2 A3 A4 A5 A6 A7 A8 G1BAR G2BAR Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UA nor(2) DPWR DGND + G1BAR G2BAR E + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} U1 inv3a(8) DPWR DGND + A1 A2 A3 A4 A5 A6 A7 A8 + E + Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 + D_ALS540 IO_ALS00_ST MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS540 utgate ( + tplhmn=2ns tplhmx=12ns + tphlmn=2ns tphlmx=9ns + tpzhmn=5ns tpzhmx=15ns + tpzlmn=8ns tpzlmx=20ns + tphzmn=1ns tphzmx=10ns + tplzmn=2ns tplzmx=12ns + ) *$ *---------- * 74ALS541 Octal Buffers and Line Driver with 3-STATE Outputs * * The ALS/AS Data Book, 1986, TI * atl 7/19/89 Update interface and model names * .subckt 74ALS541 A1 A2 A3 A4 A5 A6 A7 A8 G1BAR G2BAR Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UA nor(2) DPWR DGND + G1BAR G2BAR E + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} U1 buf3a(8) DPWR DGND + A1 A2 A3 A4 A5 A6 A7 A8 + E + Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 + D_ALS541 IO_ALS00_ST MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS541 utgate ( + tplhmn=4ns tplhmx=14ns + tphlmn=2ns tphlmx=10ns + tpzhmn=5ns tpzhmx=15ns + tpzlmn=8ns tpzlmx=20ns + tphzmn=1ns tphzmx=10ns + tplzmn=2ns tplzmx=12ns + ) *$ *------------------------------------------------------------------------- * 74ALS560A Synchronous 4-bit Decade Counters with 3-STATE Outputs * * The ALS/AS Data Book, 1986, TI * JSW 6/26/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74ALS560A CLK_I GBAR_I ENP_I ENT_I ALOADBAR_I ACLRBAR_I SLOADBAR_I + SCLRBAR_I A_I B_I C_I D_I + QA_O QB_O QC_O QD_O CCO_O RCO_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UALS560ALOG LOGICEXP(20,31) DPWR DGND + CLK_I GBAR_I ENP_I ENT_I ALOADBAR_I ACLRBAR_I SLOADBAR_I SCLRBAR_I A_I B_I + C_I D_I IQA IQB IQC IQD LQABAR LQBBAR LQCBAR LQDBAR + CLK GBAR ENP ENT ALOADBAR ACLRBAR SLOADBAR SCLRBAR A B C D + LCCO LRCO SA RA DA SB RB DB SC RC DC SD RD DD LQA LQB LQC LQD IEN + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} + LOGIC: + CLK = { CLK_I } + GBAR = { GBAR_I } + ENP = { ENP_I } + ENT = { ENT_I } + ALOADBAR = { ALOADBAR_I } + ACLRBAR = { ACLRBAR_I } + SLOADBAR = { SLOADBAR_I } + SCLRBAR = { SCLRBAR_I } + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + LQA = { ~LQABAR } + LQB = { ~LQBBAR } + LQC = { ~LQCBAR } + LQD ={ ~LQDBAR } + LRCO = { ENT & IQD & IQA } + LCCO = { (ENT & ENP) & ~CLK & LRCO } + ACLR = { ~ACLRBAR } + ALOAD = { ~ALOADBAR } + IEN = { ENT & ENP & SLOADBAR & SCLRBAR } + ISC = { SLOADBAR & SCLRBAR } + ISL = { ~SLOADBAR & SCLRBAR } + SET = { ALOAD & ACLRBAR } + SA = { ~(A & SET) } + RA = { ~((SA & ALOAD) | ACLR) } + DA = { (A & ISL) | (~IEN & ISC & IQA) | (~(ISC & IQA) + & IEN) } + SB = { ~(B & SET) } + RB = { ~((SB & ALOAD) | ACLR) } + DB = { (B & ISL) | (~(IQA & IEN) & ISC & IQB) | (~(IQB & ISC) & + IEN & LQDBAR & IQA) } + SC = { ~(C & SET) } + RC = { ~((SC & ALOAD) | ACLR) } + DC = { (C & ISL) | (~(IEN & IQB & IQA) & IQC & ISC) | + (~(ISC & IQC) & IQA & IQB & IEN) } + SD = { ~(D & SET) } + RD = { ~((SD & ALOAD) | ACLR) } + DD = { (D & ISL) | (~(IEN & IQA) & IQD & ISC) | (~(ISC & IQD) + & IEN & IQC & IQB & IQA) } * UDFFA DFF(1) DPWR DGND SA RA CLK DA IQA LQABAR D0_EFF IO_ALS00 UDFFB DFF(1) DPWR DGND SB RB CLK DB IQB LQBBAR D0_EFF IO_ALS00 UDFFC DFF(1) DPWR DGND SC RC CLK DC IQC LQCBAR D0_EFF IO_ALS00 UDFFD DFF(1) DPWR DGND SD RD CLK DD IQD LQDBAR D0_EFF IO_ALS00 * UALS560ADLY PINDLY (6,1,13) DPWR DGND + LCCO LRCO LQA LQB LQC LQD + GBAR + CLK GBAR ENP ENT ALOADBAR ACLRBAR A B C D SLOADBAR SCLRBAR IEN + CCO_O RCO_O QA_O QB_O QC_O QD_O + IO_ALS00 + MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + BOOLEAN: + DATA = { CHANGED(A,0) | CHANGED(B,0) | CHANGED(C,0) | CHANGED(D,0) + & ALOADBAR!='0 } + CLOCK = { CHANGED_LH(CLK,0) } + ALOAD = { CHANGED_HL(ALOADBAR,0) } + ACLEAR = { CHANGED_HL(ACLRBAR,0) } + CNTENT = { CHANGED(ENT,0) } + CNTENP = { CHANGED(ENP,0) } + ENABLE = { CHANGED_HL(GBAR,0) } + DISABLE = { CHANGED_LH(GBAR,0) } + PINDLY: + CCO_O = { + CASE( + CNTENT & TRN_HL, DELAY(4NS,-1,12NS), + CNTENP & TRN_HL, DELAY(4NS,-1,12NS), + CHANGED(CLK,0) & TRN_HL, DELAY(5NS,-1,16NS), + CNTENP & TRN_LH, DELAY(5NS,-1,18NS), + CHANGED(CLK,0) & TRN_LH, DELAY(8NS,-1,26NS), + CNTENT & TRN_LH, DELAY(12NS,-1,32NS), + ALOAD & TRN_HL, DELAY(12NS,-1,33NS), + ALOAD & TRN_LH, DELAY(25NS,-1,55NS), + DELAY(25NS,-1,55NS) + ) + } + RCO_O = { + CASE( + CNTENT & TRN_HL, DELAY(4NS,-1,14NS), + CNTENT & TRN_LH, DELAY(5NS,-1,16NS), + CLOCK & TRN_HL, DELAY(8NS,-1,24NS), + CLOCK & TRN_LH, DELAY(9NS,-1,29NS), + ALOAD & TRN_HL, DELAY(12NS,-1,30NS), + ALOAD & TRN_LH, DELAY(15NS,-1,40NS), + DELAY(15NS,-1,40NS) + ) + } + TRISTATE: + ENABLE LO GBAR + QA_O QB_O QC_O QD_O = { + CASE( + DISABLE & TRN_HZ, DELAY(2NS,-1,10NS), + CLOCK & TRN_LH, DELAY(4NS,-1,12NS), + DISABLE & TRN_LZ, DELAY(4NS,-1,15NS), + CLOCK & TRN_HL, DELAY(5NS,-1,18NS), + ENABLE & TRN_ZH, DELAY(5NS,-1,19NS), + DATA & TRN_HL, DELAY(7NS,-1,22NS), + ACLEAR, DELAY(7NS,-1,22NS), + ALOAD & TRN_HL, DELAY(7NS,-1,23NS), + ENABLE & TRN_ZL, DELAY(8NS,-1,23NS), + DATA & TRN_LH, DELAY(8NS,-1,30NS), + ALOAD & TRN_LH, DELAY(10NS,-1,35NS), + DELAY(10NS,-1,35NS) + ) + } + FREQ: + NODE = CLK + MAXFREQ = 20MEG + WIDTH: + NODE = ACLRBAR + MIN_LO = 15NS + WIDTH: + NODE = ALOADBAR + MIN_LO = 15NS + WHEN = { ACLRBAR!='0 } + WIDTH: + NODE = CLK + MIN_LO = 25NS + MIN_HI = 25NS + SETUP_HOLD: + DATA(4) = A B C D + CLOCK LH = CLK + SETUPTIME = 20NS + WHEN = { (SLOADBAR!='1 ^ CHANGED(SLOADBAR,0)) & ACLRBAR!='0 + & (SCLRBAR!='0 ^ CHANGED(SCLRBAR,0)) } + SETUP_HOLD: + DATA(2) = ENP ENT + CLOCK LH = CLK + SETUPTIME = 20NS + WHEN = { CHANGED(IEN,20NS) & ALOADBAR!='0 & ACLRBAR!='0 + & (SLOADBAR!='0 ^ CHANGED(SLOADBAR,0)) + & (SCLRBAR!='0 ^ CHANGED(SCLRBAR,0)) } + SETUP_HOLD: + DATA(1) = SCLRBAR + CLOCK LH = CLK + SETUPTIME_LO = 15NS + SETUPTIME_HI = 30NS + WHEN = { ACLRBAR!='0 & ALOADBAR!='0 } + SETUP_HOLD: + DATA(1) = SLOADBAR + CLOCK LH = CLK + SETUPTIME_LO = 15NS + SETUPTIME_HI = 30NS + WHEN = { ACLRBAR!='0 & ALOADBAR!='0 & (SCLRBAR!='0 ^ CHANGED(SCLRBAR,0)) } + SETUP_HOLD: + DATA(1) = ACLRBAR + CLOCK LH = CLK + RELEASETIME_LH = 10NS + SETUP_HOLD: + DATA(1) = ALOADBAR + CLOCK LH = CLK + RELEASETIME_LH = 10NS + WHEN = { ACLRBAR!='0 } * .ENDS * *$ *------------------------------------------------------------------------- * 74ALS561A Synchronous 4-Bit Binary Counter With 3-State Outputs * * THE ALS/AS DATA BOOK, 1986, TI * tc 06/25/92 Remodeled using LOGICEXP, PINDLY & CONSTRAINT Devices * .SUBCKT 74ALS561A CLK_I GBAR_I ENP_I ENT_I ALOADBAR_I ACLRBAR_I SLOADBAR_I + SCLRBAR_I A_I B_I C_I D_I QA_O QB_O QC_O QD_O CCO_O RCO_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 DFF(1) DPWR DGND SA RA CLK DA QA $D_NC + D0_EFF IO_ALS00 U2 DFF(1) DPWR DGND SB RB CLK DB QB $D_NC + D0_EFF IO_ALS00 U3 DFF(1) DPWR DGND SC RC CLK DC QC $D_NC + D0_EFF IO_ALS00 U4 DFF(1) DPWR DGND SD RD CLK DD QD $D_NC + D0_EFF IO_ALS00 * UALS561ALOG LOGICEXP(16,27) DPWR DGND + CLK_I GBAR_I ENP_I ENT_I ALOADBAR_I ACLRBAR_I SLOADBAR_I SCLRBAR_I + A_I B_I C_I D_I QA QB QC QD + CCO RCO RA RB RC RD SA SB SC SD DA DB DC DD CLK GBAR ENP ENT ALOADBAR + ACLRBAR SLOADBAR SCLRBAR A B C D IEN + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} + LOGIC: + CLK = { CLK_I } + GBAR = { GBAR_I } + ENP = { ENP_I } + ENT = { ENT_I } + ALOADBAR = { ALOADBAR_I } + ACLRBAR = { ACLRBAR_I } + SLOADBAR = { SLOADBAR_I } + SCLRBAR = { SCLRBAR_I } + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + ICLK = { ~CLK } + IEN = { (ENT & ENP & SLOADBAR) & SCLRBAR } + ISC = { SLOADBAR & SCLRBAR } + ISL = { ~SLOADBAR & SCLRBAR } + IACLRBAR = { ~ACLRBAR } + IALOADBAR = { ~ALOADBAR } + IA1 = { A & ISL } + IA2 = { ISC & QA & ~IEN } + IA3 = { IEN & ~(ISC & QA) } + IB1 = { B & ISL } + IB2 = { ~(IEN & QA) & QB & ISC } + IB3 = { IEN & QA & ~(ISC & QB) } + IC1 = { C & ISL } + IC2 = { ~(IEN & QB & QA) & QC & ISC } + IC3 = { IEN & QB & QA & ~(ISC & QC) } + ID1 = { D & ISL } + ID2 = { ~(IEN & QC & QB & QA) & QD & ISC } + ID3 = { IEN & QC & QB & QA & ~(QD & ISC) } + RCO = { ENT & QD & QC & QB & QA } + CCO = { (ENT & ENP) & ICLK & RCO } + SA = { ~(A & IALOADBAR & ACLRBAR) } + RA = { ~(IACLRBAR | (IALOADBAR & SA)) } + DA = { IA1 | IA2 | IA3 } + SB = { ~(B & IALOADBAR & ACLRBAR) } + RB = { ~(IACLRBAR | (IALOADBAR & SB)) } + DB = { IB1 | IB2 | IB3 } + SC = { ~(C & IALOADBAR & ACLRBAR) } + RC = { ~(IACLRBAR | (IALOADBAR & SC)) } + DC = { IC1 | IC2 | IC3 } + SD = { ~(D & IALOADBAR & ACLRBAR) } + RD = { ~(IACLRBAR | (IALOADBAR & SD)) } + DD = { ID1 | ID2 | ID3 } * UALS561ADLY PINDLY (6,1,13) DPWR DGND + CCO RCO QA QB QC QD + GBAR + CLK ALOADBAR ACLRBAR ENT ENP GBAR A B C D SLOADBAR SCLRBAR IEN + CCO_O RCO_O QA_O QB_O QC_O QD_O + IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + DATA = { (CHANGED(A,0) | CHANGED(B,0) | CHANGED(C,0) | CHANGED(D,0)) + & ALOADBAR!='1 } + CLOCK = { CHANGED_LH(CLK,0) } + ALOAD = { CHANGED_HL(ALOADBAR,0) } + ACLEAR = { CHANGED_HL(ACLRBAR,0) } + CNTENT = { CHANGED(ENT,0) } + CNTENP = { CHANGED(ENP,0) } + ENABLE = { CHANGED_HL(GBAR,0) } + DISABLE = { CHANGED_LH(GBAR,0) } + PINDLY: + CCO_O = { + CASE( + CNTENT & TRN_HL, DELAY(4NS,-1,12NS), + CNTENP & TRN_HL, DELAY(4NS,-1,12NS), + CHANGED(CLK,0) & TRN_HL, DELAY(5NS,-1,16NS), + CNTENP & TRN_LH, DELAY(5NS,-1,18NS), + CHANGED(CLK,0) & TRN_LH, DELAY(8NS,-1,26NS), + CNTENT & TRN_LH, DELAY(12NS,-1,32NS), + ALOAD & TRN_HL, DELAY(12NS,-1,33NS), + ALOAD & TRN_LH, DELAY(25NS,-1,55NS), + DELAY(25NS,-1,55NS) + ) + } + RCO_O = { + CASE( + CNTENT & TRN_HL, DELAY(4NS,-1,14NS), + CNTENT & TRN_LH, DELAY(5NS,-1,16NS), + CLOCK & TRN_HL, DELAY(8NS,-1,24NS), + CLOCK & TRN_LH, DELAY(9NS,-1,29NS), + ALOAD & TRN_HL, DELAY(12NS,-1,30NS), + ALOAD & TRN_LH, DELAY(15NS,-1,40NS), + DELAY(15NS,-1,40NS) + ) + } + TRISTATE: + ENABLE LO GBAR + QA_O QB_O QC_O QD_O = { + CASE( + DISABLE & TRN_HZ, DELAY(2NS,-1,10NS), + CLOCK & TRN_LH, DELAY(4NS,-1,12NS), + DISABLE & TRN_LZ, DELAY(4NS,-1,15NS), + CLOCK & TRN_HL, DELAY(5NS,-1,18NS), + ENABLE & TRN_ZH, DELAY(5NS,-1,19NS), + ACLEAR, DELAY(7NS,-1,22NS), + DATA & TRN_HL, DELAY(7NS,-1,22NS), + ALOAD & TRN_HL, DELAY(7NS,-1,23NS), + ENABLE & TRN_ZL, DELAY(8NS,-1,23NS), + DATA & TRN_LH, DELAY(8NS,-1,30NS), + ALOAD & TRN_LH, DELAY(10NS,-1,35NS), + DELAY(10NS,-1,35NS) + ) + } + FREQ: + NODE = CLK + MAXFREQ = 30MEG + WIDTH: + NODE = ACLRBAR + MIN_LO = 15NS + WIDTH: + NODE = ALOADBAR + MIN_LO = 15NS + WHEN = { ACLRBAR!='0 } + WIDTH: + NODE = CLK + MIN_LO = 16.5NS + MIN_HI = 16.5NS + SETUP_HOLD: + DATA(4) = A B C D + CLOCK LH = CLK + SETUPTIME = 20NS + WHEN = { (SLOADBAR!='1 ^ CHANGED(SLOADBAR,0)) & ACLRBAR!='0 + & (SCLRBAR!='0 ^ CHANGED(SCLRBAR,0)) } + SETUP_HOLD: + DATA(2) = ENP ENT + CLOCK LH = CLK + SETUPTIME = 20NS + WHEN = { CHANGED(IEN,20NS) & ALOADBAR!='0 & ACLRBAR!='0 + & (SLOADBAR!='0 ^ CHANGED(SLOADBAR,0)) + & (SCLRBAR!='0 ^ CHANGED(SCLRBAR,0)) } + SETUP_HOLD: + DATA(1) = SCLRBAR + CLOCK LH = CLK + SETUPTIME_LO = 15NS + SETUPTIME_HI = 30NS + WHEN = { ACLRBAR!='0 & ALOADBAR!='0 } + SETUP_HOLD: + DATA(1) = SLOADBAR + CLOCK LH = CLK + SETUPTIME_LO = 15NS + SETUPTIME_HI = 30NS + WHEN = { ACLRBAR!='0 & ALOADBAR!='0 & (SCLRBAR!='0 ^ CHANGED(SCLRBAR,0)) } + SETUP_HOLD: + DATA(1) = ACLRBAR + CLOCK LH = CLK + RELEASETIME_LH = 10NS + SETUP_HOLD: + DATA(1) = ALOADBAR + CLOCK LH = CLK + RELEASETIME_LH = 10NS + WHEN = { ACLRBAR!='0 } * .ENDS * *$ *----------- * 74ALS563A Octal D-TYPE Transparent Latches with 3-STATE Outputs * * The ALS/AS Data Book, 1986, TI * atl 8/16/89 Update interface and model names * .subckt 74ALS563A OCBAR C 1D 2D 3D 4D 5D 6D 7D 8D 1QBAR 2QBAR 3QBAR 4QBAR 5QBAR + 6QBAR 7QBAR 8QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UINV inv DPWR DGND + OCBAR OC + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} UQBUF dltch(8) DPWR DGND + $D_HI $D_HI C + 1D 2D 3D 4D 5D 6D 7D 8D + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + 1QB 2QB 3QB 4QB 5QB 6QB 7QB 8QB + D_ALS563A_1 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UQOUT buf3a(8) DPWR DGND + 1QB 2QB 3QB 4QB 5QB 6QB 7QB 8QB + OC + 1QBAR 2QBAR 3QBAR 4QBAR 5QBAR 6QBAR 7QBAR 8QBAR + D_ALS563A_2 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS563A_1 ugff ( + twghmn=15ns tsudgmn=10ns + thdgmn=10ns tpgqlhmn=5ns + tpgqlhmx=4ns tpgqhlmn=5ns + tpgqhlmx=7ns + ) .model D_ALS563A_2 utgate ( + tplhmn=3ns tplhmx=18ns + tphlmn=3ns tphlmx=14ns + tpzhmn=4ns tpzhmx=18ns + tpzlmn=4ns tpzlmx=18ns + tphzmn=2ns tphzmx=10ns + tplzmn=3ns tplzmx=15ns + ) *$ *----------- * 74ALS564A Octal D-TYPE Edge-Triggered Flip-Flops with 3-STATE Outputs * * The ALS/AS Data Book, 1986, TI * atl 7/19/89 Update interface and model names * .subckt 74ALS564A OCBAR CLK 1D 2D 3D 4D 5D 6D 7D 8D 1QBAR 2QBAR 3QBAR 4QBAR + 5QBAR 6QBAR 7QBAR 8QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UOC inv DPWR DGND + OCBAR OC + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} UDFF dff(8) DPWR DGND + $D_HI $D_HI CLK + 1D 2D 3D 4D 5D 6D 7D 8D + 1QQ 2QQ 3QQ 4QQ 5QQ 6QQ 7QQ 8QQ + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D_ALS564A_1 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UOCQ inv3a(8) DPWR DGND + 1QQ 2QQ 3QQ 4QQ 5QQ 6QQ 7QQ 8QQ + OC + 1QBAR 2QBAR 3QBAR 4QBAR 5QBAR 6QBAR 7QBAR 8QBAR + D_ALS564A_2 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS564A_1 ueff ( + twclklmn=14ns + twclkhmn=14ns + tsudclkmn=15ns + ) .model D_ALS564A_2 utgate ( + tplhmn=4ns tplhmx=14ns + tphlmn=4ns tphlmx=14ns + tpzhmn=4ns tpzhmx=18ns + tpzlmn=4ns tpzlmx=18ns + tphzmn=2ns tphzmx=10ns + tplzmn=3ns tplzmx=15ns + ) *$ *------------------------------------------------------------------------- * 74ALS568A Synchronous 4-bit Up/Down Decade Counters with 3-STATE Outputs * * The ALS/AS Data Book, 1986, TI * JSW 7/22/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * NOTICE: Since a propogation delay from D/UBAR to CCO was not specified * for the ALS device, the value for D/UBAR to RCO was used. * .SUBCKT 74ALS568A CLK_I GBAR_I U/DBAR_I ENPBAR_I ENTBAR_I LOADBAR_I + ACLRBAR_I SCLRBAR_I A_I B_I C_I D_I + QA_O QB_O QC_O QD_O CCOBAR_O RCOBAR_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UALS568ALOG LOGICEXP(20,19) DPWR DGND + CLK_I GBAR_I U/DBAR_I ENPBAR_I ENTBAR_I LOADBAR_I ACLRBAR_I SCLRBAR_I + A_I B_I C_I D_I QA QB QC QD QABAR QBBAR QCBAR QDBAR + CLK GBAR U/DBAR ENPBAR ENTBAR LOADBAR ACLRBAR SCLRBAR A B C D + CCOBAR RCOBAR DA DB DC DD EN + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} + LOGIC: + CLK = { CLK_I } + GBAR = { GBAR_I } + ENPBAR = { ENPBAR_I } + ENTBAR = { ENTBAR_I } + U/DBAR = { U/DBAR_I } + LOADBAR = { LOADBAR_I } + ACLRBAR = { ACLRBAR_I } + SCLRBAR = { SCLRBAR_I } + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + UD = { ~U/DBAR } + SCLR = { SCLRBAR & LOADBAR } + LOAD = { ~LOADBAR & SCLRBAR } + EN = { ~ENTBAR & ~ENPBAR & ~LOAD & SCLRBAR } + IA4 = { ~((QABAR & U/DBAR) | (QA & UD)) } + IB4 = { ~((QBBAR & U/DBAR) | (QB & UD)) } + IC4 = { ~((QCBAR & U/DBAR) | (QC & UD)) } + ID4 = { ~((QDBAR & U/DBAR) | (QD & UD)) } + IB5 = { ~(U/DBAR & ID4) } + IC5 = { ~(QCBAR & UD & QDBAR) } + IA1 = { A & LOAD } + IA2 = { SCLR & ~EN & QA } + IA3 = { ~(SCLR & QA) & EN } + IB1 = { B & LOAD } + IB2 = { ~(EN & IA4) & SCLR & QB } + IB3 = { IA4 & EN & IC5 & IB5 & QBBAR } + IC1 = { C & LOAD } + IC2 = { ~(EN & IA4 & IB4) & SCLR & QC } + IC3 = { ~(QC & SCLR) & EN & IA4 & IB4 & IC5 } + ID1 = { D & LOAD } + ID2 = { ~(EN & IA4) & SCLR & QD } + ID3 = { ~(QD & SCLR) & EN & IA4 & IB4 & IC4 } + DA = { IA1 | IA2 | IA3 } + DB = { IB1 | IB2 | IB3 } + DC = { IC1 | IC2 | IC3 } + DD = { ID1 | ID2 | ID3 } + RCOBAR = { ~((U/DBAR & IA4 & ID4 & ~ENTBAR) | (~ENTBAR & UD & + IA4 & IB4 & IC4 & ID4)) } + CCOBAR = { ~(~CLK & (~ENTBAR & ~ENPBAR) & ~RCOBAR) } * UDFF DFF(4) DPWR DGND $D_HI ACLRBAR CLK DA DB DC DD QA QB QC QD + QABAR QBBAR QCBAR QDBAR D0_EFF IO_ALS00 * UALS568ADLY PINDLY (6,1,14) DPWR DGND + CCOBAR RCOBAR QA QB QC QD + GBAR + CLK GBAR ENPBAR ENTBAR ACLRBAR U/DBAR U/DBAR LOADBAR SCLRBAR A B C D EN + CCOBAR_O RCOBAR_O QA_O QB_O QC_O QD_O + IO_ALS00 + MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + BOOLEAN: + CLOCK = { CHANGED_LH(CLK,0) } + ACLEAR = { CHANGED_HL(ACLRBAR,0) } + CNTENT = { CHANGED(ENTBAR,0) } + CNTENP = { CHANGED(ENPBAR,0) } + ENABLE = { CHANGED_HL(GBAR,0) } + DISABLE = { CHANGED_LH(GBAR,0) } + PINDLY: + CCOBAR_O = { + CASE( + CNTENP & TRN_LH, DELAY(4NS,-1,12NS), + CHANGED(CLK,0) & TRN_LH, DELAY(5NS,-1,13NS), + CNTENT & TRN_LH, DELAY(5NS,-1,13NS), + CNTENP & TRN_HL, DELAY(5NS,-1,14NS), + CHANGED(U/DBAR,0) & TRN_HL, DELAY(9NS,-1,19NS), + CHANGED(U/DBAR,0) & TRN_LH, DELAY(9NS,-1,23NS), + CNTENT & TRN_HL, DELAY(9NS,-1,23NS), + CHANGED(CLK,0) & TRN_HL, DELAY(6NS,-1,25NS), + DELAY(6NS,-1,25NS) + ) + } + RCOBAR_O = { + CASE( + CNTENT & TRN_HL, DELAY(4NS,-1,13NS), + CNTENT & TRN_LH, DELAY(6NS,-1,15NS), + CHANGED(U/DBAR,0) & TRN_HL, DELAY(9NS,-1,19NS), + CLOCK & TRN_HL, DELAY(10NS,-1,19NS), + CHANGED(U/DBAR,0) & TRN_LH, DELAY(9NS,-1,23NS), + CLOCK & TRN_LH, DELAY(12NS,-1,28NS), + DELAY(12NS,-1,28NS) + ) + } + TRISTATE: + ENABLE LO GBAR + QA_O QB_O QC_O QD_O = { + CASE( + DISABLE & TRN_HZ, DELAY(1NS,-1,10NS), + DISABLE & TRN_LZ, DELAY(3NS,-1,13NS), + CLOCK & TRN_LH, DELAY(4NS,-1,13NS), + CLOCK & TRN_HL, DELAY(7NS,-1,16NS), + ENABLE & TRN_ZH, DELAY(6NS,-1,18NS), + ACLEAR, DELAY(9NS,-1,20NS), + ENABLE & TRN_ZL, DELAY(6NS,-1,24NS), + DELAY(9NS,-1,24NS) + ) + } + BOOLEAN: + SCLEAR = { SCLRBAR!='0 ^ CHANGED(SCLRBAR,0) } + LOAD = { LOADBAR!='0 ^ CHANGED(LOADBAR,0) } + FREQ: + NODE = CLK + MAXFREQ = 20MEG + WIDTH: + NODE = ACLRBAR + MIN_LO = 15NS + WIDTH: + NODE = LOADBAR + MIN_LO = 15NS + WHEN = { ACLRBAR!='0 & SCLEAR} + WIDTH: + NODE = CLK + MIN_LO = 25NS + MIN_HI = 25NS + SETUP_HOLD: + DATA(4) = A B C D + CLOCK LH = CLK + SETUPTIME = 20NS + WHEN = { (LOADBAR!='1 ^ CHANGED(LOADBAR,0)) & ACLRBAR!='0 & SCLEAR } + SETUP_HOLD: + DATA(2) = ENPBAR ENTBAR + CLOCK LH = CLK + SETUPTIME_HI = 30NS + SETUPTIME_LO = 20NS + WHEN = { CHANGED(EN,30NS) & LOAD & ACLRBAR!='0 & SCLEAR } + SETUP_HOLD: + DATA(1) = SCLRBAR + CLOCK LH = CLK + SETUPTIME_LO = 15NS + SETUPTIME_HI = 30NS + WHEN = { ACLRBAR!='0 } + SETUP_HOLD: + DATA(1) = LOADBAR + CLOCK LH = CLK + SETUPTIME_LO = 15NS + SETUPTIME_HI = 30NS + WHEN = { ACLRBAR!='0 & SCLEAR } + SETUP_HOLD: + DATA(1) = ACLRBAR + CLOCK LH = CLK + RELEASETIME_LH = 10NS + SETUP_HOLD: + DATA(1) = U/DBAR + CLOCK LH = CLK + SETUPTIME = 30NS + WHEN = { ACLRBAR!='0 & SCLEAR & LOAD } * * .ENDS * *$ *------------------------------------------------------------------------- * 74ALS569A Synchronous 4-Bit Up/Down Binary Counter w/ 3-state Outputs * * ALS/AS LOGIC CIRCUITS DATA BOOK, 1986, TI * tc 7/30/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * NOTICE: Since a propogation delay from D/UBAR to CCO was not specified * for the ALS device, the value for D/UBAR to RCO was used. * .SUBCKT 74ALS569A CLK_I GBAR_I U/DBAR_I ENPBAR_I ENTBAR_I LOADBAR_I + ACLRBAR_I SCLRBAR_I A_I B_I C_I D_I QA_O QB_O QC_O QD_O CCOBAR_O RCOBAR_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UDFF DFF(4) DPWR DGND $D_HI ACLRBAR CLK DA DB DC DD QA QB QC QD + QABAR QBBAR QCBAR QDBAR D0_EFF IO_ALS00 * UALS569ALOG LOGICEXP(20,19) DPWR DGND + CLK_I GBAR_I U/DBAR_I ENPBAR_I ENTBAR_I LOADBAR_I ACLRBAR_I SCLRBAR_I + A_I B_I C_I D_I QA QB QC QD QABAR QBBAR QCBAR QDBAR + CLK GBAR U/DBAR ENPBAR ENTBAR LOADBAR ACLRBAR SCLRBAR A B C D DA DB DC DD + CCOBAR RCOBAR IEN + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} + LOGIC: + CLK = { CLK_I } + GBAR = { GBAR_I } + ENPBAR = { ENPBAR_I } + ENTBAR = { ENTBAR_I } + U/DBAR = { U/DBAR_I } + LOADBAR = { LOADBAR_I } + ACLRBAR = { ACLRBAR_I } + SCLRBAR = { SCLRBAR_I } + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + UP = { U/DBAR } + DN = { ~U/DBAR } + ILC1 = { SCLRBAR & LOADBAR } + ILC2 = { SCLRBAR & ~LOADBAR } + IEN = { ~(ENTBAR | ENPBAR | ~SCLRBAR | ILC2) } + IUD1 = { ~((QABAR & UP) | (QA & DN)) } + IUD2 = { ~((QBBAR & UP) | (QB & DN)) } + IUD3 = { ~((QCBAR & UP) | (QC & DN)) } + IUD4 = { ~((QDBAR & UP) | (QD & DN)) } + IA1 = { A & ILC2 } + IA2 = { ILC1 & ~IEN & QA } + IA3 = { IEN & ~(QA & ILC1) } + IB1 = { B & ILC2 } + IB2 = { ILC1 & ~(IEN & IUD1) & QB } + IB3 = { IEN & ~(QB & ILC1) & IUD1 } + IC1 = { C & ILC2 } + IC2 = { ILC1 & ~(IEN & IUD1 & IUD2) & QC } + IC3 = { IEN & ~(QC & ILC1) & IUD1 & IUD2 } + ID1 = { D & ILC2 } + ID2 = { ILC1 & ~(IEN & IUD1 & IUD2 & IUD3) & QD } + ID3 = { IEN & ~(QD & ILC1) & IUD1 & IUD2 & IUD3 } + IRC1 = { UP & IUD4 & IUD3 & IUD2 & IUD1 & ~ENTBAR } + IRC2 = { DN & IUD4 & IUD3 & IUD2 & IUD1 & ~ENTBAR } + DA = { IA1 | IA2 | IA3 } + DB = { IB1 | IB2 | IB3 } + DC = { IC1 | IC2 | IC3 } + DD = { ID1 | ID2 | ID3 } + RCOBAR = { ~(IRC1 | IRC2) } + CCOBAR = { ~(~CLK & ~(ENTBAR | ENPBAR) & ~RCOBAR) } * UALS569ADLY PINDLY (6,1,14) DPWR DGND + CCOBAR RCOBAR QA QB QC QD + GBAR + CLK GBAR ENPBAR ENTBAR ACLRBAR U/DBAR U/DBAR LOADBAR SCLRBAR A B C D IEN + CCOBAR_O RCOBAR_O QA_O QB_O QC_O QD_O + IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + CLOCK = { CHANGED_LH(CLK,0) } + ACLEAR = { CHANGED_HL(ACLRBAR,0) } + CNTENT = { CHANGED(ENTBAR,0) } + CNTENP = { CHANGED(ENPBAR,0) } + ENABLE = { CHANGED_HL(GBAR,0) } + DISABLE = { CHANGED_LH(GBAR,0) } + PINDLY: + CCOBAR_O = { + CASE( + CNTENP & TRN_LH, DELAY(4NS,-1,12NS), + CHANGED(CLK,0) & TRN_LH, DELAY(5NS,-1,13NS), + CNTENT & TRN_LH, DELAY(5NS,-1,13NS), + CNTENP & TRN_HL, DELAY(5NS,-1,14NS), + CHANGED(U/DBAR,0) & TRN_HL, DELAY(9NS,-1,19NS), + CHANGED(U/DBAR,0) & TRN_LH, DELAY(9NS,-1,23NS), + CNTENT & TRN_HL, DELAY(9NS,-1,23NS), + CHANGED(CLK,0) & TRN_HL, DELAY(6NS,-1,25NS), + DELAY(6NS,-1,25NS) + ) + } + RCOBAR_O = { + CASE( + CNTENT & TRN_HL, DELAY(4NS,-1,13NS), + CNTENT & TRN_LH, DELAY(6NS,-1,15NS), + CHANGED(U/DBAR,0) & TRN_HL, DELAY(9NS,-1,19NS), + CLOCK & TRN_HL, DELAY(10NS,-1,19NS), + CHANGED(U/DBAR,0) & TRN_LH, DELAY(9NS,-1,23NS), + CLOCK & TRN_LH, DELAY(12NS,-1,28NS), + DELAY(12NS,-1,28NS) + ) + } + TRISTATE: + ENABLE LO GBAR + QA_O QB_O QC_O QD_O = { + CASE( + DISABLE & TRN_HZ, DELAY(1NS,-1,10NS), + DISABLE & TRN_LZ, DELAY(3NS,-1,13NS), + CLOCK & TRN_LH, DELAY(4NS,-1,13NS), + CLOCK & TRN_HL, DELAY(7NS,-1,16NS), + ENABLE & TRN_ZH, DELAY(6NS,-1,18NS), + ACLEAR, DELAY(9NS,-1,20NS), + ENABLE & TRN_ZL, DELAY(6NS,-1,24NS), + DELAY(6NS,-1,24NS) + ) + } + BOOLEAN: + NOTCLEARING = { SCLRBAR!='0 ^ CHANGED(SCLRBAR,0) } + NOTLOADING = { LOADBAR!='0 ^ CHANGED(LOADBAR,0) } + FREQ: + NODE = CLK + MAXFREQ = 30MEG + WIDTH: + NODE = ACLRBAR + MIN_LO = 15NS + WIDTH: + NODE = LOADBAR + MIN_LO = 15NS + WHEN = { ACLRBAR!='0 } + WIDTH: + NODE = CLK + MIN_LO = 16.5NS + MIN_HI = 16.5NS + SETUP_HOLD: + DATA(4) = A B C D + CLOCK LH = CLK + SETUPTIME = 20NS + WHEN = { (LOADBAR!='1 ^ CHANGED(LOADBAR,0)) & ACLRBAR!='0 & NOTCLEARING } + SETUP_HOLD: + DATA(2) = ENPBAR ENTBAR + CLOCK LH = CLK + SETUPTIME_HI = 30NS + SETUPTIME_LO = 20NS + WHEN = { CHANGED(IEN,30NS) & ACLRBAR!='0 & NOTLOADING & NOTCLEARING } + SETUP_HOLD: + DATA(1) = SCLRBAR + CLOCK LH = CLK + SETUPTIME_LO = 15NS + SETUPTIME_HI = 30NS + WHEN = { ACLRBAR!='0 } + SETUP_HOLD: + DATA(1) = LOADBAR + CLOCK LH = CLK + SETUPTIME_LO = 15NS + SETUPTIME_HI = 30NS + WHEN = { ACLRBAR!='0 & NOTCLEARING } + SETUP_HOLD: + DATA(1) = ACLRBAR + CLOCK LH = CLK + RELEASETIME_LH = 10NS + SETUP_HOLD: + DATA(1) = U/DBAR + CLOCK LH = CLK + SETUPTIME = 30NS + WHEN = { ACLRBAR!='0 & NOTCLEARING & NOTLOADING } * .ENDS * *$ *----------- * 74ALS573B Octal D-TYPE Transparent Latches with 3-STATE Outputs * * The ALS/AS Data Book, 1986, TI * atl 7/20/89 Update interface and model names * .subckt 74ALS573B OCBAR C 1D 2D 3D 4D 5D 6D 7D 8D 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UA inv DPWR DGND + OCBAR OC + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} U1 dltch(8) DPWR DGND + $D_HI $D_HI C + 1D 2D 3D 4D 5D 6D 7D 8D + 1QI 2QI 3QI 4QI 5QI 6QI 7QI 8QI + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D_ALS573B_1 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 buf3a(8) DPWR DGND + 1QI 2QI 3QI 4QI 5QI 6QI 7QI 8QI + OC + 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q + D_ALS573B_2 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS573B_1 ugff ( + tpgqlhmn=6ns tpgqlhmx=6ns + tpgqhlmn=6ns tpgqhlmx=5ns + twghmn=10ns tsudgmn=10ns + thdgmn=7ns + ) .model D_ALS573B_2 utgate ( + tplhmn=2ns tplhmx=14ns + tphlmn=2ns tphlmx=14ns + tpzhmn=4ns tpzhmx=18ns + tpzlmn=4ns tpzlmx=18ns + tphzmn=2ns tphzmx=10ns + tplzmn=3ns tplzmx=15ns + ) *$ *----------- * 74ALS574A Octal D-TYPE Edge-Triggered Flip-Flops with 3-STATE Outputs * * The ALS/AS Data Book, 1986, TI * atl 7/20/89 Update interface and model names * .subckt 74ALS574A OCBAR CLK 1D 2D 3D 4D 5D 6D 7D 8D 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UOC inv DPWR DGND + OCBAR OC + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} UD dff(8) DPWR DGND + $D_HI $D_HI CLK + 1D 2D 3D 4D 5D 6D 7D 8D + SQ1 SQ2 SQ3 SQ4 SQ5 SQ6 SQ7 SQ8 + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D_ALS574A_1 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UQS buf3a(8) DPWR DGND + SQ1 SQ2 SQ3 SQ4 SQ5 SQ6 SQ7 SQ8 + OC + 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q + D_ALS574A_2 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS574A_1 ueff ( + twclklmn=14ns twclkhmn=14ns + tsudclkmn=15ns + ) .model D_ALS574A_2 utgate ( + tplhmn=4ns tplhmx=14ns + tphlmn=4ns tphlmx=14ns + tpzhmn=4ns tpzhmx=18ns + tpzlmn=4ns tpzlmx=18ns + tphzmn=2ns tphzmx=10ns + tplzmn=2ns tplzmx=12ns + ) *$ *------------------------------------------------------------------------- * 74ALS575A Octal D-TYPE Edge-Triggered Flip-Flops with 3-STATE Outputs * * The ALS/AS Data Book, 1986, TI * atl 7/21/89 Update interface and model names * .subckt 74ALS575A OCBAR CLK CLRBAR 1D 2D 3D 4D 5D 6D 7D 8D 1Q 2Q 3Q 4Q 5Q 6Q + 7Q 8Q + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UBUFF buf DPWR DGND + CLRBAR CLRBAR_BUF + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} UOC inv DPWR DGND + OCBAR OC + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} UAND anda(2,8) DPWR DGND + CLRBAR 1D + CLRBAR 2D + CLRBAR 3D + CLRBAR 4D + CLRBAR 5D + CLRBAR 6D + CLRBAR 7D + CLRBAR 8D + 1DD 2DD 3DD 4DD 5DD 6DD 7DD 8DD + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} UDFF dff(8) DPWR DGND + $D_HI $D_HI CLK + 1DD 2DD 3DD 4DD 5DD 6DD 7DD 8DD + 1QQ 2QQ 3QQ 4QQ 5QQ 6QQ 7QQ 8QQ + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D_ALS575A_1 IO_ALS00 MNTYMXDLY={MNTYMXDLY} UOCQ buf3a(8) DPWR DGND + 1QQ 2QQ 3QQ 4QQ 5QQ 6QQ 7QQ 8QQ + OC + 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q + D_ALS575A_2 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS575A_1 ueff ( + twclklmn=16.5ns twclkhmn=16.5ns + tsudclkmn=15ns + ) .model D_ALS575A_2 utgate ( + tplhmn=4ns tplhmx=14ns + tphlmn=4ns tphlmx=14ns + tpzhmn=4ns tpzhmx=18ns + tpzlmn=4ns tpzlmx=18ns + tphzmn=2ns tphzmx=10ns + tplzmn=3ns tplzmx=13ns + ) *$ *------------------------------------------------------------------------- * 74ALS576A Octal D-TYPE Edge-Triggered Flip-Flops with 3-STATE Outputs * * The ALS/AS Data Book, 1986, TI * atl 7/21/89 Update interface and model names * .subckt 74ALS576A OCBAR CLK 1D 2D 3D 4D 5D 6D 7D 8D 1QBAR 2QBAR 3QBAR 4QBAR + 5QBAR 6QBAR 7QBAR 8QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UOC inv DPWR DGND + OCBAR OC + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} UDFF dff(8) DPWR DGND + $D_HI $D_HI CLK + 1D 2D 3D 4D 5D 6D 7D 8D + 1QQ 2QQ 3QQ 4QQ 5QQ 6QQ 7QQ 8QQ + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D_ALS576A_1 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UOCQ inv3a(8) DPWR DGND + 1QQ 2QQ 3QQ 4QQ 5QQ 6QQ 7QQ 8QQ + OC + 1QBAR 2QBAR 3QBAR 4QBAR 5QBAR 6QBAR 7QBAR 8QBAR + D_ALS576A_2 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS576A_1 ueff ( + twclklmn=16.5ns twclkhmn=16.5ns + tsudclkmn=15ns + ) .model D_ALS576A_2 utgate ( + tplhmn=4ns tplhmx=14ns + tphlmn=4ns tphlmx=14ns + tpzhmn=4ns tpzhmx=18ns + tpzlmn=4ns tpzlmx=18ns + tphzmn=2ns tphzmx=10ns + tplzmn=3ns tplzmx=15ns + ) *$ *------------------------------------------------------------------------- * 74ALS577A Octal D-TYPE Edge-Triggered Flip-Flops with 3-STATE Outputs * * The ALS/AS Data Book, 1986, TI * atl 9/6/89 Update interface and model names * .subckt 74ALS577A OCBAR CLK CLRBAR 1D 2D 3D 4D 5D 6D 7D 8D 1QBAR 2QBAR 3QBAR + 4QBAR 5QBAR 6QBAR 7QBAR 8QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UBUF buf DPWR DGND + CLRBAR CLB + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} UINV inv DPWR DGND + OCBAR OC + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} UD anda(2,8) DPWR DGND + 1D CLB + 2D CLB + 3D CLB + 4D CLB + 5D CLB + 6D CLB + 7D CLB + 8D CLB + D1 D2 D3 D4 D5 D6 D7 D8 + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} UQI dff(8) DPWR DGND + $D_HI $D_HI CLK + D1 D2 D3 D4 D5 D6 D7 D8 + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + 1QI 2QI 3QI 4QI 5QI 6QI 7QI 8QI + D_ALS577A_1 IO_ALS00 MNTYMXDLY={MNTYMXDLY} UQB buf3a(8) DPWR DGND + 1QI 2QI 3QI 4QI 5QI 6QI 7QI 8QI + OC + 1QBAR 2QBAR 3QBAR 4QBAR 5QBAR 6QBAR 7QBAR 8QBAR + D_ALS577A_2 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS577A_1 ueff ( + twclklmn=16.5ns twclkhmn=16.5ns + tsudclkmn=15ns + ) .model D_ALS577A_2 utgate ( + tplhmn=4ns tplhmx=14ns + tphlmn=4ns tphlmx=14ns + tpzhmn=4ns tpzhmx=18ns + tpzlmn=4ns tpzlmx=18ns + tphzmn=2ns tphzmx=10ns + tplzmn=3ns tplzmx=15ns + ) *$ *------------------------------------------------------------------------- * 74ALS580A Octal D-TYPE Transparent Inverting Latches with 3-STATE Outputs * * The ALS/AS Data Book, 1986, TI * atl 7/21/89 Update interface and model names * .subckt 74ALS580A OCBAR C 1D 2D 3D 4D 5D 6D 7D 8D 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U0 inv DPWR DGND + OCBAR OC + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} U1 dltch(8) DPWR DGND + $D_HI $D_HI C + 1D 2D 3D 4D 5D 6D 7D 8D + 1QI 2QI 3QI 4QI 5QI 6QI 7QI 8QI + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D_ALS580A_1 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 inv3a(8) DPWR DGND + 1QI 2QI 3QI 4QI 5QI 6QI 7QI 8QI + OC + 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q + D_ALS580A_2 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS580A_1 ugff ( + tpgqlhmn=5ns tpgqlhmx=7ns + tpgqhlmn=5ns tpgqhlmx=4ns + twghmn=15ns tsudgmn=10ns + thdgmn=10ns + ) .model D_ALS580A_2 utgate ( + tplhmn=3ns tplhmx=18ns + tphlmn=3ns tphlmx=14ns + tpzhmn=4ns tpzhmx=18ns + tpzlmn=4ns tpzlmx=18ns + tphzmn=2ns tphzmx=10ns + tplzmn=3ns tplzmx=15ns + ) *$ *------------------------------------------------------------------------- * 74ALS614 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH OPEN-COLLECTOR OUTPUTS * * ALS/AS LOGIC CIRCUITS DATA BOOK, 1986, TI * NH 9/4/92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74ALS614 GAB_I GBABAR_I CAB_I CBA_I SAB_I SBA_I + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UBUF BUFA(16) DPWR DGND + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} * U1 DFF(8) DPWR DGND + $D_HI $D_HI CAB + A1 A2 A3 A4 A5 A6 A7 A8 + QA1 QA2 QA3 QA4 QA5 QA6 QA7 QA8 + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D0_EFF IO_ALS00 * U2 DFF(8) DPWR DGND + $D_HI $D_HI CBA + B1 B2 B3 B4 B5 B6 B7 B8 + QB1 QB2 QB3 QB4 QB5 QB6 QB7 QB8 + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D0_EFF IO_ALS00 * UALS614LOG LOGICEXP(38,22) DPWR DGND + GAB_I GBABAR_I CAB_I CBA_I SAB_I SBA_I + A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 + QA1 QA2 QA3 QA4 QA5 QA6 QA7 QA8 QB1 QB2 QB3 QB4 QB5 QB6 QB7 QB8 + GAB GBABAR CAB CBA SAB SBA + A1O A2O A3O A4O A5O A6O A7O A8O B1O B2O B3O B4O B5O B6O B7O B8O + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} + + LOGIC: * BUFFERS + GAB = { GAB_I } + GBABAR = { GBABAR_I } + CAB = { CAB_I } + CBA = { CBA_I } + SAB = { SAB_I } + SBA = { SBA_I } + + TRANS_B = { ~SBA & ~GBABAR } + STORE_B = { SBA & ~GBABAR } + TRANS_A = { ~SAB & GAB } + STORE_A = { SAB & GAB } + A1O = { ~( (STORE_B & QB1) | (TRANS_B & B1) ) } + A2O = { ~( (STORE_B & QB2) | (TRANS_B & B2) ) } + A3O = { ~( (STORE_B & QB3) | (TRANS_B & B3) ) } + A4O = { ~( (STORE_B & QB4) | (TRANS_B & B4) ) } + A5O = { ~( (STORE_B & QB5) | (TRANS_B & B5) ) } + A6O = { ~( (STORE_B & QB6) | (TRANS_B & B6) ) } + A7O = { ~( (STORE_B & QB7) | (TRANS_B & B7) ) } + A8O = { ~( (STORE_B & QB8) | (TRANS_B & B8) ) } + B1O = { ~( (STORE_A & QA1) | (TRANS_A & A1) ) } + B2O = { ~( (STORE_A & QA2) | (TRANS_A & A2) ) } + B3O = { ~( (STORE_A & QA3) | (TRANS_A & A3) ) } + B4O = { ~( (STORE_A & QA4) | (TRANS_A & A4) ) } + B5O = { ~( (STORE_A & QA5) | (TRANS_A & A5) ) } + B6O = { ~( (STORE_A & QA6) | (TRANS_A & A6) ) } + B7O = { ~( (STORE_A & QA7) | (TRANS_A & A7) ) } + B8O = { ~( (STORE_A & QA8) | (TRANS_A & A8) ) } * UALS614DLY PINDLY (16,0,6) DPWR DGND + A1O A2O A3O A4O A5O A6O A7O A8O B1O B2O B3O B4O B5O B6O B7O B8O + GAB GBABAR CAB CBA SAB SBA + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + IO_ALS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + A_OUTPUT = { (GAB!='1 & GBABAR!='1) | (GAB!='0 & GBABAR!='1) } + B_OUTPUT = { (GAB!='0 & GBABAR!='0) | (GAB!='0 & GBABAR!='1) } + CH_G = { CHANGED(GBABAR,0) | CHANGED(GAB,0) } + + PINDLY: + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B = { + CASE( + CHANGED(CBA,0) & TRN_LH, DELAY(20NS,37NS,64NS), + CHANGED(SBA,0) & TRN_LH, DELAY(19NS,35NS,58NS), + A_OUTPUT & TRN_LH, DELAY(14NS,31NS,51NS), + A_OUTPUT & CH_G & TRN_LH, DELAY(9NS,16NS,27NS), + A_OUTPUT & CH_G & TRN_HL, DELAY(6NS,12NS,22NS), + CHANGED(SBA,0) & TRN_HL, DELAY(5NS,12NS,22NS), + CHANGED(CBA,0) & TRN_HL, DELAY(6NS,14NS,20NS), + A_OUTPUT & TRN_HL, DELAY(2NS,6NS,12NS), + DELAY(0NS,0NS,0NS) ;DEFAULT + ) + } + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B = { + CASE( + CHANGED(CAB,0) & TRN_LH, DELAY(20NS,37NS,64NS), + CHANGED(SAB,0) & TRN_LH, DELAY(19NS,35NS,58NS), + B_OUTPUT & TRN_LH, DELAY(14NS,31NS,51NS), + B_OUTPUT & CH_G & TRN_LH, DELAY(9NS,16NS,27NS), + B_OUTPUT & CH_G & TRN_HL, DELAY(6NS,12NS,22NS), + CHANGED(SAB,0) & TRN_HL, DELAY(5NS,12NS,22NS), + CHANGED(CAB,0) & TRN_HL, DELAY(6NS,14NS,20NS), + B_OUTPUT & TRN_HL, DELAY(2NS,6NS,12NS), + DELAY(0NS,0NS,0NS) ;DEFAULT + ) + } * .ENDS * *$ *------------------------------------------------------------------------- * 74ALS615 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH OPEN-COLLECTOR OUTPUTS * * ALS/AS LOGIC CIRCUITS DATA BOOK, 1986, TI * NH 9/8/92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74ALS615 GAB_I GBABAR_I CAB_I CBA_I SAB_I SBA_I + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UBUF BUFA(16) DPWR DGND + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} * U1 DFF(8) DPWR DGND + $D_HI $D_HI CAB + A1 A2 A3 A4 A5 A6 A7 A8 + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + QA1BAR QA2BAR QA3BAR QA4BAR QA5BAR QA6BAR QA7BAR QA8BAR + D0_EFF IO_ALS00 * U2 DFF(8) DPWR DGND + $D_HI $D_HI CBA + B1 B2 B3 B4 B5 B6 B7 B8 + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + QB1BAR QB2BAR QB3BAR QB4BAR QB5BAR QB6BAR QB7BAR QB8BAR + D0_EFF IO_ALS00 * UALS615LOG LOGICEXP(38,22) DPWR DGND + GAB_I GBABAR_I CAB_I CBA_I SAB_I SBA_I + A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 + QA1BAR QA2BAR QA3BAR QA4BAR QA5BAR QA6BAR QA7BAR QA8BAR + QB1BAR QB2BAR QB3BAR QB4BAR QB5BAR QB6BAR QB7BAR QB8BAR + GAB GBABAR CAB CBA SAB SBA + A1O A2O A3O A4O A5O A6O A7O A8O B1O B2O B3O B4O B5O B6O B7O B8O + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} + + LOGIC: * BUFFERS + GAB = { GAB_I } + GBABAR = { GBABAR_I } + CAB = { CAB_I } + CBA = { CBA_I } + SAB = { SAB_I } + SBA = { SBA_I } + + TRANS_B = { ~SBA & ~GBABAR } + STORE_B = { SBA & ~GBABAR } + TRANS_A = { ~SAB & GAB } + STORE_A = { SAB & GAB } + A1O = { ~( (STORE_B & QB1BAR) | (TRANS_B & ~B1) ) } + A2O = { ~( (STORE_B & QB2BAR) | (TRANS_B & ~B2) ) } + A3O = { ~( (STORE_B & QB3BAR) | (TRANS_B & ~B3) ) } + A4O = { ~( (STORE_B & QB4BAR) | (TRANS_B & ~B4) ) } + A5O = { ~( (STORE_B & QB5BAR) | (TRANS_B & ~B5) ) } + A6O = { ~( (STORE_B & QB6BAR) | (TRANS_B & ~B6) ) } + A7O = { ~( (STORE_B & QB7BAR) | (TRANS_B & ~B7) ) } + A8O = { ~( (STORE_B & QB8BAR) | (TRANS_B & ~B8) ) } + B1O = { ~( (STORE_A & QA1BAR) | (TRANS_A & ~A1) ) } + B2O = { ~( (STORE_A & QA2BAR) | (TRANS_A & ~A2) ) } + B3O = { ~( (STORE_A & QA3BAR) | (TRANS_A & ~A3) ) } + B4O = { ~( (STORE_A & QA4BAR) | (TRANS_A & ~A4) ) } + B5O = { ~( (STORE_A & QA5BAR) | (TRANS_A & ~A5) ) } + B6O = { ~( (STORE_A & QA6BAR) | (TRANS_A & ~A6) ) } + B7O = { ~( (STORE_A & QA7BAR) | (TRANS_A & ~A7) ) } + B8O = { ~( (STORE_A & QA8BAR) | (TRANS_A & ~A8) ) } * UALS615DLY PINDLY (16,0,6) DPWR DGND + A1O A2O A3O A4O A5O A6O A7O A8O B1O B2O B3O B4O B5O B6O B7O B8O + GAB GBABAR CAB CBA SAB SBA + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + IO_ALS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + A_OUTPUT = { (GAB!='1 & GBABAR!='1) | (GAB!='0 & GBABAR!='1) } + B_OUTPUT = { (GAB!='0 & GBABAR!='0) | (GAB!='0 & GBABAR!='1) } + CH_G = { CHANGED(GBABAR,0) | CHANGED(GAB,0) } + + PINDLY: + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B = { + CASE( + CHANGED(CBA,0) & TRN_LH, DELAY(19NS,33NS,64NS), + CHANGED(SBA,0) & TRN_LH, DELAY(19NS,35NS,62NS), + A_OUTPUT & TRN_LH, DELAY(12NS,28NS,56NS), + CH_G & TRN_LH, DELAY(6NS,17NS,27NS), + CHANGED(SBA,0) & TRN_HL, DELAY(5NS,15NS,25NS), + CH_G & TRN_HL, DELAY(6NS,14NS,24NS), + CHANGED(CBA,0) & TRN_HL, DELAY(6NS,14NS,22NS), + A_OUTPUT & TRN_HL, DELAY(4NS,11NS,20NS), + DELAY(0NS,0NS,0NS) ;DEFAULT + ) + } + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B = { + CASE( + CHANGED(CAB,0) & TRN_LH, DELAY(19NS,33NS,64NS), + CHANGED(SAB,0) & TRN_LH, DELAY(19NS,35NS,62NS), + B_OUTPUT & TRN_LH, DELAY(12NS,28NS,56NS), + CH_G & TRN_LH, DELAY(6NS,17NS,27NS), + CHANGED(SAB,0) & TRN_HL, DELAY(5NS,15NS,25NS), + CH_G & TRN_HL, DELAY(6NS,14NS,24NS), + CHANGED(CAB,0) & TRN_HL, DELAY(6NS,14NS,22NS), + B_OUTPUT & TRN_HL, DELAY(4NS,11NS,20NS), + DELAY(0NS,0NS,0NS) ;DEFAULT + ) + } * .ENDS * *$ *--------- * 74ALS620A OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS * * ALS/AS LOGIC CIRCUITS DATA BOOK, 1986, TI * JLS 9-3-92 UPDATE TIMING * .SUBCKT 74ALS620A GBABAR_I GAB_I + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 BUF DPWR DGND + GAB_I GAB + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} U2 INV DPWR DGND + GBABAR_I GBA + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} * U3 INV3A(8) DPWR DGND + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + GAB + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + D_ALS620A_AB IO_ALS00 + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U4 INV3A(8) DPWR DGND + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + GBA + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + D_ALS620A_BA IO_ALS00 + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} * .MODEL D_ALS620A_AB UTGATE ( + TPLHMN=2NS TPLHMX=10NS + TPHLMN=2NS TPHLMX=10NS + TPZHMN=3NS TPZHMX=18NS + TPZLMN=5NS TPZLMX=25NS + TPHZMN=2NS TPHZMX=12NS + TPLZMN=3NS TPLZMX=18NS + ) .MODEL D_ALS620A_BA UTGATE ( + TPLHMN=2NS TPLHMX=10NS + TPHLMN=2NS TPHLMX=10NS + TPZHMN=3NS TPZHMX=17NS + TPZLMN=5NS TPZLMX=25NS + TPHZMN=2NS TPHZMX=12NS + TPLZMN=3NS TPLZMX=18NS + ) * .ENDS * *$ *------------------------------------------------------------------------- * 74ALS621A OCTAL BUS TRANSCEIVERS WITH OPEN-COLLECTOR OUTPUTS * * ALS/AS LOGIC CIRCUITS DATA BOOK, 1986, TI * KN 8/28/92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74ALS621A GBABAR_I GAB_I A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UALS621ALOG LOGICEXP(18,18) DPWR DGND + GBABAR_I GAB_I A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + GBABAR GAB A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} + + LOGIC: + * BUFFER: + GBABAR = { GBABAR_I } + GBA = { ~GBABAR_I } + GAB = { GAB_I } + * OUTPUT ASSIGNMENTS + A1 = { ~(~B1_B & GBA) } + A2 = { ~(~B2_B & GBA) } + A3 = { ~(~B3_B & GBA) } + A4 = { ~(~B4_B & GBA) } + A5 = { ~(~B5_B & GBA) } + A6 = { ~(~B6_B & GBA) } + A7 = { ~(~B7_B & GBA) } + A8 = { ~(~B8_B & GBA) } + B1 = { ~(~A1_B & GAB) } + B2 = { ~(~A2_B & GAB) } + B3 = { ~(~A3_B & GAB) } + B4 = { ~(~A4_B & GAB) } + B5 = { ~(~A5_B & GAB) } + B6 = { ~(~A6_B & GAB) } + B7 = { ~(~A7_B & GAB) } + B8 = { ~(~A8_B & GAB) } * UALS621ADLY PINDLY (16,0,18) DPWR DGND + A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 + GBABAR GAB A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + IO_ALS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + A_OUTPUT = { (GBABAR!='1 & GAB!='1) | (GBABAR!='1 & GAB!='0) | + (GBABAR!='0 & GAB!='1) } + B_OUTPUT = { (GBABAR!='0 & GAB!='0) | (GBABAR!='1 & GAB!='0) | + (GBABAR!='0 & GAB!='1) } + GBABAR_CHANGE = { CHANGED(GBABAR,0) } + GAB_CHANGE = { CHANGED(GAB,0) } + + PINDLY: + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B = { + CASE( + A_OUTPUT & GBABAR_CHANGE & TRN_LH, DELAY(10NS,-1,39NS), + A_OUTPUT & GBABAR_CHANGE & TRN_HL, DELAY(12NS,-1,35NS), + A_OUTPUT & TRN_LH, DELAY(10NS,-1,33NS), + A_OUTPUT & TRN_HL, DELAY(5NS,-1,20NS), + B_OUTPUT, DELAY(0NS,0NS,0NS), + DELAY(13NS,-1,40NS) ;DEFAULT + ) + } + + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B = { + CASE( + B_OUTPUT & GAB_CHANGE & TRN_LH, DELAY(10NS,-1,39NS), + B_OUTPUT & GAB_CHANGE & TRN_HL, DELAY(12NS,-1,35NS), + B_OUTPUT & TRN_LH, DELAY(10NS,-1,33NS), + B_OUTPUT & TRN_HL, DELAY(5NS,-1,20NS), + A_OUTPUT, DELAY(0NS,0NS,0NS), + DELAY(13NS,-1,40NS) ;DEFAULT + ) + } * .ENDS * *$ *------------------------------------------------------------------------- * 74ALS622A OCTAL BUS TRANSCEIVERS WITH OPEN-COLLECTOR OUTPUTS * * ALS/AS LOGIC CIRCUITS DATA BOOK, 1986, TI * KN 8/28/92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74ALS622A GBABAR_I GAB_I A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UALS622ALOG LOGICEXP(18,18) DPWR DGND + GBABAR_I GAB_I A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + GBABAR GAB A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} + + LOGIC: + * BUFFER: + GBABAR = { GBABAR_I } + GBA = { ~GBABAR } + GAB = { GAB_I } + * OUTPUT ASSIGNMENTS + A1 = { ~(B1_B & GBA) } + A2 = { ~(B2_B & GBA) } + A3 = { ~(B3_B & GBA) } + A4 = { ~(B4_B & GBA) } + A5 = { ~(B5_B & GBA) } + A6 = { ~(B6_B & GBA) } + A7 = { ~(B7_B & GBA) } + A8 = { ~(B8_B & GBA) } + B1 = { ~(A1_B & GAB) } + B2 = { ~(A2_B & GAB) } + B3 = { ~(A3_B & GAB) } + B4 = { ~(A4_B & GAB) } + B5 = { ~(A5_B & GAB) } + B6 = { ~(A6_B & GAB) } + B7 = { ~(A7_B & GAB) } + B8 = { ~(A8_B & GAB) } * UALS622ADLY PINDLY (16,0,18) DPWR DGND + A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 + GBABAR GAB A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + IO_ALS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + A_OUTPUT = { (GBABAR!='1 & GAB!='1) | (GBABAR!='1 & GAB!='0) | + (GBABAR!='0 & GAB!='1) } + B_OUTPUT = { (GBABAR!='0 & GAB!='0) | (GBABAR!='1 & GAB!='0) | + (GBABAR!='0 & GAB!='1) } + GBABAR_CHANGE = { CHANGED(GBABAR,0) } + GAB_CHANGE = { CHANGED(GAB,0) } + + PINDLY: + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B = { + CASE( + A_OUTPUT & GBABAR_CHANGE & TRN_LH, DELAY(8NS,-1,38NS), + A_OUTPUT & GBABAR_CHANGE & TRN_HL, DELAY(10NS,-1,35NS), + A_OUTPUT & TRN_LH, DELAY(8NS,-1,35NS), + A_OUTPUT & TRN_HL, DELAY(5NS,-1,19NS), + B_OUTPUT, DELAY(0NS,0NS,0NS), + DELAY(11NS,-1,39NS) ;DEFAULT + ) + } + + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B = { + CASE( + B_OUTPUT & GAB_CHANGE & TRN_LH, DELAY(8NS,-1,38NS), + B_OUTPUT & GAB_CHANGE & TRN_HL, DELAY(10NS,-1,35NS), + B_OUTPUT & TRN_LH, DELAY(8NS,-1,35NS), + B_OUTPUT & TRN_HL, DELAY(5NS,-1,19NS), + A_OUTPUT, DELAY(0NS,0NS,0NS), + DELAY(11NS,-1,39NS) ;DEFAULT + ) + } * .ENDS * *$ *--------- * 74ALS623A OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS * * ALS/AS LOGIC CIRCUITS DATA BOOK, 1986, TI * JLS 9-3-92 UPDATE TIMING * .SUBCKT 74ALS623A GBABAR_I GAB_I + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 BUF DPWR DGND + GAB_I GAB + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} U2 INV DPWR DGND + GBABAR_I GBA + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} * U3 BUF3A(8) DPWR DGND + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + GAB + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + D_ALS623A IO_ALS00 + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U4 BUF3A(8) DPWR DGND + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + GBA + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + D_ALS623A IO_ALS00 + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} * .MODEL D_ALS623A UTGATE ( + TPLHMN=2NS TPLHMX=13NS + TPHLMN=3NS TPHLMX=11NS + TPZHMN=5NS TPZHMX=22NS + TPZLMN=5NS TPZLMX=22NS + TPHZMN=2NS TPHZMX=16NS + TPLZMN=2NS TPLZMX=19NS + ) * .ENDS * *$ *------------------------------------------------------------------------- * 74ALS638A BUS TRANSCEIVERS OCTAL WITH 3-STATE AND OPEN-COLLECTOR OUTPUTS * * ALS/AS LOGIC DATA BOOK, 1986, TI * TC 09/11/92 REMODELED USING LOGICEXP, PINDLY, & CONSTRAINT DEVICES .SUBCKT 74ALS638A GBAR_I DIR_I + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 UALS638ALOG LOGICEXP(18,35) DPWR DGND + GBAR_I DIR_I + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + GBAR DIR A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 + A1_O A2_O A3_O A4_O A5_O A6_O A7_O A8_O + B1_O B2_O B3_O B4_O B5_O B6_O B7_O B8_O ENB + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} + LOGIC: + GBAR = { GBAR_I } + DIR = { DIR_I } + A1 = { A1_B } + A2 = { A2_B } + A3 = { A3_B } + A4 = { A4_B } + A5 = { A5_B } + A6 = { A6_B } + A7 = { A7_B } + A8 = { A8_B } + B1 = { B1_B } + B2 = { B2_B } + B3 = { B3_B } + B4 = { B4_B } + B5 = { B5_B } + B6 = { B6_B } + B7 = { B7_B } + B8 = { B8_B } + ENA = { ~(GBAR | DIR) } + ENB = { ~GBAR & DIR } + A1_O = { ~(ENA & B1) } + A2_O = { ~(ENA & B2) } + A3_O = { ~(ENA & B3) } + A4_O = { ~(ENA & B4) } + A5_O = { ~(ENA & B5) } + A6_O = { ~(ENA & B6) } + A7_O = { ~(ENA & B7) } + A8_O = { ~(ENA & B8) } + B1_O = { ~A1 } + B2_O = { ~A2 } + B3_O = { ~A3 } + B4_O = { ~A4 } + B5_O = { ~A5 } + B6_O = { ~A6 } + B7_O = { ~A7 } + B8_O = { ~A8 } UALS638ADLY_1 PINDLY(8,0,9) DPWR DGND + A1_O A2_O A3_O A4_O A5_O A6_O A7_O A8_O + GBAR B1 B2 B3 B4 B5 B6 B7 B8 + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + IO_ALS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + BUS_B = { CHANGED(B1,0) | CHANGED(B2,0) | CHANGED(B3,0) | CHANGED(B4,0) | + CHANGED(B5,0) | CHANGED(B6,0) | CHANGED(B7,0) | CHANGED(B8,0) } + ENABLE = { CHANGED(GBAR,0) } + PINDLY: + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B = { + CASE( + ENABLE & TRN_HL, DELAY(10NS,-1,45NS), + BUS_B & TRN_HL, DELAY(8NS,-1,30NS), + BUS_B & TRN_LH, DELAY(8NS,-1,25NS), + ENABLE & TRN_LH, DELAY(5NS,-1,25NS), + DELAY(11NS,-1,46NS) + ) + } UALS638ADLY_2 PINDLY(8,1,8) DPWR DGND + B1_O B2_O B3_O B4_O B5_O B6_O B7_O B8_O + ENB + A1 A2 A3 A4 A5 A6 A7 A8 + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + BUS_A = { CHANGED(A1,0) | CHANGED(A2,0) | CHANGED(A3,0) | CHANGED(A4,0) | + CHANGED(A5,0) | CHANGED(A6,0) | CHANGED(A7,0) | CHANGED(A8,0) } + TRISTATE: + ENABLE HI ENB + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B = { + CASE( + BUS_A, DELAY(2NS,-1,12NS), + TRN_ZH, DELAY(5NS,-1,20NS), + TRN_ZL, DELAY(5NS,-1,22NS), + TRN_HZ, DELAY(2NS,-1,10NS), + TRN_LZ, DELAY(3NS,-1,15NS), + DELAY(6NS,-1,23NS) + ) + } .ENDS *$ *------------------------------------------------------------------------- * 74ALS639A BUS TRANSCEIVERS OCTAL WITH 3-STATE AND OPEN-COLLECTOR OUTPUTS * * ALS/AS LOGIC DATA BOOK, 1986, TI * TC 09/11/92 REMODELED USING LOGICEXP, PINDLY, & CONSTRAINT DEVICES .SUBCKT 74ALS639A GBAR_I DIR_I + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 UALS639ALOG LOGICEXP(18,35) DPWR DGND + GBAR_I DIR_I + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + GBAR DIR A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 + A1_O A2_O A3_O A4_O A5_O A6_O A7_O A8_O + B1_O B2_O B3_O B4_O B5_O B6_O B7_O B8_O ENB + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} + LOGIC: + GBAR = { GBAR_I } + DIR = { DIR_I } + A1 = { A1_B } + A2 = { A2_B } + A3 = { A3_B } + A4 = { A4_B } + A5 = { A5_B } + A6 = { A6_B } + A7 = { A7_B } + A8 = { A8_B } + B1 = { B1_B } + B2 = { B2_B } + B3 = { B3_B } + B4 = { B4_B } + B5 = { B5_B } + B6 = { B6_B } + B7 = { B7_B } + B8 = { B8_B } + ENA = { ~(GBAR | DIR) } + ENB = { ~GBAR & DIR } + A1_O = { ~(ENA & ~B1) } + A2_O = { ~(ENA & ~B2) } + A3_O = { ~(ENA & ~B3) } + A4_O = { ~(ENA & ~B4) } + A5_O = { ~(ENA & ~B5) } + A6_O = { ~(ENA & ~B6) } + A7_O = { ~(ENA & ~B7) } + A8_O = { ~(ENA & ~B8) } + B1_O = { A1 } + B2_O = { A2 } + B3_O = { A3 } + B4_O = { A4 } + B5_O = { A5 } + B6_O = { A6 } + B7_O = { A7 } + B8_O = { A8 } UALS639ADLY_1 PINDLY(8,0,9) DPWR DGND + A1_O A2_O A3_O A4_O A5_O A6_O A7_O A8_O + GBAR B1 B2 B3 B4 B5 B6 B7 B8 + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + IO_ALS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + BUS_B = { CHANGED(B1,0) | CHANGED(B2,0) | CHANGED(B3,0) | CHANGED(B4,0) | + CHANGED(B5,0) | CHANGED(B6,0) | CHANGED(B7,0) | CHANGED(B8,0) } + ENABLE = { CHANGED(GBAR,0) } + PINDLY: + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B = { + CASE( + ENABLE & TRN_LH, DELAY(10NS,-1,30NS), + ENABLE & TRN_HL, DELAY(10NS,-1,35NS), + BUS_B & TRN_LH, DELAY(10NS,-1,30NS), + BUS_B & TRN_HL, DELAY(5NS,-1,22NS), + DELAY(11NS,-1,36NS) + ) + } UALS639ADLY_2 PINDLY(8,1,8) DPWR DGND + B1_O B2_O B3_O B4_O B5_O B6_O B7_O B8_O + ENB + A1 A2 A3 A4 A5 A6 A7 A8 + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + BUS_A = { CHANGED(A1,0) | CHANGED(A2,0) | CHANGED(A3,0) | CHANGED(A4,0) | + CHANGED(A5,0) | CHANGED(A6,0) | CHANGED(A7,0) | CHANGED(A8,0) } + TRISTATE: + ENABLE HI ENB + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B = { + CASE( + BUS_A, DELAY(2NS,-1,12NS), + TRN_ZH, DELAY(6NS,-1,21NS), + TRN_ZL, DELAY(8NS,-1,25NS), + TRN_HZ, DELAY(2NS,-1,10NS), + TRN_LZ, DELAY(3NS,-1,16NS), + DELAY(9NS,-1,26NS) + ) + } .ENDS *$ *--------- * 74ALS640A OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS * * ALS/AS LOGIC CIRCUITS DATA BOOK, 1986, TI * JLS 9-3-92 UPDATE TIMING * .SUBCKT 74ALS640A GBAR_I DIR_I + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 BUFA(2) DPWR DGND + GBAR_I DIR_I + GBAR DIR + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} U2 INV DPWR DGND + DIR DIRBAR + D0_GATE IO_ALS00 U3 NORA(2,2) DPWR DGND + DIRBAR GBAR DIR GBAR + ENABLEAB ENABLEBA + D0_GATE IO_ALS00 * U4 INV3A(8) DPWR DGND + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + ENABLEAB + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + D_ALS640A IO_ALS00 + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U5 INV3A(8) DPWR DGND + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + ENABLEBA + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + D_ALS640A IO_ALS00 + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} * .MODEL D_ALS640A UTGATE ( + TPLHMN=2NS TPLHMX=11NS + TPHLMN=2NS TPHLMX=10NS + TPZHMN=5NS TPZHMX=21NS + TPZLMN=8NS TPZLMX=24NS + TPHZMN=2NS TPHZMX=10NS + TPLZMN=3NS TPLZMX=15NS + ) * .ENDS * *$ *------------------------------------------------------------------------- * 74ALS641A OCTAL BUS TRANSCEIVERS WITH OPEN-COLLECTOR OUTPUTS * * ALS/AS LOGIC CIRCUITS DATA BOOK, 1986, TI * NH 8/28/92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74ALS641A GBAR_I DIR_I A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UALS641ALOG LOGICEXP(18,20) DPWR DGND + GBAR_I DIR_I A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B B1_B B2_B B3_B B4_B + B5_B B6_B B7_B B8_B + GBAR DIR A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 ATOB BTOA + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} + + LOGIC: + * BUFFER + GBAR = { GBAR_I } + DIR = { DIR_I } + * OUTPUT ASSIGNMENTS + ATOB = { ~GBAR & DIR } + BTOA = { ~GBAR & ~DIR } + A1 = { ~(~B1_B & BTOA) } + A2 = { ~(~B2_B & BTOA) } + A3 = { ~(~B3_B & BTOA) } + A4 = { ~(~B4_B & BTOA) } + A5 = { ~(~B5_B & BTOA) } + A6 = { ~(~B6_B & BTOA) } + A7 = { ~(~B7_B & BTOA) } + A8 = { ~(~B8_B & BTOA) } + B1 = { ~(~A1_B & ATOB) } + B2 = { ~(~A2_B & ATOB) } + B3 = { ~(~A3_B & ATOB) } + B4 = { ~(~A4_B & ATOB) } + B5 = { ~(~A5_B & ATOB) } + B6 = { ~(~A6_B & ATOB) } + B7 = { ~(~A7_B & ATOB) } + B8 = { ~(~A8_B & ATOB) } * UALS641ADLY PINDLY (16,0,4) DPWR DGND + A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 + GBAR DIR ATOB BTOA + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B B1_B B2_B B3_B B4_B + B5_B B6_B B7_B B8_B + IO_ALS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + A_EN = { BTOA!='0 } + B_EN = { ATOB!='0 } + + PINDLY: + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B = { + CASE( + A_EN & CHANGED(DIR,0), DELAY(8NS,-1,32NS), + CHANGED(GBAR,0), DELAY(8NS,-1,30NS), + A_EN & TRN_LH, DELAY(5NS,-1,25NS), + A_EN & TRN_HL, DELAY(3NS,-1,18NS), + B_EN & CHANGED(DIR,0), DELAY(0,0,0), + DELAY(9NS,-1,33NS) ;DEFAULT + ) + } + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B = { + CASE( + B_EN & CHANGED(DIR,0), DELAY(8NS,-1,32NS), + CHANGED(GBAR,0), DELAY(8NS,-1,30NS), + B_EN & TRN_LH, DELAY(5NS,-1,25NS), + B_EN & TRN_HL, DELAY(3NS,-1,18NS), + A_EN & CHANGED(DIR,0), DELAY(0,0,0), + DELAY(9NS,-1,33NS) ;DEFAULT + ) + } * .ENDS * *$ *------------------------------------------------------------------------- * 74ALS642A OCTAL BUS TRANSCEIVERS WITH OPEN-COLLECTOR OUTPUTS * * ALS/AS LOGIC CIRCUITS DATA BOOK, 1986, TI * NH 8/31/92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74ALS642A GBAR_I DIR_I A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UALS642ALOG LOGICEXP(18,20) DPWR DGND + GBAR_I DIR_I A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B B1_B B2_B B3_B B4_B + B5_B B6_B B7_B B8_B + GBAR DIR A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 ATOB BTOA + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} + + LOGIC: + * BUFFER + GBAR = { GBAR_I } + DIR = { DIR_I } + * OUTPUT ASSIGNMENTS + ATOB = { ~GBAR & DIR } + BTOA = { ~GBAR & ~DIR } + A1 = { ~(B1_B & BTOA) } + A2 = { ~(B2_B & BTOA) } + A3 = { ~(B3_B & BTOA) } + A4 = { ~(B4_B & BTOA) } + A5 = { ~(B5_B & BTOA) } + A6 = { ~(B6_B & BTOA) } + A7 = { ~(B7_B & BTOA) } + A8 = { ~(B8_B & BTOA) } + B1 = { ~(A1_B & ATOB) } + B2 = { ~(A2_B & ATOB) } + B3 = { ~(A3_B & ATOB) } + B4 = { ~(A4_B & ATOB) } + B5 = { ~(A5_B & ATOB) } + B6 = { ~(A6_B & ATOB) } + B7 = { ~(A7_B & ATOB) } + B8 = { ~(A8_B & ATOB) } * UALS642ADLY1 PINDLY (16,0,4) DPWR DGND + A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 + GBAR DIR ATOB BTOA + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B B1_B B2_B B3_B B4_B + B5_B B6_B B7_B B8_B + IO_ALS00_OC MNTYMXDLY={MNTYMXDLY} + + BOOLEAN: + A_EN = { BTOA!='0 } + B_EN = { ATOB!='0 } + + PINDLY: + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B = { + CASE( + CHANGED(GBAR,0) & TRN_HL, DELAY(15NS,-1,38NS), + A_EN & CHANGED(DIR,0) & TRN_HL, DELAY(15NS,-1,38NS), + CHANGED(GBAR,0) & TRN_LH, DELAY(10NS,-1,30NS), + A_EN & CHANGED(DIR,0) & TRN_LH, DELAY(10NS,-1,30NS), + A_EN & TRN_LH, DELAY(10NS,-1,30NS), + A_EN & TRN_HL, DELAY(5NS,-1,22NS), + B_EN & CHANGED(DIR,0), DELAY(0,0,0), + DELAY(16NS,0NS,39NS) ;DEFAULT + ) + } + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B = { + CASE( + B_EN & CHANGED(DIR,0) & TRN_HL, DELAY(15NS,-1,38NS), + CHANGED(GBAR,0) & TRN_HL, DELAY(15NS,-1,38NS), + CHANGED(GBAR,0) & TRN_LH, DELAY(10NS,-1,30NS), + B_EN & CHANGED(DIR,0) & TRN_LH, DELAY(10NS,-1,30NS), + B_EN & TRN_LH, DELAY(10NS,-1,30NS), + B_EN & TRN_HL, DELAY(5NS,-1,22NS), + A_EN & CHANGED(DIR,0), DELAY(0,0,0), + DELAY(16NS,0NS,39NS) ;DEFAULT + ) + } * .ENDS * *$ *----------- * 74ALS643A OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS * * THE ALS/AS DATA BOOK, 1986, TI * ATL 9/8/89 UPDATE INTERFACE AND MODEL NAMES * KC 9/1/92 * .SUBCKT 74ALS643A GBAR DIR A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 UBUF BUF DPWR DGND + DIR DR + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} UINV INVA(2) DPWR DGND + DR GBAR DRB G + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} UEN ANDA(2,2) DPWR DGND + DR G DRB G EAB EBA + D0_GATE IO_ALS00 UA BUF3A(8) DPWR DGND + B1 B2 B3 B4 B5 B6 B7 B8 + EBA + A1 A2 A3 A4 A5 A6 A7 A8 + D_ALS643A IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UB INV3A(8) DPWR DGND + A1 A2 A3 A4 A5 A6 A7 A8 + EAB + B1 B2 B3 B4 B5 B6 B7 B8 + D_ALS643A IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ENDS * .MODEL D_ALS643A UTGATE ( + TPLHMN=2NS TPLHMX=13NS + TPHLMN=2NS TPHLMX=11NS + TPZHMN=5NS TPZHMX=25NS + TPZLMN=5NS TPZLMX=25NS + TPHZMN=2NS TPHZMX=10NS + TPLZMN=3NS TPLZMX=17NS + ) * *$ *------------------------------------------------------------------------- * 74ALS644A OCTAL BUS TRANSCEIVERS WITH OPEN-COLLECTOR OUTPUTS * * ALS/AS LOGIC CIRCUITS DATA BOOK, 1986, TI * NH 8/31/92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74ALS644A GBAR_I DIR_I A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UALS644ALOG LOGICEXP(18,20) DPWR DGND + GBAR_I DIR_I A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B B1_B B2_B B3_B B4_B + B5_B B6_B B7_B B8_B + GBAR DIR A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 ATOB BTOA + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} + + LOGIC: + * BUFFER + GBAR = { GBAR_I } + DIR = { DIR_I } + * OUTPUT ASSIGNMENTS + ATOB = { ~GBAR & DIR } + BTOA = { ~GBAR & ~DIR } + A1 = { ~(~B1_B & BTOA) } + A2 = { ~(~B2_B & BTOA) } + A3 = { ~(~B3_B & BTOA) } + A4 = { ~(~B4_B & BTOA) } + A5 = { ~(~B5_B & BTOA) } + A6 = { ~(~B6_B & BTOA) } + A7 = { ~(~B7_B & BTOA) } + A8 = { ~(~B8_B & BTOA) } + B1 = { ~(A1_B & ATOB) } + B2 = { ~(A2_B & ATOB) } + B3 = { ~(A3_B & ATOB) } + B4 = { ~(A4_B & ATOB) } + B5 = { ~(A5_B & ATOB) } + B6 = { ~(A6_B & ATOB) } + B7 = { ~(A7_B & ATOB) } + B8 = { ~(A8_B & ATOB) } * UALS644ADLY PINDLY (16,0,4) DPWR DGND + A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 + GBAR DIR ATOB BTOA + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B B1_B B2_B B3_B B4_B + B5_B B6_B B7_B B8_B + IO_ALS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + A_EN = { BTOA!='0 } + B_EN = { ATOB!='0 } + + PINDLY: + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B = { + CASE( + CHANGED(GBAR,0) & TRN_HL, DELAY(10NS,-1,35NS), + A_EN & CHANGED(DIR,0) & TRN_HL, DELAY(10NS,-1,35NS), + CHANGED(GBAR,0) & TRN_LH, DELAY(8NS,-1,30NS), + A_EN & TRN_LH, DELAY(10NS,-1,30NS), + A_EN & CHANGED(DIR,0) & TRN_LH, DELAY(8NS,-1,26NS), + A_EN & TRN_HL, DELAY(5NS,-1,21NS), + B_EN & CHANGED(DIR,0), DELAY(0,0,0), + DELAY(11NS,-1,36NS) ;DEFAULT + ) + } + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B = { + CASE( + B_EN & CHANGED(DIR,0) & TRN_HL, DELAY(15NS,-1,35NS), + CHANGED(GBAR,0) & TRN_HL, DELAY(15NS,-1,35NS), + B_EN & CHANGED(DIR,0) & TRN_LH, DELAY(10NS,-1,30NS), + B_EN & TRN_LH, DELAY(10NS,-1,30NS), + CHANGED(GBAR,0) & TRN_LH, DELAY(8NS,-1,26NS), + B_EN & TRN_HL, DELAY(5NS,-1,22NS), + A_EN & CHANGED(DIR,0), DELAY(0,0,0), + DELAY(16NS,-1,36NS) ;DEFAULT + ) + } * .ENDS * *$ *-------------------------------------------------------------------------- * 74ALS645A OCTAL BUS TRANSCEIVERS * * THE ALS/AS DATA BOOK, 1986, TI * ATL 7/24/89 UPDATE INTERFACE AND MODEL NAMES * KN 9/1/92 CHECK * .SUBCKT 74ALS645A GBAR DIR A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UBUFF BUFA(2) DPWR DGND + GBAR DIR GBAR_BUF DIR_BUF + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} UA NOR(2) DPWR DGND + GBAR_BUF DIR_BUF T1 + D0_GATE IO_ALS00 UB INV DPWR DGND + GBAR_BUF RE1 + D0_GATE IO_ALS00 UC AND(2) DPWR DGND + RE1 DIR_BUF T2 + D0_GATE IO_ALS00 U1 BUF3A(8) DPWR DGND + A1 A2 A3 A4 A5 A6 A7 A8 + T2 + B1 B2 B3 B4 B5 B6 B7 B8 + D_ALS645A IO_ALS00_ST MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 BUF3A(8) DPWR DGND + B1 B2 B3 B4 B5 B6 B7 B8 + T1 + A1 A2 A3 A4 A5 A6 A7 A8 + D_ALS645A IO_ALS00_ST MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ENDS * .MODEL D_ALS645A UTGATE ( + TPLHMN=3NS TPLHMX=10NS + TPHLMN=3NS TPHLMX=10NS + TPZHMN=5NS TPZHMX=20NS + TPZLMN=5NS TPZLMX=20NS + TPHZMN=2NS TPHZMX=10NS + TPLZMN=4NS TPLZMX=15NS + ) * *$ *--------- * 74ALS646 OCTAL BUS TRANSCEIVER/REGISTER WITH 3-STATE OUTPUTS * * ALS/AS Logic Data Book, 1986, TI * JSW 8/31/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74ALS646 GBAR_I DIR_I CBA_I SBA_I CAB_I SAB_I + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UALS646LOG1 LOGICEXP(38,40) DPWR DGND + GBAR_I DIR_I CBA_I SBA_I CAB_I SAB_I + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + QA1 QA2 QA3 QA4 QA5 QA6 QA7 QA8 + QB1 QB2 QB3 QB4 QB5 QB6 QB7 QB8 + GBAR DIR CBA SBA CAB SAB + A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 + A1_OUT A2_OUT A3_OUT A4_OUT A5_OUT A6_OUT A7_OUT A8_OUT + B1_OUT B2_OUT B3_OUT B4_OUT B5_OUT B6_OUT B7_OUT B8_OUT + ENA ENB + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} + LOGIC: + GBAR = { GBAR_I } + DIR = { DIR_I } + CBA = { CBA_I } + SBA = { SBA_I } + SBABAR = { ~SBA } + CAB = { CAB_I } + SAB = { SAB_I } + SABBAR = { ~SAB } + ENA = { ~DIR & ~GBAR } + ENB = { DIR & ~GBAR } + A1 = { A1_B } + B1 = { B1_B } + A2 = { A2_B } + B2 = { B2_B } + A3 = { A3_B } + B3 = { B3_B } + A4 = { A4_B } + B4 = { B4_B } + A5 = { A5_B } + B5 = { B5_B } + A6 = { A6_B } + B6 = { B6_B } + A7 = { A7_B } + B7 = { B7_B } + A8 = { A8_B } + B8 = { B8_B } + A1_OUT = { ~((~B1 & SBABAR) | (SBA & QB1)) } + B1_OUT = { ~((~A1 & SABBAR) | (SAB & QA1)) } + A2_OUT = { ~((~B2 & SBABAR) | (SBA & QB2)) } + B2_OUT = { ~((~A2 & SABBAR) | (SAB & QA2)) } + A3_OUT = { ~((~B3 & SBABAR) | (SBA & QB3)) } + B3_OUT = { ~((~A3 & SABBAR) | (SAB & QA3)) } + A4_OUT = { ~((~B4 & SBABAR) | (SBA & QB4)) } + B4_OUT = { ~((~A4 & SABBAR) | (SAB & QA4)) } + A5_OUT = { ~((~B5 & SBABAR) | (SBA & QB5)) } + B5_OUT = { ~((~A5 & SABBAR) | (SAB & QA5)) } + A6_OUT = { ~((~B6 & SBABAR) | (SBA & QB6)) } + B6_OUT = { ~((~A6 & SABBAR) | (SAB & QA6)) } + A7_OUT = { ~((~B7 & SBABAR) | (SBA & QB7)) } + B7_OUT = { ~((~A7 & SABBAR) | (SAB & QA7)) } + A8_OUT = { ~((~B8 & SBABAR) | (SBA & QB8)) } + B8_OUT = { ~((~A8 & SABBAR) | (SAB & QA8)) } * UAREG DFF(8) DPWR DGND $D_HI $D_HI CAB + A1 A2 A3 A4 A5 A6 A7 A8 + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + QA1 QA2 QA3 QA4 QA5 QA6 QA7 QA8 + D0_EFF IO_ALS00 * UBREG DFF(8) DPWR DGND $D_HI $D_HI CBA + B1 B2 B3 B4 B5 B6 B7 B8 + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + QB1 QB2 QB3 QB4 QB5 QB6 QB7 QB8 + D0_EFF IO_ALS00 * UALS646DLY PINDLY (16,2,23) DPWR DGND + A1_OUT A2_OUT A3_OUT A4_OUT A5_OUT A6_OUT A7_OUT A8_OUT B1_OUT B2_OUT B3_OUT B4_OUT B5_OUT B6_OUT B7_OUT B8_OUT + ENA ENB + A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 CAB CBA SAB SBA GBAR DIR DIR + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + IO_ALS00 + MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + TRISTATE: + ENABLE HI ENA + A1_B = { + CASE( + CHANGED(CBA,0) & TRN_LH & SBA=='1, DELAY(10NS,20NS,30NS), + CHANGED(CBA,0) & TRN_HL & SBA=='1, DELAY(5NS,11NS,17NS), + CHANGED(B1,0) & TRN_LH & SBA!='1, DELAY(5NS,11NS,20NS), + CHANGED(B1,0) & TRN_HL & SBA!='1, DELAY(3NS,7.5NS,12NS), + CHANGED(SBA,0) & B1!='0 & TRN_LH, DELAY(15NS,24NS,35NS), + CHANGED(SBA,0) & TRN_LH, DELAY(8NS,17NS,25NS), + CHANGED(SBA,0) & TRN_HL, DELAY(5NS,13NS,20NS), + CHANGED(GBAR,0) & TRN_ZH, DELAY(3NS,10NS,17NS), + CHANGED(GBAR,0) & TRN_ZL, DELAY(5NS,10NS,20NS), + CHANGED(GBAR,0) & TRN_HZ, DELAY(1NS,6NS,10NS), + CHANGED(GBAR,0) & TRN_LZ, DELAY(2NS,10NS,16NS), + CHANGED(DIR,0) & TRN_ZH, DELAY(10NS,22NS,30NS), + CHANGED(DIR,0) & TRN_ZL, DELAY(5NS,14.5NS,25NS), + CHANGED(DIR,0) & TRN_HZ, DELAY(1NS,6NS,10NS), + CHANGED(DIR,0) & TRN_LZ, DELAY(2NS,10NS,16NS), + DELAY(16NS,25NS,36NS) + ) + } + A2_B = { + CASE( + CHANGED(CBA,0) & TRN_LH & SBA=='1, DELAY(10NS,20NS,30NS), + CHANGED(CBA,0) & TRN_HL & SBA=='1, DELAY(5NS,11NS,17NS), + CHANGED(B2,0) & TRN_LH & SBA!='1, DELAY(5NS,11NS,20NS), + CHANGED(B2,0) & TRN_HL & SBA!='1, DELAY(3NS,7.5NS,12NS), + CHANGED(SBA,0) & B2!='0 & TRN_LH, DELAY(15NS,24NS,35NS), + CHANGED(SBA,0) & TRN_LH, DELAY(8NS,17NS,25NS), + CHANGED(SBA,0) & TRN_HL, DELAY(5NS,13NS,20NS), + CHANGED(GBAR,0) & TRN_ZH, DELAY(3NS,10NS,17NS), + CHANGED(GBAR,0) & TRN_ZL, DELAY(5NS,10NS,20NS), + CHANGED(GBAR,0) & TRN_HZ, DELAY(1NS,6NS,10NS), + CHANGED(GBAR,0) & TRN_LZ, DELAY(2NS,10NS,16NS), + CHANGED(DIR,0) & TRN_ZH, DELAY(10NS,22NS,30NS), + CHANGED(DIR,0) & TRN_ZL, DELAY(5NS,14.5NS,25NS), + CHANGED(DIR,0) & TRN_HZ, DELAY(1NS,6NS,10NS), + CHANGED(DIR,0) & TRN_LZ, DELAY(2NS,10NS,16NS), + DELAY(16NS,25NS,36NS) + ) + } + A3_B = { + CASE( + CHANGED(CBA,0) & TRN_LH & SBA=='1, DELAY(10NS,20NS,30NS), + CHANGED(CBA,0) & TRN_HL & SBA=='1, DELAY(5NS,11NS,17NS), + CHANGED(B3,0) & TRN_LH & SBA!='1, DELAY(5NS,11NS,20NS), + CHANGED(B3,0) & TRN_HL & SBA!='1, DELAY(3NS,7.5NS,12NS), + CHANGED(SBA,0) & B3!='0 & TRN_LH, DELAY(15NS,24NS,35NS), + CHANGED(SBA,0) & TRN_LH, DELAY(8NS,17NS,25NS), + CHANGED(SBA,0) & TRN_HL, DELAY(5NS,13NS,20NS), + CHANGED(GBAR,0) & TRN_ZH, DELAY(3NS,10NS,17NS), + CHANGED(GBAR,0) & TRN_ZL, DELAY(5NS,10NS,20NS), + CHANGED(GBAR,0) & TRN_HZ, DELAY(1NS,6NS,10NS), + CHANGED(GBAR,0) & TRN_LZ, DELAY(2NS,10NS,16NS), + CHANGED(DIR,0) & TRN_ZH, DELAY(10NS,22NS,30NS), + CHANGED(DIR,0) & TRN_ZL, DELAY(5NS,14.5NS,25NS), + CHANGED(DIR,0) & TRN_HZ, DELAY(1NS,6NS,10NS), + CHANGED(DIR,0) & TRN_LZ, DELAY(2NS,10NS,16NS), + DELAY(16NS,25NS,36NS) + ) + } + A4_B = { + CASE( + CHANGED(CBA,0) & TRN_LH & SBA=='1, DELAY(10NS,20NS,30NS), + CHANGED(CBA,0) & TRN_HL & SBA=='1, DELAY(5NS,11NS,17NS), + CHANGED(B4,0) & TRN_LH & SBA!='1, DELAY(5NS,11NS,20NS), + CHANGED(B4,0) & TRN_HL & SBA!='1, DELAY(3NS,7.5NS,12NS), + CHANGED(SBA,0) & B4!='0 & TRN_LH, DELAY(15NS,24NS,35NS), + CHANGED(SBA,0) & TRN_LH, DELAY(8NS,17NS,25NS), + CHANGED(SBA,0) & TRN_HL, DELAY(5NS,13NS,20NS), + CHANGED(GBAR,0) & TRN_ZH, DELAY(3NS,10NS,17NS), + CHANGED(GBAR,0) & TRN_ZL, DELAY(5NS,10NS,20NS), + CHANGED(GBAR,0) & TRN_HZ, DELAY(1NS,6NS,10NS), + CHANGED(GBAR,0) & TRN_LZ, DELAY(2NS,10NS,16NS), + CHANGED(DIR,0) & TRN_ZH, DELAY(10NS,22NS,30NS), + CHANGED(DIR,0) & TRN_ZL, DELAY(5NS,14.5NS,25NS), + CHANGED(DIR,0) & TRN_HZ, DELAY(1NS,6NS,10NS), + CHANGED(DIR,0) & TRN_LZ, DELAY(2NS,10NS,16NS), + DELAY(16NS,25NS,36NS) + ) + } + A5_B = { + CASE( + CHANGED(CBA,0) & TRN_LH & SBA=='1, DELAY(10NS,20NS,30NS), + CHANGED(CBA,0) & TRN_HL & SBA=='1, DELAY(5NS,11NS,17NS), + CHANGED(B5,0) & TRN_LH & SBA!='1, DELAY(5NS,11NS,20NS), + CHANGED(B5,0) & TRN_HL & SBA!='1, DELAY(3NS,7.5NS,12NS), + CHANGED(SBA,0) & B5!='0 & TRN_LH, DELAY(15NS,24NS,35NS), + CHANGED(SBA,0) & TRN_LH, DELAY(8NS,17NS,25NS), + CHANGED(SBA,0) & TRN_HL, DELAY(5NS,13NS,20NS), + CHANGED(GBAR,0) & TRN_ZH, DELAY(3NS,10NS,17NS), + CHANGED(GBAR,0) & TRN_ZL, DELAY(5NS,10NS,20NS), + CHANGED(GBAR,0) & TRN_HZ, DELAY(1NS,6NS,10NS), + CHANGED(GBAR,0) & TRN_LZ, DELAY(2NS,10NS,16NS), + CHANGED(DIR,0) & TRN_ZH, DELAY(10NS,22NS,30NS), + CHANGED(DIR,0) & TRN_ZL, DELAY(5NS,14.5NS,25NS), + CHANGED(DIR,0) & TRN_HZ, DELAY(1NS,6NS,10NS), + CHANGED(DIR,0) & TRN_LZ, DELAY(2NS,10NS,16NS), + DELAY(16NS,25NS,36NS) + ) + } + A6_B = { + CASE( + CHANGED(CBA,0) & TRN_LH & SBA=='1, DELAY(10NS,20NS,30NS), + CHANGED(CBA,0) & TRN_HL & SBA=='1, DELAY(5NS,11NS,17NS), + CHANGED(B6,0) & TRN_LH & SBA!='1, DELAY(5NS,11NS,20NS), + CHANGED(B6,0) & TRN_HL & SBA!='1, DELAY(3NS,7.5NS,12NS), + CHANGED(SBA,0) & B6!='0 & TRN_LH, DELAY(15NS,24NS,35NS), + CHANGED(SBA,0) & TRN_LH, DELAY(8NS,17NS,25NS), + CHANGED(SBA,0) & TRN_HL, DELAY(5NS,13NS,20NS), + CHANGED(GBAR,0) & TRN_ZH, DELAY(3NS,10NS,17NS), + CHANGED(GBAR,0) & TRN_ZL, DELAY(5NS,10NS,20NS), + CHANGED(GBAR,0) & TRN_HZ, DELAY(1NS,6NS,10NS), + CHANGED(GBAR,0) & TRN_LZ, DELAY(2NS,10NS,16NS), + CHANGED(DIR,0) & TRN_ZH, DELAY(10NS,22NS,30NS), + CHANGED(DIR,0) & TRN_ZL, DELAY(5NS,14.5NS,25NS), + CHANGED(DIR,0) & TRN_HZ, DELAY(1NS,6NS,10NS), + CHANGED(DIR,0) & TRN_LZ, DELAY(2NS,10NS,16NS), + DELAY(16NS,25NS,36NS) + ) + } + A7_B = { + CASE( + CHANGED(CBA,0) & TRN_LH & SBA=='1, DELAY(10NS,20NS,30NS), + CHANGED(CBA,0) & TRN_HL & SBA=='1, DELAY(5NS,11NS,17NS), + CHANGED(B7,0) & TRN_LH & SBA!='1, DELAY(5NS,11NS,20NS), + CHANGED(B7,0) & TRN_HL & SBA!='1, DELAY(3NS,7.5NS,12NS), + CHANGED(SBA,0) & B7!='0 & TRN_LH, DELAY(15NS,24NS,35NS), + CHANGED(SBA,0) & TRN_LH, DELAY(8NS,17NS,25NS), + CHANGED(SBA,0) & TRN_HL, DELAY(5NS,13NS,20NS), + CHANGED(GBAR,0) & TRN_ZH, DELAY(3NS,10NS,17NS), + CHANGED(GBAR,0) & TRN_ZL, DELAY(5NS,10NS,20NS), + CHANGED(GBAR,0) & TRN_HZ, DELAY(1NS,6NS,10NS), + CHANGED(GBAR,0) & TRN_LZ, DELAY(2NS,10NS,16NS), + CHANGED(DIR,0) & TRN_ZH, DELAY(10NS,22NS,30NS), + CHANGED(DIR,0) & TRN_ZL, DELAY(5NS,14.5NS,25NS), + CHANGED(DIR,0) & TRN_HZ, DELAY(1NS,6NS,10NS), + CHANGED(DIR,0) & TRN_LZ, DELAY(2NS,10NS,16NS), + DELAY(16NS,25NS,36NS) + ) + } + A8_B = { + CASE( + CHANGED(CBA,0) & TRN_LH & SBA=='1, DELAY(10NS,20NS,30NS), + CHANGED(CBA,0) & TRN_HL & SBA=='1, DELAY(5NS,11NS,17NS), + CHANGED(B8,0) & TRN_LH & SBA!='1, DELAY(5NS,11NS,20NS), + CHANGED(B8,0) & TRN_HL & SBA!='1, DELAY(3NS,7.5NS,12NS), + CHANGED(SBA,0) & B8!='0 & TRN_LH, DELAY(15NS,24NS,35NS), + CHANGED(SBA,0) & TRN_LH, DELAY(8NS,17NS,25NS), + CHANGED(SBA,0) & TRN_HL, DELAY(5NS,13NS,20NS), + CHANGED(GBAR,0) & TRN_ZH, DELAY(3NS,10NS,17NS), + CHANGED(GBAR,0) & TRN_ZL, DELAY(5NS,10NS,20NS), + CHANGED(GBAR,0) & TRN_HZ, DELAY(1NS,6NS,10NS), + CHANGED(GBAR,0) & TRN_LZ, DELAY(2NS,10NS,16NS), + CHANGED(DIR,0) & TRN_ZH, DELAY(10NS,22NS,30NS), + CHANGED(DIR,0) & TRN_ZL, DELAY(5NS,14.5NS,25NS), + CHANGED(DIR,0) & TRN_HZ, DELAY(1NS,6NS,10NS), + CHANGED(DIR,0) & TRN_LZ, DELAY(2NS,10NS,16NS), + DELAY(16NS,25NS,36NS) + ) + } + TRISTATE: + ENABLE HI ENB + B1_B = { + CASE( + CHANGED(CAB,0) & TRN_LH & SAB=='1, DELAY(10NS,20NS,30NS), + CHANGED(CAB,0) & TRN_HL & SAB=='1, DELAY(5NS,11NS,17NS), + CHANGED(A1,0) & TRN_LH & SAB!='1, DELAY(5NS,11NS,20NS), + CHANGED(A1,0) & TRN_HL & SAB!='1, DELAY(3NS,7.5NS,12NS), + CHANGED(SAB,0) & A1!='0 & TRN_LH, DELAY(15NS,24NS,35NS), + CHANGED(SAB,0) & TRN_LH, DELAY(8NS,17NS,25NS), + CHANGED(SAB,0) & TRN_HL, DELAY(5NS,13NS,20NS), + CHANGED(GBAR,0) & TRN_ZH, DELAY(3NS,10NS,17NS), + CHANGED(GBAR,0) & TRN_ZL, DELAY(5NS,10NS,20NS), + CHANGED(GBAR,0) & TRN_HZ, DELAY(1NS,6NS,10NS), + CHANGED(GBAR,0) & TRN_LZ, DELAY(2NS,10NS,16NS), + CHANGED(DIR,0) & TRN_ZH, DELAY(10NS,22NS,30NS), + CHANGED(DIR,0) & TRN_ZL, DELAY(5NS,14.5NS,25NS), + CHANGED(DIR,0) & TRN_HZ, DELAY(1NS,6NS,10NS), + CHANGED(DIR,0) & TRN_LZ, DELAY(2NS,10NS,16NS), + DELAY(16NS,25NS,36NS) + ) + } + B2_B = { + CASE( + CHANGED(CAB,0) & TRN_LH & SAB=='1, DELAY(10NS,20NS,30NS), + CHANGED(CAB,0) & TRN_HL & SAB=='1, DELAY(5NS,11NS,17NS), + CHANGED(A2,0) & TRN_LH & SAB!='1, DELAY(5NS,11NS,20NS), + CHANGED(A2,0) & TRN_HL & SAB!='1, DELAY(3NS,7.5NS,12NS), + CHANGED(SAB,0) & A2!='0 & TRN_LH, DELAY(15NS,24NS,35NS), + CHANGED(SAB,0) & TRN_LH, DELAY(8NS,17NS,25NS), + CHANGED(SAB,0) & TRN_HL, DELAY(5NS,13NS,20NS), + CHANGED(GBAR,0) & TRN_ZH, DELAY(3NS,10NS,17NS), + CHANGED(GBAR,0) & TRN_ZL, DELAY(5NS,10NS,20NS), + CHANGED(GBAR,0) & TRN_HZ, DELAY(1NS,6NS,10NS), + CHANGED(GBAR,0) & TRN_LZ, DELAY(2NS,10NS,16NS), + CHANGED(DIR,0) & TRN_ZH, DELAY(10NS,22NS,30NS), + CHANGED(DIR,0) & TRN_ZL, DELAY(5NS,14.5NS,25NS), + CHANGED(DIR,0) & TRN_HZ, DELAY(1NS,6NS,10NS), + CHANGED(DIR,0) & TRN_LZ, DELAY(2NS,10NS,16NS), + DELAY(16NS,25NS,36NS) + ) + } + B3_B = { + CASE( + CHANGED(CAB,0) & TRN_LH & SAB=='1, DELAY(10NS,20NS,30NS), + CHANGED(CAB,0) & TRN_HL & SAB=='1, DELAY(5NS,11NS,17NS), + CHANGED(A3,0) & TRN_LH & SAB!='1, DELAY(5NS,11NS,20NS), + CHANGED(A3,0) & TRN_HL & SAB!='1, DELAY(3NS,7.5NS,12NS), + CHANGED(SAB,0) & A3!='0 & TRN_LH, DELAY(15NS,24NS,35NS), + CHANGED(SAB,0) & TRN_LH, DELAY(8NS,17NS,25NS), + CHANGED(SAB,0) & TRN_HL, DELAY(5NS,13NS,20NS), + CHANGED(GBAR,0) & TRN_ZH, DELAY(3NS,10NS,17NS), + CHANGED(GBAR,0) & TRN_ZL, DELAY(5NS,10NS,20NS), + CHANGED(GBAR,0) & TRN_HZ, DELAY(1NS,6NS,10NS), + CHANGED(GBAR,0) & TRN_LZ, DELAY(2NS,10NS,16NS), + CHANGED(DIR,0) & TRN_ZH, DELAY(10NS,22NS,30NS), + CHANGED(DIR,0) & TRN_ZL, DELAY(5NS,14.5NS,25NS), + CHANGED(DIR,0) & TRN_HZ, DELAY(1NS,6NS,10NS), + CHANGED(DIR,0) & TRN_LZ, DELAY(2NS,10NS,16NS), + DELAY(16NS,25NS,36NS) + ) + } + B4_B = { + CASE( + CHANGED(CAB,0) & TRN_LH & SAB=='1, DELAY(10NS,20NS,30NS), + CHANGED(CAB,0) & TRN_HL & SAB=='1, DELAY(5NS,11NS,17NS), + CHANGED(A4,0) & TRN_LH & SAB!='1, DELAY(5NS,11NS,20NS), + CHANGED(A4,0) & TRN_HL & SAB!='1, DELAY(3NS,7.5NS,12NS), + CHANGED(SAB,0) & A4!='0 & TRN_LH, DELAY(15NS,24NS,35NS), + CHANGED(SAB,0) & TRN_LH, DELAY(8NS,17NS,25NS), + CHANGED(SAB,0) & TRN_HL, DELAY(5NS,13NS,20NS), + CHANGED(GBAR,0) & TRN_ZH, DELAY(3NS,10NS,17NS), + CHANGED(GBAR,0) & TRN_ZL, DELAY(5NS,10NS,20NS), + CHANGED(GBAR,0) & TRN_HZ, DELAY(1NS,6NS,10NS), + CHANGED(GBAR,0) & TRN_LZ, DELAY(2NS,10NS,16NS), + CHANGED(DIR,0) & TRN_ZH, DELAY(10NS,22NS,30NS), + CHANGED(DIR,0) & TRN_ZL, DELAY(5NS,14.5NS,25NS), + CHANGED(DIR,0) & TRN_HZ, DELAY(1NS,6NS,10NS), + CHANGED(DIR,0) & TRN_LZ, DELAY(2NS,10NS,16NS), + DELAY(16NS,25NS,36NS) + ) + } + B5_B = { + CASE( + CHANGED(CAB,0) & TRN_LH & SAB=='1, DELAY(10NS,20NS,30NS), + CHANGED(CAB,0) & TRN_HL & SAB=='1, DELAY(5NS,11NS,17NS), + CHANGED(A5,0) & TRN_LH & SAB!='1, DELAY(5NS,11NS,20NS), + CHANGED(A5,0) & TRN_HL & SAB!='1, DELAY(3NS,7.5NS,12NS), + CHANGED(SAB,0) & A5!='0 & TRN_LH, DELAY(15NS,24NS,35NS), + CHANGED(SAB,0) & TRN_LH, DELAY(8NS,17NS,25NS), + CHANGED(SAB,0) & TRN_HL, DELAY(5NS,13NS,20NS), + CHANGED(GBAR,0) & TRN_ZH, DELAY(3NS,10NS,17NS), + CHANGED(GBAR,0) & TRN_ZL, DELAY(5NS,10NS,20NS), + CHANGED(GBAR,0) & TRN_HZ, DELAY(1NS,6NS,10NS), + CHANGED(GBAR,0) & TRN_LZ, DELAY(2NS,10NS,16NS), + CHANGED(DIR,0) & TRN_ZH, DELAY(10NS,22NS,30NS), + CHANGED(DIR,0) & TRN_ZL, DELAY(5NS,14.5NS,25NS), + CHANGED(DIR,0) & TRN_HZ, DELAY(1NS,6NS,10NS), + CHANGED(DIR,0) & TRN_LZ, DELAY(2NS,10NS,16NS), + DELAY(16NS,25NS,36NS) + ) + } + B6_B = { + CASE( + CHANGED(CAB,0) & TRN_LH & SAB=='1, DELAY(10NS,20NS,30NS), + CHANGED(CAB,0) & TRN_HL & SAB=='1, DELAY(5NS,11NS,17NS), + CHANGED(A6,0) & TRN_LH & SAB!='1, DELAY(5NS,11NS,20NS), + CHANGED(A6,0) & TRN_HL & SAB!='1, DELAY(3NS,7.5NS,12NS), + CHANGED(SAB,0) & A6!='0 & TRN_LH, DELAY(15NS,24NS,35NS), + CHANGED(SAB,0) & TRN_LH, DELAY(8NS,17NS,25NS), + CHANGED(SAB,0) & TRN_HL, DELAY(5NS,13NS,20NS), + CHANGED(GBAR,0) & TRN_ZH, DELAY(3NS,10NS,17NS), + CHANGED(GBAR,0) & TRN_ZL, DELAY(5NS,10NS,20NS), + CHANGED(GBAR,0) & TRN_HZ, DELAY(1NS,6NS,10NS), + CHANGED(GBAR,0) & TRN_LZ, DELAY(2NS,10NS,16NS), + CHANGED(DIR,0) & TRN_ZH, DELAY(10NS,22NS,30NS), + CHANGED(DIR,0) & TRN_ZL, DELAY(5NS,14.5NS,25NS), + CHANGED(DIR,0) & TRN_HZ, DELAY(1NS,6NS,10NS), + CHANGED(DIR,0) & TRN_LZ, DELAY(2NS,10NS,16NS), + DELAY(16NS,25NS,36NS) + ) + } + B7_B = { + CASE( + CHANGED(CAB,0) & TRN_LH & SAB=='1, DELAY(10NS,20NS,30NS), + CHANGED(CAB,0) & TRN_HL & SAB=='1, DELAY(5NS,11NS,17NS), + CHANGED(A7,0) & TRN_LH & SAB!='1, DELAY(5NS,11NS,20NS), + CHANGED(A7,0) & TRN_HL & SAB!='1, DELAY(3NS,7.5NS,12NS), + CHANGED(SAB,0) & A7!='0 & TRN_LH, DELAY(15NS,24NS,35NS), + CHANGED(SAB,0) & TRN_LH, DELAY(8NS,17NS,25NS), + CHANGED(SAB,0) & TRN_HL, DELAY(5NS,13NS,20NS), + CHANGED(GBAR,0) & TRN_ZH, DELAY(3NS,10NS,17NS), + CHANGED(GBAR,0) & TRN_ZL, DELAY(5NS,10NS,20NS), + CHANGED(GBAR,0) & TRN_HZ, DELAY(1NS,6NS,10NS), + CHANGED(GBAR,0) & TRN_LZ, DELAY(2NS,10NS,16NS), + CHANGED(DIR,0) & TRN_ZH, DELAY(10NS,22NS,30NS), + CHANGED(DIR,0) & TRN_ZL, DELAY(5NS,14.5NS,25NS), + CHANGED(DIR,0) & TRN_HZ, DELAY(1NS,6NS,10NS), + CHANGED(DIR,0) & TRN_LZ, DELAY(2NS,10NS,16NS), + DELAY(16NS,25NS,36NS) + ) + } + B8_B = { + CASE( + CHANGED(CAB,0) & TRN_LH & SAB=='1, DELAY(10NS,20NS,30NS), + CHANGED(CAB,0) & TRN_HL & SAB=='1, DELAY(5NS,11NS,17NS), + CHANGED(A8,0) & TRN_LH & SAB!='1, DELAY(5NS,11NS,20NS), + CHANGED(A8,0) & TRN_HL & SAB!='1, DELAY(3NS,7.5NS,12NS), + CHANGED(SAB,0) & A8!='0 & TRN_LH, DELAY(15NS,24NS,35NS), + CHANGED(SAB,0) & TRN_LH, DELAY(8NS,17NS,25NS), + CHANGED(SAB,0) & TRN_HL, DELAY(5NS,13NS,20NS), + CHANGED(GBAR,0) & TRN_ZH, DELAY(3NS,10NS,17NS), + CHANGED(GBAR,0) & TRN_ZL, DELAY(5NS,10NS,20NS), + CHANGED(GBAR,0) & TRN_HZ, DELAY(1NS,6NS,10NS), + CHANGED(GBAR,0) & TRN_LZ, DELAY(2NS,10NS,16NS), + CHANGED(DIR,0) & TRN_ZH, DELAY(10NS,22NS,30NS), + CHANGED(DIR,0) & TRN_ZL, DELAY(5NS,14.5NS,25NS), + CHANGED(DIR,0) & TRN_HZ, DELAY(1NS,6NS,10NS), + CHANGED(DIR,0) & TRN_LZ, DELAY(2NS,10NS,16NS), + DELAY(16NS,25NS,36NS) + ) + } + FREQ: + NODE = CAB + MAXFREQ = 40MEG + FREQ: + NODE = CBA + MAXFREQ = 40MEG + WIDTH: + NODE = CAB + MIN_HI = 12.5NS + MIN_LO = 12.5NS + WIDTH: + NODE = CBA + MIN_HI = 12.5NS + MIN_LO = 12.5NS + SETUP_HOLD: + DATA(8) = A1 A2 A3 A4 A5 A6 A7 A8 + CLOCK LH = CAB + SETUPTIME = 10NS + WHEN = { DIR!='0 } + SETUP_HOLD: + DATA(8) = B1 B2 B3 B4 B5 B6 B7 B8 + CLOCK LH = CBA + SETUPTIME = 10NS + WHEN = { DIR!='1 } * .ENDS * *$ *--------- * 74ALS648 OCTAL BUS TRANSCEIVER/REGISTER WITH 3-STATE OUTPUTS * * ALS/AS Logic Data Book, 1986, TI * JSW 9/7/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74ALS648 GBAR_I DIR_I CBA_I SBA_I CAB_I SAB_I + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UALS648LOG1 LOGICEXP(38,40) DPWR DGND + GBAR_I DIR_I CBA_I SBA_I CAB_I SAB_I + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + QA1 QA2 QA3 QA4 QA5 QA6 QA7 QA8 + QB1 QB2 QB3 QB4 QB5 QB6 QB7 QB8 + GBAR DIR CBA SBA CAB SAB + A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 + A1_OUT A2_OUT A3_OUT A4_OUT A5_OUT A6_OUT A7_OUT A8_OUT + B1_OUT B2_OUT B3_OUT B4_OUT B5_OUT B6_OUT B7_OUT B8_OUT + ENA ENB + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} + LOGIC: + GBAR = { GBAR_I } + DIR = { DIR_I } + CBA = { CBA_I } + SBA = { SBA_I } + SBABAR = { ~SBA } + CAB = { CAB_I } + SAB = { SAB_I } + SABBAR = { ~SAB } + ENA = { ~DIR & ~GBAR } + ENB = { DIR & ~GBAR } + A1 = { A1_B } + B1 = { B1_B } + A2 = { A2_B } + B2 = { B2_B } + A3 = { A3_B } + B3 = { B3_B } + A4 = { A4_B } + B4 = { B4_B } + A5 = { A5_B } + B5 = { B5_B } + A6 = { A6_B } + B6 = { B6_B } + A7 = { A7_B } + B7 = { B7_B } + A8 = { A8_B } + B8 = { B8_B } + A1_OUT = { ~((B1 & SBABAR) | (SBA & QB1)) } + B1_OUT = { ~((A1 & SABBAR) | (SAB & QA1)) } + A2_OUT = { ~((B2 & SBABAR) | (SBA & QB2)) } + B2_OUT = { ~((A2 & SABBAR) | (SAB & QA2)) } + A3_OUT = { ~((B3 & SBABAR) | (SBA & QB3)) } + B3_OUT = { ~((A3 & SABBAR) | (SAB & QA3)) } + A4_OUT = { ~((B4 & SBABAR) | (SBA & QB4)) } + B4_OUT = { ~((A4 & SABBAR) | (SAB & QA4)) } + A5_OUT = { ~((B5 & SBABAR) | (SBA & QB5)) } + B5_OUT = { ~((A5 & SABBAR) | (SAB & QA5)) } + A6_OUT = { ~((B6 & SBABAR) | (SBA & QB6)) } + B6_OUT = { ~((A6 & SABBAR) | (SAB & QA6)) } + A7_OUT = { ~((B7 & SBABAR) | (SBA & QB7)) } + B7_OUT = { ~((A7 & SABBAR) | (SAB & QA7)) } + A8_OUT = { ~((B8 & SBABAR) | (SBA & QB8)) } + B8_OUT = { ~((A8 & SABBAR) | (SAB & QA8)) } * UAREG DFF(8) DPWR DGND $D_HI $D_HI CAB + A1 A2 A3 A4 A5 A6 A7 A8 + QA1 QA2 QA3 QA4 QA5 QA6 QA7 QA8 + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D0_EFF IO_ALS00 * UBREG DFF(8) DPWR DGND $D_HI $D_HI CBA + B1 B2 B3 B4 B5 B6 B7 B8 + QB1 QB2 QB3 QB4 QB5 QB6 QB7 QB8 + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D0_EFF IO_ALS00 * UALS648DLY PINDLY (16,2,23) DPWR DGND + A1_OUT A2_OUT A3_OUT A4_OUT A5_OUT A6_OUT A7_OUT A8_OUT B1_OUT B2_OUT B3_OUT B4_OUT B5_OUT B6_OUT B7_OUT B8_OUT + ENA ENB + A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 CAB CBA SAB SBA GBAR DIR DIR + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + IO_ALS00 + MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + TRISTATE: + ENABLE HI ENA + A1_B = { + CASE( + CHANGED(CBA,0) & TRN_LH & SBA=='1, DELAY(8NS,21NS,33NS), + CHANGED(CBA,0) & TRN_HL & SBA=='1, DELAY(5NS,13NS,20NS), + CHANGED(B1,0) & TRN_LH & SBA!='1, DELAY(3NS,10NS,17NS), + CHANGED(B1,0) & TRN_HL & SBA!='1, DELAY(2NS,6NS,10NS), + CHANGED(SBA,0) & B1!='0 & TRN_LH, DELAY(5NS,24NS,39NS), + CHANGED(SBA,0) & B1!='0 & TRN_HL, DELAY(4NS,15NS,22NS), + CHANGED(SBA,0) & TRN_LH, DELAY(6NS,16NS,25NS), + CHANGED(SBA,0) & TRN_HL, DELAY(6NS,14NS,21NS), + CHANGED(GBAR,0) & TRN_ZH, DELAY(4NS,12NS,22NS), + CHANGED(GBAR,0) & TRN_ZL, DELAY(4NS,12NS,22NS), + CHANGED(GBAR,0) & TRN_HZ, DELAY(1NS,5NS,10NS), + CHANGED(GBAR,0) & TRN_LZ, DELAY(2NS,7NS,15NS), + CHANGED(DIR,0) & TRN_ZH, DELAY(4NS,14NS,27NS), + CHANGED(DIR,0) & TRN_ZL, DELAY(3NS,10NS,19NS), + CHANGED(DIR,0) & TRN_HZ, DELAY(1NS,7NS,14NS), + CHANGED(DIR,0) & TRN_LZ, DELAY(2NS,7NS,15NS), + DELAY(9NS,25NS,40NS) + ) + } + A2_B = { + CASE( + CHANGED(CBA,0) & TRN_LH & SBA=='1, DELAY(8NS,21NS,33NS), + CHANGED(CBA,0) & TRN_HL & SBA=='1, DELAY(5NS,13NS,20NS), + CHANGED(B2,0) & TRN_LH & SBA!='1, DELAY(3NS,10NS,17NS), + CHANGED(B2,0) & TRN_HL & SBA!='1, DELAY(2NS,6NS,10NS), + CHANGED(SBA,0) & B2!='0 & TRN_LH, DELAY(5NS,24NS,39NS), + CHANGED(SBA,0) & B2!='0 & TRN_HL, DELAY(4NS,15NS,22NS), + CHANGED(SBA,0) & TRN_LH, DELAY(6NS,16NS,25NS), + CHANGED(SBA,0) & TRN_HL, DELAY(6NS,14NS,21NS), + CHANGED(GBAR,0) & TRN_ZH, DELAY(4NS,12NS,22NS), + CHANGED(GBAR,0) & TRN_ZL, DELAY(4NS,12NS,22NS), + CHANGED(GBAR,0) & TRN_HZ, DELAY(1NS,5NS,10NS), + CHANGED(GBAR,0) & TRN_LZ, DELAY(2NS,7NS,15NS), + CHANGED(DIR,0) & TRN_ZH, DELAY(4NS,14NS,27NS), + CHANGED(DIR,0) & TRN_ZL, DELAY(3NS,10NS,19NS), + CHANGED(DIR,0) & TRN_HZ, DELAY(1NS,7NS,14NS), + CHANGED(DIR,0) & TRN_LZ, DELAY(2NS,7NS,15NS), + DELAY(9NS,25NS,40NS) + ) + } + A3_B = { + CASE( + CHANGED(CBA,0) & TRN_LH & SBA=='1, DELAY(8NS,21NS,33NS), + CHANGED(CBA,0) & TRN_HL & SBA=='1, DELAY(5NS,13NS,20NS), + CHANGED(B3,0) & TRN_LH & SBA!='1, DELAY(3NS,10NS,17NS), + CHANGED(B3,0) & TRN_HL & SBA!='1, DELAY(2NS,6NS,10NS), + CHANGED(SBA,0) & B3!='0 & TRN_LH, DELAY(5NS,24NS,39NS), + CHANGED(SBA,0) & B3!='0 & TRN_HL, DELAY(4NS,15NS,22NS), + CHANGED(SBA,0) & TRN_LH, DELAY(6NS,16NS,25NS), + CHANGED(SBA,0) & TRN_HL, DELAY(6NS,14NS,21NS), + CHANGED(GBAR,0) & TRN_ZH, DELAY(4NS,12NS,22NS), + CHANGED(GBAR,0) & TRN_ZL, DELAY(4NS,12NS,22NS), + CHANGED(GBAR,0) & TRN_HZ, DELAY(1NS,5NS,10NS), + CHANGED(GBAR,0) & TRN_LZ, DELAY(2NS,7NS,15NS), + CHANGED(DIR,0) & TRN_ZH, DELAY(4NS,14NS,27NS), + CHANGED(DIR,0) & TRN_ZL, DELAY(3NS,10NS,19NS), + CHANGED(DIR,0) & TRN_HZ, DELAY(1NS,7NS,14NS), + CHANGED(DIR,0) & TRN_LZ, DELAY(2NS,7NS,15NS), + DELAY(9NS,25NS,40NS) + ) + } + A4_B = { + CASE( + CHANGED(CBA,0) & TRN_LH & SBA=='1, DELAY(8NS,21NS,33NS), + CHANGED(CBA,0) & TRN_HL & SBA=='1, DELAY(5NS,13NS,20NS), + CHANGED(B4,0) & TRN_LH & SBA!='1, DELAY(3NS,10NS,17NS), + CHANGED(B4,0) & TRN_HL & SBA!='1, DELAY(2NS,6NS,10NS), + CHANGED(SBA,0) & B4!='0 & TRN_LH, DELAY(5NS,24NS,39NS), + CHANGED(SBA,0) & B4!='0 & TRN_HL, DELAY(4NS,15NS,22NS), + CHANGED(SBA,0) & TRN_LH, DELAY(6NS,16NS,25NS), + CHANGED(SBA,0) & TRN_HL, DELAY(6NS,14NS,21NS), + CHANGED(GBAR,0) & TRN_ZH, DELAY(4NS,12NS,22NS), + CHANGED(GBAR,0) & TRN_ZL, DELAY(4NS,12NS,22NS), + CHANGED(GBAR,0) & TRN_HZ, DELAY(1NS,5NS,10NS), + CHANGED(GBAR,0) & TRN_LZ, DELAY(2NS,7NS,15NS), + CHANGED(DIR,0) & TRN_ZH, DELAY(4NS,14NS,27NS), + CHANGED(DIR,0) & TRN_ZL, DELAY(3NS,10NS,19NS), + CHANGED(DIR,0) & TRN_HZ, DELAY(1NS,7NS,14NS), + CHANGED(DIR,0) & TRN_LZ, DELAY(2NS,7NS,15NS), + DELAY(9NS,25NS,40NS) + ) + } + A5_B = { + CASE( + CHANGED(CBA,0) & TRN_LH & SBA=='1, DELAY(8NS,21NS,33NS), + CHANGED(CBA,0) & TRN_HL & SBA=='1, DELAY(5NS,13NS,20NS), + CHANGED(B5,0) & TRN_LH & SBA!='1, DELAY(3NS,10NS,17NS), + CHANGED(B5,0) & TRN_HL & SBA!='1, DELAY(2NS,6NS,10NS), + CHANGED(SBA,0) & B5!='0 & TRN_LH, DELAY(5NS,24NS,39NS), + CHANGED(SBA,0) & B5!='0 & TRN_HL, DELAY(4NS,15NS,22NS), + CHANGED(SBA,0) & TRN_LH, DELAY(6NS,16NS,25NS), + CHANGED(SBA,0) & TRN_HL, DELAY(6NS,14NS,21NS), + CHANGED(GBAR,0) & TRN_ZH, DELAY(4NS,12NS,22NS), + CHANGED(GBAR,0) & TRN_ZL, DELAY(4NS,12NS,22NS), + CHANGED(GBAR,0) & TRN_HZ, DELAY(1NS,5NS,10NS), + CHANGED(GBAR,0) & TRN_LZ, DELAY(2NS,7NS,15NS), + CHANGED(DIR,0) & TRN_ZH, DELAY(4NS,14NS,27NS), + CHANGED(DIR,0) & TRN_ZL, DELAY(3NS,10NS,19NS), + CHANGED(DIR,0) & TRN_HZ, DELAY(1NS,7NS,14NS), + CHANGED(DIR,0) & TRN_LZ, DELAY(2NS,7NS,15NS), + DELAY(9NS,25NS,40NS) + ) + } + A6_B = { + CASE( + CHANGED(CBA,0) & TRN_LH & SBA=='1, DELAY(8NS,21NS,33NS), + CHANGED(CBA,0) & TRN_HL & SBA=='1, DELAY(5NS,13NS,20NS), + CHANGED(B6,0) & TRN_LH & SBA!='1, DELAY(3NS,10NS,17NS), + CHANGED(B6,0) & TRN_HL & SBA!='1, DELAY(2NS,6NS,10NS), + CHANGED(SBA,0) & B6!='0 & TRN_LH, DELAY(5NS,24NS,39NS), + CHANGED(SBA,0) & B6!='0 & TRN_HL, DELAY(4NS,15NS,22NS), + CHANGED(SBA,0) & TRN_LH, DELAY(6NS,16NS,25NS), + CHANGED(SBA,0) & TRN_HL, DELAY(6NS,14NS,21NS), + CHANGED(GBAR,0) & TRN_ZH, DELAY(4NS,12NS,22NS), + CHANGED(GBAR,0) & TRN_ZL, DELAY(4NS,12NS,22NS), + CHANGED(GBAR,0) & TRN_HZ, DELAY(1NS,5NS,10NS), + CHANGED(GBAR,0) & TRN_LZ, DELAY(2NS,7NS,15NS), + CHANGED(DIR,0) & TRN_ZH, DELAY(4NS,14NS,27NS), + CHANGED(DIR,0) & TRN_ZL, DELAY(3NS,10NS,19NS), + CHANGED(DIR,0) & TRN_HZ, DELAY(1NS,7NS,14NS), + CHANGED(DIR,0) & TRN_LZ, DELAY(2NS,7NS,15NS), + DELAY(9NS,25NS,40NS) + ) + } + A7_B = { + CASE( + CHANGED(CBA,0) & TRN_LH & SBA=='1, DELAY(8NS,21NS,33NS), + CHANGED(CBA,0) & TRN_HL & SBA=='1, DELAY(5NS,13NS,20NS), + CHANGED(B7,0) & TRN_LH & SBA!='1, DELAY(3NS,10NS,17NS), + CHANGED(B7,0) & TRN_HL & SBA!='1, DELAY(2NS,6NS,10NS), + CHANGED(SBA,0) & B7!='0 & TRN_LH, DELAY(5NS,24NS,39NS), + CHANGED(SBA,0) & B7!='0 & TRN_HL, DELAY(4NS,15NS,22NS), + CHANGED(SBA,0) & TRN_LH, DELAY(6NS,16NS,25NS), + CHANGED(SBA,0) & TRN_HL, DELAY(6NS,14NS,21NS), + CHANGED(GBAR,0) & TRN_ZH, DELAY(4NS,12NS,22NS), + CHANGED(GBAR,0) & TRN_ZL, DELAY(4NS,12NS,22NS), + CHANGED(GBAR,0) & TRN_HZ, DELAY(1NS,5NS,10NS), + CHANGED(GBAR,0) & TRN_LZ, DELAY(2NS,7NS,15NS), + CHANGED(DIR,0) & TRN_ZH, DELAY(4NS,14NS,27NS), + CHANGED(DIR,0) & TRN_ZL, DELAY(3NS,10NS,19NS), + CHANGED(DIR,0) & TRN_HZ, DELAY(1NS,7NS,14NS), + CHANGED(DIR,0) & TRN_LZ, DELAY(2NS,7NS,15NS), + DELAY(9NS,25NS,40NS) + ) + } + A8_B = { + CASE( + CHANGED(CBA,0) & TRN_LH & SBA=='1, DELAY(8NS,21NS,33NS), + CHANGED(CBA,0) & TRN_HL & SBA=='1, DELAY(5NS,13NS,20NS), + CHANGED(B8,0) & TRN_LH & SBA!='1, DELAY(3NS,10NS,17NS), + CHANGED(B8,0) & TRN_HL & SBA!='1, DELAY(2NS,6NS,10NS), + CHANGED(SBA,0) & B8!='0 & TRN_LH, DELAY(5NS,24NS,39NS), + CHANGED(SBA,0) & B8!='0 & TRN_HL, DELAY(4NS,15NS,22NS), + CHANGED(SBA,0) & TRN_LH, DELAY(6NS,16NS,25NS), + CHANGED(SBA,0) & TRN_HL, DELAY(6NS,14NS,21NS), + CHANGED(GBAR,0) & TRN_ZH, DELAY(4NS,12NS,22NS), + CHANGED(GBAR,0) & TRN_ZL, DELAY(4NS,12NS,22NS), + CHANGED(GBAR,0) & TRN_HZ, DELAY(1NS,5NS,10NS), + CHANGED(GBAR,0) & TRN_LZ, DELAY(2NS,7NS,15NS), + CHANGED(DIR,0) & TRN_ZH, DELAY(4NS,14NS,27NS), + CHANGED(DIR,0) & TRN_ZL, DELAY(3NS,10NS,19NS), + CHANGED(DIR,0) & TRN_HZ, DELAY(1NS,7NS,14NS), + CHANGED(DIR,0) & TRN_LZ, DELAY(2NS,7NS,15NS), + DELAY(9NS,25NS,40NS) + ) + } + TRISTATE: + ENABLE HI ENB + B1_B = { + CASE( + CHANGED(CAB,0) & TRN_LH & SAB=='1, DELAY(8NS,21NS,33NS), + CHANGED(CAB,0) & TRN_HL & SAB=='1, DELAY(5NS,13NS,20NS), + CHANGED(A1,0) & TRN_LH & SAB!='1, DELAY(3NS,10NS,17NS), + CHANGED(A1,0) & TRN_HL & SAB!='1, DELAY(2NS,6NS,10NS), + CHANGED(SAB,0) & A1!='0 & TRN_LH, DELAY(5NS,24NS,39NS), + CHANGED(SAB,0) & A1!='0 & TRN_HL, DELAY(4NS,15NS,22NS), + CHANGED(SAB,0) & TRN_LH, DELAY(6NS,16NS,25NS), + CHANGED(SAB,0) & TRN_HL, DELAY(6NS,14NS,21NS), + CHANGED(GBAR,0) & TRN_ZH, DELAY(4NS,12NS,22NS), + CHANGED(GBAR,0) & TRN_ZL, DELAY(4NS,12NS,22NS), + CHANGED(GBAR,0) & TRN_HZ, DELAY(1NS,5NS,10NS), + CHANGED(GBAR,0) & TRN_LZ, DELAY(2NS,7NS,15NS), + CHANGED(DIR,0) & TRN_ZH, DELAY(4NS,14NS,27NS), + CHANGED(DIR,0) & TRN_ZL, DELAY(3NS,10NS,19NS), + CHANGED(DIR,0) & TRN_HZ, DELAY(1NS,7NS,14NS), + CHANGED(DIR,0) & TRN_LZ, DELAY(2NS,7NS,15NS), + DELAY(9NS,25NS,40NS) + ) + } + B2_B = { + CASE( + CHANGED(CAB,0) & TRN_LH & SAB=='1, DELAY(8NS,21NS,33NS), + CHANGED(CAB,0) & TRN_HL & SAB=='1, DELAY(5NS,13NS,20NS), + CHANGED(A2,0) & TRN_LH & SAB!='1, DELAY(3NS,10NS,17NS), + CHANGED(A2,0) & TRN_HL & SAB!='1, DELAY(2NS,6NS,10NS), + CHANGED(SAB,0) & A2!='0 & TRN_LH, DELAY(5NS,24NS,39NS), + CHANGED(SAB,0) & A2!='0 & TRN_HL, DELAY(4NS,15NS,22NS), + CHANGED(SAB,0) & TRN_LH, DELAY(6NS,16NS,25NS), + CHANGED(SAB,0) & TRN_HL, DELAY(6NS,14NS,21NS), + CHANGED(GBAR,0) & TRN_ZH, DELAY(4NS,12NS,22NS), + CHANGED(GBAR,0) & TRN_ZL, DELAY(4NS,12NS,22NS), + CHANGED(GBAR,0) & TRN_HZ, DELAY(1NS,5NS,10NS), + CHANGED(GBAR,0) & TRN_LZ, DELAY(2NS,7NS,15NS), + CHANGED(DIR,0) & TRN_ZH, DELAY(4NS,14NS,27NS), + CHANGED(DIR,0) & TRN_ZL, DELAY(3NS,10NS,19NS), + CHANGED(DIR,0) & TRN_HZ, DELAY(1NS,7NS,14NS), + CHANGED(DIR,0) & TRN_LZ, DELAY(2NS,7NS,15NS), + DELAY(9NS,25NS,40NS) + ) + } + B3_B = { + CASE( + CHANGED(CAB,0) & TRN_LH & SAB=='1, DELAY(8NS,21NS,33NS), + CHANGED(CAB,0) & TRN_HL & SAB=='1, DELAY(5NS,13NS,20NS), + CHANGED(A3,0) & TRN_LH & SAB!='1, DELAY(3NS,10NS,17NS), + CHANGED(A3,0) & TRN_HL & SAB!='1, DELAY(2NS,6NS,10NS), + CHANGED(SAB,0) & A3!='0 & TRN_LH, DELAY(5NS,24NS,39NS), + CHANGED(SAB,0) & A3!='0 & TRN_HL, DELAY(4NS,15NS,22NS), + CHANGED(SAB,0) & TRN_LH, DELAY(6NS,16NS,25NS), + CHANGED(SAB,0) & TRN_HL, DELAY(6NS,14NS,21NS), + CHANGED(GBAR,0) & TRN_ZH, DELAY(4NS,12NS,22NS), + CHANGED(GBAR,0) & TRN_ZL, DELAY(4NS,12NS,22NS), + CHANGED(GBAR,0) & TRN_HZ, DELAY(1NS,5NS,10NS), + CHANGED(GBAR,0) & TRN_LZ, DELAY(2NS,7NS,15NS), + CHANGED(DIR,0) & TRN_ZH, DELAY(4NS,14NS,27NS), + CHANGED(DIR,0) & TRN_ZL, DELAY(3NS,10NS,19NS), + CHANGED(DIR,0) & TRN_HZ, DELAY(1NS,7NS,14NS), + CHANGED(DIR,0) & TRN_LZ, DELAY(2NS,7NS,15NS), + DELAY(9NS,25NS,40NS) + ) + } + B4_B = { + CASE( + CHANGED(CAB,0) & TRN_LH & SAB=='1, DELAY(8NS,21NS,33NS), + CHANGED(CAB,0) & TRN_HL & SAB=='1, DELAY(5NS,13NS,20NS), + CHANGED(A4,0) & TRN_LH & SAB!='1, DELAY(3NS,10NS,17NS), + CHANGED(A4,0) & TRN_HL & SAB!='1, DELAY(2NS,6NS,10NS), + CHANGED(SAB,0) & A4!='0 & TRN_LH, DELAY(5NS,24NS,39NS), + CHANGED(SAB,0) & A4!='0 & TRN_HL, DELAY(4NS,15NS,22NS), + CHANGED(SAB,0) & TRN_LH, DELAY(6NS,16NS,25NS), + CHANGED(SAB,0) & TRN_HL, DELAY(6NS,14NS,21NS), + CHANGED(GBAR,0) & TRN_ZH, DELAY(4NS,12NS,22NS), + CHANGED(GBAR,0) & TRN_ZL, DELAY(4NS,12NS,22NS), + CHANGED(GBAR,0) & TRN_HZ, DELAY(1NS,5NS,10NS), + CHANGED(GBAR,0) & TRN_LZ, DELAY(2NS,7NS,15NS), + CHANGED(DIR,0) & TRN_ZH, DELAY(4NS,14NS,27NS), + CHANGED(DIR,0) & TRN_ZL, DELAY(3NS,10NS,19NS), + CHANGED(DIR,0) & TRN_HZ, DELAY(1NS,7NS,14NS), + CHANGED(DIR,0) & TRN_LZ, DELAY(2NS,7NS,15NS), + DELAY(9NS,25NS,40NS) + ) + } + B5_B = { + CASE( + CHANGED(CAB,0) & TRN_LH & SAB=='1, DELAY(8NS,21NS,33NS), + CHANGED(CAB,0) & TRN_HL & SAB=='1, DELAY(5NS,13NS,20NS), + CHANGED(A5,0) & TRN_LH & SAB!='1, DELAY(3NS,10NS,17NS), + CHANGED(A5,0) & TRN_HL & SAB!='1, DELAY(2NS,6NS,10NS), + CHANGED(SAB,0) & A5!='0 & TRN_LH, DELAY(5NS,24NS,39NS), + CHANGED(SAB,0) & A5!='0 & TRN_HL, DELAY(4NS,15NS,22NS), + CHANGED(SAB,0) & TRN_LH, DELAY(6NS,16NS,25NS), + CHANGED(SAB,0) & TRN_HL, DELAY(6NS,14NS,21NS), + CHANGED(GBAR,0) & TRN_ZH, DELAY(4NS,12NS,22NS), + CHANGED(GBAR,0) & TRN_ZL, DELAY(4NS,12NS,22NS), + CHANGED(GBAR,0) & TRN_HZ, DELAY(1NS,5NS,10NS), + CHANGED(GBAR,0) & TRN_LZ, DELAY(2NS,7NS,15NS), + CHANGED(DIR,0) & TRN_ZH, DELAY(4NS,14NS,27NS), + CHANGED(DIR,0) & TRN_ZL, DELAY(3NS,10NS,19NS), + CHANGED(DIR,0) & TRN_HZ, DELAY(1NS,7NS,14NS), + CHANGED(DIR,0) & TRN_LZ, DELAY(2NS,7NS,15NS), + DELAY(9NS,25NS,40NS) + ) + } + B6_B = { + CASE( + CHANGED(CAB,0) & TRN_LH & SAB=='1, DELAY(8NS,21NS,33NS), + CHANGED(CAB,0) & TRN_HL & SAB=='1, DELAY(5NS,13NS,20NS), + CHANGED(A6,0) & TRN_LH & SAB!='1, DELAY(3NS,10NS,17NS), + CHANGED(A6,0) & TRN_HL & SAB!='1, DELAY(2NS,6NS,10NS), + CHANGED(SAB,0) & A6!='0 & TRN_LH, DELAY(5NS,24NS,39NS), + CHANGED(SAB,0) & A6!='0 & TRN_HL, DELAY(4NS,15NS,22NS), + CHANGED(SAB,0) & TRN_LH, DELAY(6NS,16NS,25NS), + CHANGED(SAB,0) & TRN_HL, DELAY(6NS,14NS,21NS), + CHANGED(GBAR,0) & TRN_ZH, DELAY(4NS,12NS,22NS), + CHANGED(GBAR,0) & TRN_ZL, DELAY(4NS,12NS,22NS), + CHANGED(GBAR,0) & TRN_HZ, DELAY(1NS,5NS,10NS), + CHANGED(GBAR,0) & TRN_LZ, DELAY(2NS,7NS,15NS), + CHANGED(DIR,0) & TRN_ZH, DELAY(4NS,14NS,27NS), + CHANGED(DIR,0) & TRN_ZL, DELAY(3NS,10NS,19NS), + CHANGED(DIR,0) & TRN_HZ, DELAY(1NS,7NS,14NS), + CHANGED(DIR,0) & TRN_LZ, DELAY(2NS,7NS,15NS), + DELAY(9NS,25NS,40NS) + ) + } + B7_B = { + CASE( + CHANGED(CAB,0) & TRN_LH & SAB=='1, DELAY(8NS,21NS,33NS), + CHANGED(CAB,0) & TRN_HL & SAB=='1, DELAY(5NS,13NS,20NS), + CHANGED(A7,0) & TRN_LH & SAB!='1, DELAY(3NS,10NS,17NS), + CHANGED(A7,0) & TRN_HL & SAB!='1, DELAY(2NS,6NS,10NS), + CHANGED(SAB,0) & A7!='0 & TRN_LH, DELAY(5NS,24NS,39NS), + CHANGED(SAB,0) & A7!='0 & TRN_HL, DELAY(4NS,15NS,22NS), + CHANGED(SAB,0) & TRN_LH, DELAY(6NS,16NS,25NS), + CHANGED(SAB,0) & TRN_HL, DELAY(6NS,14NS,21NS), + CHANGED(GBAR,0) & TRN_ZH, DELAY(4NS,12NS,22NS), + CHANGED(GBAR,0) & TRN_ZL, DELAY(4NS,12NS,22NS), + CHANGED(GBAR,0) & TRN_HZ, DELAY(1NS,5NS,10NS), + CHANGED(GBAR,0) & TRN_LZ, DELAY(2NS,7NS,15NS), + CHANGED(DIR,0) & TRN_ZH, DELAY(4NS,14NS,27NS), + CHANGED(DIR,0) & TRN_ZL, DELAY(3NS,10NS,19NS), + CHANGED(DIR,0) & TRN_HZ, DELAY(1NS,7NS,14NS), + CHANGED(DIR,0) & TRN_LZ, DELAY(2NS,7NS,15NS), + DELAY(9NS,25NS,40NS) + ) + } + B8_B = { + CASE( + CHANGED(CAB,0) & TRN_LH & SAB=='1, DELAY(8NS,21NS,33NS), + CHANGED(CAB,0) & TRN_HL & SAB=='1, DELAY(5NS,13NS,20NS), + CHANGED(A8,0) & TRN_LH & SAB!='1, DELAY(3NS,10NS,17NS), + CHANGED(A8,0) & TRN_HL & SAB!='1, DELAY(2NS,6NS,10NS), + CHANGED(SAB,0) & A8!='0 & TRN_LH, DELAY(5NS,24NS,39NS), + CHANGED(SAB,0) & A8!='0 & TRN_HL, DELAY(4NS,15NS,22NS), + CHANGED(SAB,0) & TRN_LH, DELAY(6NS,16NS,25NS), + CHANGED(SAB,0) & TRN_HL, DELAY(6NS,14NS,21NS), + CHANGED(GBAR,0) & TRN_ZH, DELAY(4NS,12NS,22NS), + CHANGED(GBAR,0) & TRN_ZL, DELAY(4NS,12NS,22NS), + CHANGED(GBAR,0) & TRN_HZ, DELAY(1NS,5NS,10NS), + CHANGED(GBAR,0) & TRN_LZ, DELAY(2NS,7NS,15NS), + CHANGED(DIR,0) & TRN_ZH, DELAY(4NS,14NS,27NS), + CHANGED(DIR,0) & TRN_ZL, DELAY(3NS,10NS,19NS), + CHANGED(DIR,0) & TRN_HZ, DELAY(1NS,7NS,14NS), + CHANGED(DIR,0) & TRN_LZ, DELAY(2NS,7NS,15NS), + DELAY(9NS,25NS,40NS) + ) + } + FREQ: + NODE = CAB + MAXFREQ = 40MEG + FREQ: + NODE = CBA + MAXFREQ = 40MEG + WIDTH: + NODE = CAB + MIN_HI = 12.5NS + MIN_LO = 12.5NS + WIDTH: + NODE = CBA + MIN_HI = 12.5NS + MIN_LO = 12.5NS + SETUP_HOLD: + DATA(8) = A1 A2 A3 A4 A5 A6 A7 A8 + CLOCK LH = CAB + SETUPTIME = 10NS + WHEN = { DIR!='0 } + SETUP_HOLD: + DATA(8) = B1 B2 B3 B4 B5 B6 B7 B8 + CLOCK LH = CBA + SETUPTIME = 10NS + WHEN = { DIR!='1 } * .ENDS * *$ *------------------------------------------------------------------------- * 74ALS651 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH INVERTED 3-STATE OUTPUTS * * ALS/AS LOGIC DATA BOOK, 1986, TI * JSW 09/10/92 REMODELED USING LOGICEXP, PINDLY, & CONSTRAINT DEVICES * * NOTE: ADDITIONAL LOGIC WAS ADDED TO MODEL THE BIDIRECTIONAL PINS OF THIS * DEVICE. * .SUBCKT 74ALS651 GBABAR_I GAB_I CBA_I SBA_I CAB_I SAB_I A1_B A2_B A3_B A4_B + A5_B A6_B A7_B A8_B B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 DFF(8) DPWR DGND $D_HI $D_HI CAB + A1_IO A2_IO A3_IO A4_IO A5_IO A6_IO A7_IO A8_IO + QB1 QB2 QB3 QB4 QB5 QB6 QB7 QB8 + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D0_EFF IO_ALS00 * U2 DFF(8) DPWR DGND $D_HI $D_HI CBA + B1_IO B2_IO B3_IO B4_IO B5_IO B6_IO B7_IO B8_IO + QA1 QA2 QA3 QA4 QA5 QA6 QA7 QA8 + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D0_EFF IO_ALS00 * U3 BUF3A(8) DPWR DGND + A1_O A2_O A3_O A4_O A5_O A6_O A7_O A8_O IGBABAR + A1_IO A2_IO A3_IO A4_IO A5_IO A6_IO A7_IO A8_IO + D0_TGATE IO_ALS00 * U4 BUF3A(8) DPWR DGND + B1_O B2_O B3_O B4_O B5_O B6_O B7_O B8_O GAB + B1_IO B2_IO B3_IO B4_IO B5_IO B6_IO B7_IO B8_IO + D0_TGATE IO_ALS00 * U5 BUF3A(8) DPWR DGND + A1 A2 A3 A4 A5 A6 A7 A8 GBABAR + A1_IO A2_IO A3_IO A4_IO A5_IO A6_IO A7_IO A8_IO + D0_TGATE IO_ALS00 * U6 BUF3A(8) DPWR DGND + B1 B2 B3 B4 B5 B6 B7 B8 IGAB + B1_IO B2_IO B3_IO B4_IO B5_IO B6_IO B7_IO B8_IO + D0_TGATE IO_ALS00 * UALS651LOG LOGICEXP(38,40) DPWR DGND + GBABAR_I GAB_I CBA_I SBA_I CAB_I SAB_I A1_B A2_B A3_B A4_B A5_B A6_B + A7_B A8_B B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B QA1 QA2 QA3 + QA4 QA5 QA6 QA7 QA8 QB1 QB2 QB3 QB4 QB5 + QB6 QB7 QB8 + GBABAR GAB CBA SBA CAB SAB A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 + A1_O A2_O A3_O A4_O A5_O A6_O A7_O A8_O B1_O B2_O B3_O B4_O B5_O B6_O + B7_O B8_O IGAB IGBABAR + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} + LOGIC: + GBABAR = { GBABAR_I } + GAB = { GAB_I } + CBA = { CBA_I } + SBA = { SBA_I } + CAB = { CAB_I } + SAB = { SAB_I } + A1 = { A1_B } + A2 = { A2_B } + A3 = { A3_B } + A4 = { A4_B } + A5 = { A5_B } + A6 = { A6_B } + A7 = { A7_B } + A8 = { A8_B } + B1 = { B1_B } + B2 = { B2_B } + B3 = { B3_B } + B4 = { B4_B } + B5 = { B5_B } + B6 = { B6_B } + B7 = { B7_B } + B8 = { B8_B } + ISAB = { ~SAB } + ISBA = { ~SBA } + IGAB = { ~GAB } + IGBABAR = { ~GBABAR } + A1_O = { ~((SBA & QA1) | (ISBA & B1)) } + A2_O = { ~((SBA & QA2) | (ISBA & B2)) } + A3_O = { ~((SBA & QA3) | (ISBA & B3)) } + A4_O = { ~((SBA & QA4) | (ISBA & B4)) } + A5_O = { ~((SBA & QA5) | (ISBA & B5)) } + A6_O = { ~((SBA & QA6) | (ISBA & B6)) } + A7_O = { ~((SBA & QA7) | (ISBA & B7)) } + A8_O = { ~((SBA & QA8) | (ISBA & B8)) } + B1_O = { ~((SAB & QB1) | (ISAB & A1)) } + B2_O = { ~((SAB & QB2) | (ISAB & A2)) } + B3_O = { ~((SAB & QB3) | (ISAB & A3)) } + B4_O = { ~((SAB & QB4) | (ISAB & A4)) } + B5_O = { ~((SAB & QB5) | (ISAB & A5)) } + B6_O = { ~((SAB & QB6) | (ISAB & A6)) } + B7_O = { ~((SAB & QB7) | (ISAB & A7)) } + B8_O = { ~((SAB & QB8) | (ISAB & A8)) } * UALS651DLY PINDLY (16,2,22) DPWR DGND + A1_IO A2_IO A3_IO A4_IO A5_IO A6_IO A7_IO A8_IO B1_IO B2_IO B3_IO B4_IO B5_IO B6_IO B7_IO B8_IO + GBABAR GAB + CBA SBA CAB SAB A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 B7 B8 + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + CLOCK_BA = { CHANGED_LH(CBA,0) } + CLOCK_AB = { CHANGED_LH(CAB,0) } + SEL_BA = { CHANGED(SBA,0) } + SEL_AB = { CHANGED(SAB,0) } + TRISTATE: + ENABLE LO GBABAR + A1_B = { + CASE( + TRN_HZ, DELAY(2NS,4NS,9NS), + CHANGED(B1,0) & TRN_HL, DELAY(2NS,5NS,10NS), + TRN_LZ, DELAY(3NS,7NS,12NS), + TRN_ZH, DELAY(5NS,12NS,20NS), + CLOCK_BA & TRN_HL, DELAY(5NS,11NS,17NS), + TRN_ZL, DELAY(5NS,11NS,18NS), + CHANGED(B1,0) & TRN_LH, DELAY(4NS,9NS,18NS), + SEL_BA & TRN_HL, DELAY(7NS,13NS,21NS), + SEL_BA & B1=='0 & TRN_LH, DELAY(13NS,24NS,38NS), + CLOCK_BA & TRN_LH, DELAY(10NS,20NS,32NS), + SEL_BA & B1=='1 & TRN_LH, DELAY(8NS,15NS,25NS), + DELAY(14NS,25NS,39NS) + ) + } + A2_B = { + CASE( + TRN_HZ, DELAY(2NS,4NS,9NS), + CHANGED(B2,0) & TRN_HL, DELAY(2NS,5NS,10NS), + TRN_LZ, DELAY(3NS,7NS,12NS), + TRN_ZH, DELAY(5NS,12NS,20NS), + CLOCK_BA & TRN_HL, DELAY(5NS,11NS,17NS), + TRN_ZL, DELAY(5NS,11NS,18NS), + CHANGED(B2,0) & TRN_LH, DELAY(4NS,9NS,18NS), + SEL_BA & TRN_HL, DELAY(7NS,13NS,21NS), + SEL_BA & B2=='0 & TRN_LH, DELAY(13NS,24NS,38NS), + CLOCK_BA & TRN_LH, DELAY(10NS,20NS,32NS), + SEL_BA & B2=='1 & TRN_LH, DELAY(8NS,15NS,25NS), + DELAY(14NS,25NS,39NS) + ) + } + A3_B = { + CASE( + TRN_HZ, DELAY(2NS,4NS,9NS), + CHANGED(B3,0) & TRN_HL, DELAY(2NS,5NS,10NS), + TRN_LZ, DELAY(3NS,7NS,12NS), + TRN_ZH, DELAY(5NS,12NS,20NS), + CLOCK_BA & TRN_HL, DELAY(5NS,11NS,17NS), + TRN_ZL, DELAY(5NS,11NS,18NS), + CHANGED(B3,0) & TRN_LH, DELAY(4NS,9NS,18NS), + SEL_BA & TRN_HL, DELAY(7NS,13NS,21NS), + SEL_BA & B3=='0 & TRN_LH, DELAY(13NS,24NS,38NS), + CLOCK_BA & TRN_LH, DELAY(10NS,20NS,32NS), + SEL_BA & B3=='1 & TRN_LH, DELAY(8NS,15NS,25NS), + DELAY(14NS,25NS,39NS) + ) + } + A4_B = { + CASE( + TRN_HZ, DELAY(2NS,4NS,9NS), + CHANGED(B4,0) & TRN_HL, DELAY(2NS,5NS,10NS), + TRN_LZ, DELAY(3NS,7NS,12NS), + TRN_ZH, DELAY(5NS,12NS,20NS), + CLOCK_BA & TRN_HL, DELAY(5NS,11NS,17NS), + TRN_ZL, DELAY(5NS,11NS,18NS), + CHANGED(B4,0) & TRN_LH, DELAY(4NS,9NS,18NS), + SEL_BA & TRN_HL, DELAY(7NS,13NS,21NS), + SEL_BA & B4=='0 & TRN_LH, DELAY(13NS,24NS,38NS), + CLOCK_BA & TRN_LH, DELAY(10NS,20NS,32NS), + SEL_BA & B4=='1 & TRN_LH, DELAY(8NS,15NS,25NS), + DELAY(14NS,25NS,39NS) + ) + } + A5_B = { + CASE( + TRN_HZ, DELAY(2NS,4NS,9NS), + CHANGED(B5,0) & TRN_HL, DELAY(2NS,5NS,10NS), + TRN_LZ, DELAY(3NS,7NS,12NS), + TRN_ZH, DELAY(5NS,12NS,20NS), + CLOCK_BA & TRN_HL, DELAY(5NS,11NS,17NS), + TRN_ZL, DELAY(5NS,11NS,18NS), + CHANGED(B5,0) & TRN_LH, DELAY(4NS,9NS,18NS), + SEL_BA & TRN_HL, DELAY(7NS,13NS,21NS), + SEL_BA & B5=='0 & TRN_LH, DELAY(13NS,24NS,38NS), + CLOCK_BA & TRN_LH, DELAY(10NS,20NS,32NS), + SEL_BA & B5=='1 & TRN_LH, DELAY(8NS,15NS,25NS), + DELAY(14NS,25NS,39NS) + ) + } + A6_B = { + CASE( + TRN_HZ, DELAY(2NS,4NS,9NS), + CHANGED(B6,0) & TRN_HL, DELAY(2NS,5NS,10NS), + TRN_LZ, DELAY(3NS,7NS,12NS), + TRN_ZH, DELAY(5NS,12NS,20NS), + CLOCK_BA & TRN_HL, DELAY(5NS,11NS,17NS), + TRN_ZL, DELAY(5NS,11NS,18NS), + CHANGED(B6,0) & TRN_LH, DELAY(4NS,9NS,18NS), + SEL_BA & TRN_HL, DELAY(7NS,13NS,21NS), + SEL_BA & B6=='0 & TRN_LH, DELAY(13NS,24NS,38NS), + CLOCK_BA & TRN_LH, DELAY(10NS,20NS,32NS), + SEL_BA & B6=='1 & TRN_LH, DELAY(8NS,15NS,25NS), + DELAY(14NS,25NS,39NS) + ) + } + A7_B = { + CASE( + TRN_HZ, DELAY(2NS,4NS,9NS), + CHANGED(B7,0) & TRN_HL, DELAY(2NS,5NS,10NS), + TRN_LZ, DELAY(3NS,7NS,12NS), + TRN_ZH, DELAY(5NS,12NS,20NS), + CLOCK_BA & TRN_HL, DELAY(5NS,11NS,17NS), + TRN_ZL, DELAY(5NS,11NS,18NS), + CHANGED(B7,0) & TRN_LH, DELAY(4NS,9NS,18NS), + SEL_BA & TRN_HL, DELAY(7NS,13NS,21NS), + SEL_BA & B7=='0 & TRN_LH, DELAY(13NS,24NS,38NS), + CLOCK_BA & TRN_LH, DELAY(10NS,20NS,32NS), + SEL_BA & B7=='1 & TRN_LH, DELAY(8NS,15NS,25NS), + DELAY(14NS,25NS,39NS) + ) + } + A8_B = { + CASE( + TRN_HZ, DELAY(2NS,4NS,9NS), + CHANGED(B8,0) & TRN_HL, DELAY(2NS,5NS,10NS), + TRN_LZ, DELAY(3NS,7NS,12NS), + TRN_ZH, DELAY(5NS,12NS,20NS), + CLOCK_BA & TRN_HL, DELAY(5NS,11NS,17NS), + TRN_ZL, DELAY(5NS,11NS,18NS), + CHANGED(B8,0) & TRN_LH, DELAY(4NS,9NS,18NS), + SEL_BA & TRN_HL, DELAY(7NS,13NS,21NS), + SEL_BA & B8=='0 & TRN_LH, DELAY(13NS,24NS,38NS), + CLOCK_BA & TRN_LH, DELAY(10NS,20NS,32NS), + SEL_BA & B8=='1 & TRN_LH, DELAY(8NS,15NS,25NS), + DELAY(14NS,25NS,39NS) + ) + } + TRISTATE: + ENABLE HI GAB + B1_B = { + CASE( + TRN_HZ, DELAY(2NS,5NS,12NS), + CHANGED(A1,0) & TRN_HL, DELAY(2NS,5NS,10NS), + TRN_LZ, DELAY(2NS,7NS,14NS), + TRN_ZH, DELAY(7NS,14NS,22NS), + CLOCK_AB & TRN_HL, DELAY(5NS,11NS,17NS), + TRN_ZL, DELAY(7NS,13NS,21NS), + CHANGED(A1,0) & TRN_LH, DELAY(4NS,9NS,18NS), + SEL_AB & TRN_HL, DELAY(7NS,13NS,21NS), + SEL_AB & A1=='0 & TRN_LH, DELAY(13NS,24NS,38NS), + CLOCK_AB & TRN_LH, DELAY(10NS,20NS,32NS), + SEL_AB & A1=='1 & TRN_LH, DELAY(8NS,15NS,25NS), + DELAY(14NS,25NS,39NS) + ) + } + B2_B = { + CASE( + TRN_HZ, DELAY(2NS,5NS,12NS), + CHANGED(A2,0) & TRN_HL, DELAY(2NS,5NS,10NS), + TRN_LZ, DELAY(2NS,7NS,14NS), + TRN_ZH, DELAY(7NS,14NS,22NS), + CLOCK_AB & TRN_HL, DELAY(5NS,11NS,17NS), + TRN_ZL, DELAY(7NS,13NS,21NS), + CHANGED(A2,0) & TRN_LH, DELAY(4NS,9NS,18NS), + SEL_AB & TRN_HL, DELAY(7NS,13NS,21NS), + SEL_AB & A2=='0 & TRN_LH, DELAY(13NS,24NS,38NS), + CLOCK_AB & TRN_LH, DELAY(10NS,20NS,32NS), + SEL_AB & A2=='1 & TRN_LH, DELAY(8NS,15NS,25NS), + DELAY(14NS,25NS,39NS) + ) + } + B3_B = { + CASE( + TRN_HZ, DELAY(2NS,5NS,12NS), + CHANGED(A1,0) & TRN_HL, DELAY(2NS,5NS,10NS), + TRN_LZ, DELAY(2NS,7NS,14NS), + TRN_ZH, DELAY(7NS,14NS,22NS), + CLOCK_AB & TRN_HL, DELAY(5NS,11NS,17NS), + TRN_ZL, DELAY(7NS,13NS,21NS), + CHANGED(A1,0) & TRN_LH, DELAY(4NS,9NS,18NS), + SEL_AB & TRN_HL, DELAY(7NS,13NS,21NS), + SEL_AB & A1=='0 & TRN_LH, DELAY(13NS,24NS,38NS), + CLOCK_AB & TRN_LH, DELAY(10NS,20NS,32NS), + SEL_AB & A1=='1 & TRN_LH, DELAY(8NS,15NS,25NS), + DELAY(14NS,25NS,39NS) + ) + } + B4_B = { + CASE( + TRN_HZ, DELAY(2NS,5NS,12NS), + CHANGED(A4,0) & TRN_HL, DELAY(2NS,5NS,10NS), + TRN_LZ, DELAY(2NS,7NS,14NS), + TRN_ZH, DELAY(7NS,14NS,22NS), + CLOCK_AB & TRN_HL, DELAY(5NS,11NS,17NS), + TRN_ZL, DELAY(7NS,13NS,21NS), + CHANGED(A4,0) & TRN_LH, DELAY(4NS,9NS,18NS), + SEL_AB & TRN_HL, DELAY(7NS,13NS,21NS), + SEL_AB & A4=='0 & TRN_LH, DELAY(13NS,24NS,38NS), + CLOCK_AB & TRN_LH, DELAY(10NS,20NS,32NS), + SEL_AB & A4=='1 & TRN_LH, DELAY(8NS,15NS,25NS), + DELAY(14NS,25NS,39NS) + ) + } + B5_B = { + CASE( + TRN_HZ, DELAY(2NS,5NS,12NS), + CHANGED(A5,0) & TRN_HL, DELAY(2NS,5NS,10NS), + TRN_LZ, DELAY(2NS,7NS,14NS), + TRN_ZH, DELAY(7NS,14NS,22NS), + CLOCK_AB & TRN_HL, DELAY(5NS,11NS,17NS), + TRN_ZL, DELAY(7NS,13NS,21NS), + CHANGED(A5,0) & TRN_LH, DELAY(4NS,9NS,18NS), + SEL_AB & TRN_HL, DELAY(7NS,13NS,21NS), + SEL_AB & A5=='0 & TRN_LH, DELAY(13NS,24NS,38NS), + CLOCK_AB & TRN_LH, DELAY(10NS,20NS,32NS), + SEL_AB & A5=='1 & TRN_LH, DELAY(8NS,15NS,25NS), + DELAY(14NS,25NS,39NS) + ) + } + B6_B = { + CASE( + TRN_HZ, DELAY(2NS,5NS,12NS), + CHANGED(A6,0) & TRN_HL, DELAY(2NS,5NS,10NS), + TRN_LZ, DELAY(2NS,7NS,14NS), + TRN_ZH, DELAY(7NS,14NS,22NS), + CLOCK_AB & TRN_HL, DELAY(5NS,11NS,17NS), + TRN_ZL, DELAY(7NS,13NS,21NS), + CHANGED(A6,0) & TRN_LH, DELAY(4NS,9NS,18NS), + SEL_AB & TRN_HL, DELAY(7NS,13NS,21NS), + SEL_AB & A6=='0 & TRN_LH, DELAY(13NS,24NS,38NS), + CLOCK_AB & TRN_LH, DELAY(10NS,20NS,32NS), + SEL_AB & A6=='1 & TRN_LH, DELAY(8NS,15NS,25NS), + DELAY(14NS,25NS,39NS) + ) + } + B7_B = { + CASE( + TRN_HZ, DELAY(2NS,5NS,12NS), + CHANGED(A7,0) & TRN_HL, DELAY(2NS,5NS,10NS), + TRN_LZ, DELAY(2NS,7NS,14NS), + TRN_ZH, DELAY(7NS,14NS,22NS), + CLOCK_AB & TRN_HL, DELAY(5NS,11NS,17NS), + TRN_ZL, DELAY(7NS,13NS,21NS), + CHANGED(A7,0) & TRN_LH, DELAY(4NS,9NS,18NS), + SEL_AB & TRN_HL, DELAY(7NS,13NS,21NS), + SEL_AB & A7=='0 & TRN_LH, DELAY(13NS,24NS,38NS), + CLOCK_AB & TRN_LH, DELAY(10NS,20NS,32NS), + SEL_AB & A7=='1 & TRN_LH, DELAY(8NS,15NS,25NS), + DELAY(14NS,25NS,39NS) + ) + } + B8_B = { + CASE( + TRN_HZ, DELAY(2NS,5NS,12NS), + CHANGED(A8,0) & TRN_HL, DELAY(2NS,5NS,10NS), + TRN_LZ, DELAY(2NS,7NS,14NS), + TRN_ZH, DELAY(7NS,14NS,22NS), + CLOCK_AB & TRN_HL, DELAY(5NS,11NS,17NS), + TRN_ZL, DELAY(7NS,13NS,21NS), + CHANGED(A8,0) & TRN_LH, DELAY(4NS,9NS,18NS), + SEL_AB & TRN_HL, DELAY(7NS,13NS,21NS), + SEL_AB & A8=='0 & TRN_LH, DELAY(13NS,24NS,38NS), + CLOCK_AB & TRN_LH, DELAY(10NS,20NS,32NS), + SEL_AB & A8=='1 & TRN_LH, DELAY(8NS,15NS,25NS), + DELAY(14NS,25NS,39NS) + ) + } + FREQ: + NODE = CBA + MAXFREQ = 40MEG + FREQ: + NODE = CAB + MAXFREQ = 40MEG + WIDTH: + NODE = CBA + MIN_LO = 12.5NS + MIN_HI = 12.5NS + WIDTH: + NODE = CAB + MIN_LO = 12.5NS + MIN_HI = 12.5NS + SETUP_HOLD: + DATA(8) = A1 A2 A3 A4 A5 A6 A7 A8 + CLOCK LH = CAB + SETUPTIME = 10NS + SETUP_HOLD: + DATA(8) = B1 B2 B3 B4 B5 B6 B7 B8 + CLOCK LH = CBA + SETUPTIME = 10NS * .ENDS * *$ *------------------------------------------------------------------------ * 74ALS652 BUS TRANSCEIVERS AND REGISTERS OCTAL WITH 3-STATE OUTPUTS * * ALS/AS LOGIC DATA BOOK, 1986, TI * TC 08/28/92 REMODELED USING LOGICEXP, PINDLY, & CONSTRAINT DEVICES * * NOTE: ADDITIONAL LOGIC WAS ADDED TO MODEL THE BIDIRECTIONAL PINS OF THIS * DEVICE. * .SUBCKT 74ALS652 GBABAR_I GAB_I CBA_I SBA_I CAB_I SAB_I + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 DFF(8) DPWR DGND $D_HI $D_HI CAB + A1_IO A2_IO A3_IO A4_IO A5_IO A6_IO A7_IO A8_IO + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + QB1BAR QB2BAR QB3BAR QB4BAR QB5BAR QB6BAR QB7BAR QB8BAR + D0_EFF IO_ALS00 * U2 DFF(8) DPWR DGND $D_HI $D_HI CBA + B1_IO B2_IO B3_IO B4_IO B5_IO B6_IO B7_IO B8_IO + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + QA1BAR QA2BAR QA3BAR QA4BAR QA5BAR QA6BAR QA7BAR QA8BAR + D0_EFF IO_ALS00 * U3 BUF3A(8) DPWR DGND + A1_O A2_O A3_O A4_O A5_O A6_O A7_O A8_O IGBABAR + A1_IO A2_IO A3_IO A4_IO A5_IO A6_IO A7_IO A8_IO + D0_TGATE IO_ALS00 * U4 BUF3A(8) DPWR DGND + B1_O B2_O B3_O B4_O B5_O B6_O B7_O B8_O GAB + B1_IO B2_IO B3_IO B4_IO B5_IO B6_IO B7_IO B8_IO + D0_TGATE IO_ALS00 * U5 BUF3A(8) DPWR DGND + A1 A2 A3 A4 A5 A6 A7 A8 GBABAR + A1_IO A2_IO A3_IO A4_IO A5_IO A6_IO A7_IO A8_IO + D0_TGATE IO_ALS00 * U6 BUF3A(8) DPWR DGND + B1 B2 B3 B4 B5 B6 B7 B8 IGAB + B1_IO B2_IO B3_IO B4_IO B5_IO B6_IO B7_IO B8_IO + D0_TGATE IO_ALS00 * UALS652LOG LOGICEXP(38,40) DPWR DGND + GBABAR_I GAB_I CBA_I SBA_I CAB_I SAB_I + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + QA1BAR QA2BAR QA3BAR QA4BAR QA5BAR QA6BAR QA7BAR QA8BAR + QB1BAR QB2BAR QB3BAR QB4BAR QB5BAR QB6BAR QB7BAR QB8BAR + GBABAR GAB CBA SBA CAB SAB A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 + A1_O A2_O A3_O A4_O A5_O A6_O A7_O A8_O + B1_O B2_O B3_O B4_O B5_O B6_O B7_O B8_O IGAB IGBABAR + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} + LOGIC: + GBABAR = { GBABAR_I } + GAB = { GAB_I } + CBA = { CBA_I } + SBA = { SBA_I } + CAB = { CAB_I } + SAB = { SAB_I } + A1 = { A1_B } + A2 = { A2_B } + A3 = { A3_B } + A4 = { A4_B } + A5 = { A5_B } + A6 = { A6_B } + A7 = { A7_B } + A8 = { A8_B } + B1 = { B1_B } + B2 = { B2_B } + B3 = { B3_B } + B4 = { B4_B } + B5 = { B5_B } + B6 = { B6_B } + B7 = { B7_B } + B8 = { B8_B } + ISAB = { ~SAB } + ISBA = { ~SBA } + IGAB = { ~GAB } + IGBABAR = { ~GBABAR } + A1_O = { ~((SBA & QA1BAR) | (ISBA & ~B1)) } + A2_O = { ~((SBA & QA2BAR) | (ISBA & ~B2)) } + A3_O = { ~((SBA & QA3BAR) | (ISBA & ~B3)) } + A4_O = { ~((SBA & QA4BAR) | (ISBA & ~B4)) } + A5_O = { ~((SBA & QA5BAR) | (ISBA & ~B5)) } + A6_O = { ~((SBA & QA6BAR) | (ISBA & ~B6)) } + A7_O = { ~((SBA & QA7BAR) | (ISBA & ~B7)) } + A8_O = { ~((SBA & QA8BAR) | (ISBA & ~B8)) } + B1_O = { ~((SAB & QB1BAR) | (ISAB & ~A1)) } + B2_O = { ~((SAB & QB2BAR) | (ISAB & ~A2)) } + B3_O = { ~((SAB & QB3BAR) | (ISAB & ~A3)) } + B4_O = { ~((SAB & QB4BAR) | (ISAB & ~A4)) } + B5_O = { ~((SAB & QB5BAR) | (ISAB & ~A5)) } + B6_O = { ~((SAB & QB6BAR) | (ISAB & ~A6)) } + B7_O = { ~((SAB & QB7BAR) | (ISAB & ~A7)) } + B8_O = { ~((SAB & QB8BAR) | (ISAB & ~A8)) } * UALS652DLY PINDLY (16,2,22) DPWR DGND + A1_IO A2_IO A3_IO A4_IO A5_IO A6_IO A7_IO A8_IO B1_IO B2_IO B3_IO B4_IO B5_IO B6_IO B7_IO B8_IO + GBABAR GAB + CBA SBA CAB SAB A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 B7 B8 + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + CLOCK_BA = { CHANGED_LH(CBA,0) } + CLOCK_AB = { CHANGED_LH(CAB,0) } + SEL_BA = { CHANGED(SBA,0) } + SEL_AB = { CHANGED(SAB,0) } + TRISTATE: + ENABLE LO GBABAR + A1_B = { + CASE( + SEL_BA & B1=='0 & TRN_LH, DELAY(15NS,24NS,35NS), + CLOCK_BA & TRN_LH, DELAY(10NS,20NS,30NS), + SEL_BA & B1=='1 & TRN_LH, DELAY(8NS,17NS,25NS), + SEL_BA & B1=='0 & TRN_HL, DELAY(6NS,13NS,20NS), + SEL_BA & B1=='1 & TRN_HL, DELAY(5NS,13NS,20NS), + CHANGED(B1,0) & TRN_LH, DELAY(5NS,11NS,18NS), + CLOCK_BA & TRN_HL, DELAY(5NS,11NS,17NS), + CHANGED(B1,0) & TRN_HL, DELAY(3NS,8NS,12NS), + TRN_ZH, DELAY(3NS,10NS,17NS), + TRN_ZL, DELAY(5NS,10NS,18NS), + TRN_HZ, DELAY(1NS,6NS,10NS), + TRN_LZ, DELAY(2NS,10NS,16NS), + DELAY(16NS,25NS,36NS) + ) + } + A2_B = { + CASE( + SEL_BA & B2=='0 & TRN_LH, DELAY(15NS,24NS,35NS), + CLOCK_BA & TRN_LH, DELAY(10NS,20NS,30NS), + SEL_BA & B2=='1 & TRN_LH, DELAY(8NS,17NS,25NS), + SEL_BA & B2=='0 & TRN_HL, DELAY(6NS,13NS,20NS), + SEL_BA & B2=='1 & TRN_HL, DELAY(5NS,13NS,20NS), + CHANGED(B2,0) & TRN_LH, DELAY(5NS,11NS,18NS), + CLOCK_BA & TRN_HL, DELAY(5NS,11NS,17NS), + CHANGED(B2,0) & TRN_HL, DELAY(3NS,8NS,12NS), + TRN_ZH, DELAY(3NS,10NS,17NS), + TRN_ZL, DELAY(5NS,10NS,18NS), + TRN_HZ, DELAY(1NS,6NS,10NS), + TRN_LZ, DELAY(2NS,10NS,16NS), + DELAY(16NS,25NS,36NS) + ) + } + A3_B = { + CASE( + SEL_BA & B3=='0 & TRN_LH, DELAY(15NS,24NS,35NS), + CLOCK_BA & TRN_LH, DELAY(10NS,20NS,30NS), + SEL_BA & B3=='1 & TRN_LH, DELAY(8NS,17NS,25NS), + SEL_BA & B3=='0 & TRN_HL, DELAY(6NS,13NS,20NS), + SEL_BA & B3=='1 & TRN_HL, DELAY(5NS,13NS,20NS), + CHANGED(B3,0) & TRN_LH, DELAY(5NS,11NS,18NS), + CLOCK_BA & TRN_HL, DELAY(5NS,11NS,17NS), + CHANGED(B3,0) & TRN_HL, DELAY(3NS,8NS,12NS), + TRN_ZH, DELAY(3NS,10NS,17NS), + TRN_ZL, DELAY(5NS,10NS,18NS), + TRN_HZ, DELAY(1NS,6NS,10NS), + TRN_LZ, DELAY(2NS,10NS,16NS), + DELAY(16NS,25NS,36NS) + ) + } + A4_B = { + CASE( + SEL_BA & B4=='0 & TRN_LH, DELAY(15NS,24NS,35NS), + CLOCK_BA & TRN_LH, DELAY(10NS,20NS,30NS), + SEL_BA & B4=='1 & TRN_LH, DELAY(8NS,17NS,25NS), + SEL_BA & B4=='0 & TRN_HL, DELAY(6NS,13NS,20NS), + SEL_BA & B4=='1 & TRN_HL, DELAY(5NS,13NS,20NS), + CHANGED(B4,0) & TRN_LH, DELAY(5NS,11NS,18NS), + CLOCK_BA & TRN_HL, DELAY(5NS,11NS,17NS), + CHANGED(B4,0) & TRN_HL, DELAY(3NS,8NS,12NS), + TRN_ZH, DELAY(3NS,10NS,17NS), + TRN_ZL, DELAY(5NS,10NS,18NS), + TRN_HZ, DELAY(1NS,6NS,10NS), + TRN_LZ, DELAY(2NS,10NS,16NS), + DELAY(16NS,25NS,36NS) + ) + } + A5_B = { + CASE( + SEL_BA & B5=='0 & TRN_LH, DELAY(15NS,24NS,35NS), + CLOCK_BA & TRN_LH, DELAY(10NS,20NS,30NS), + SEL_BA & B5=='1 & TRN_LH, DELAY(8NS,17NS,25NS), + SEL_BA & B5=='0 & TRN_HL, DELAY(6NS,13NS,20NS), + SEL_BA & B5=='1 & TRN_HL, DELAY(5NS,13NS,20NS), + CHANGED(B5,0) & TRN_LH, DELAY(5NS,11NS,18NS), + CLOCK_BA & TRN_HL, DELAY(5NS,11NS,17NS), + CHANGED(B5,0) & TRN_HL, DELAY(3NS,8NS,12NS), + TRN_ZH, DELAY(3NS,10NS,17NS), + TRN_ZL, DELAY(5NS,10NS,18NS), + TRN_HZ, DELAY(1NS,6NS,10NS), + TRN_LZ, DELAY(2NS,10NS,16NS), + DELAY(16NS,25NS,36NS) + ) + } + A6_B = { + CASE( + SEL_BA & B6=='0 & TRN_LH, DELAY(15NS,24NS,35NS), + CLOCK_BA & TRN_LH, DELAY(10NS,20NS,30NS), + SEL_BA & B6=='1 & TRN_LH, DELAY(8NS,17NS,25NS), + SEL_BA & B6=='0 & TRN_HL, DELAY(6NS,13NS,20NS), + SEL_BA & B6=='1 & TRN_HL, DELAY(5NS,13NS,20NS), + CHANGED(B6,0) & TRN_LH, DELAY(5NS,11NS,18NS), + CLOCK_BA & TRN_HL, DELAY(5NS,11NS,17NS), + CHANGED(B6,0) & TRN_HL, DELAY(3NS,8NS,12NS), + TRN_ZH, DELAY(3NS,10NS,17NS), + TRN_ZL, DELAY(5NS,10NS,18NS), + TRN_HZ, DELAY(1NS,6NS,10NS), + TRN_LZ, DELAY(2NS,10NS,16NS), + DELAY(16NS,25NS,36NS) + ) + } + A7_B = { + CASE( + SEL_BA & B7=='0 & TRN_LH, DELAY(15NS,24NS,35NS), + CLOCK_BA & TRN_LH, DELAY(10NS,20NS,30NS), + SEL_BA & B7=='1 & TRN_LH, DELAY(8NS,17NS,25NS), + SEL_BA & B7=='0 & TRN_HL, DELAY(6NS,13NS,20NS), + SEL_BA & B7=='1 & TRN_HL, DELAY(5NS,13NS,20NS), + CHANGED(B7,0) & TRN_LH, DELAY(5NS,11NS,18NS), + CLOCK_BA & TRN_HL, DELAY(5NS,11NS,17NS), + CHANGED(B7,0) & TRN_HL, DELAY(3NS,8NS,12NS), + TRN_ZH, DELAY(3NS,10NS,17NS), + TRN_ZL, DELAY(5NS,10NS,18NS), + TRN_HZ, DELAY(1NS,6NS,10NS), + TRN_LZ, DELAY(2NS,10NS,16NS), + DELAY(16NS,25NS,36NS) + ) + } + A8_B = { + CASE( + SEL_BA & B8=='0 & TRN_LH, DELAY(15NS,24NS,35NS), + CLOCK_BA & TRN_LH, DELAY(10NS,20NS,30NS), + SEL_BA & B8=='1 & TRN_LH, DELAY(8NS,17NS,25NS), + SEL_BA & B8=='0 & TRN_HL, DELAY(6NS,13NS,20NS), + SEL_BA & B8=='1 & TRN_HL, DELAY(5NS,13NS,20NS), + CHANGED(B8,0) & TRN_LH, DELAY(5NS,11NS,18NS), + CLOCK_BA & TRN_HL, DELAY(5NS,11NS,17NS), + CHANGED(B8,0) & TRN_HL, DELAY(3NS,8NS,12NS), + TRN_ZH, DELAY(3NS,10NS,17NS), + TRN_ZL, DELAY(5NS,10NS,18NS), + TRN_HZ, DELAY(1NS,6NS,10NS), + TRN_LZ, DELAY(2NS,10NS,16NS), + DELAY(16NS,25NS,36NS) + ) + } + TRISTATE: + ENABLE HI GAB + B1_B = { + CASE( + SEL_AB & A1=='0 & TRN_LH, DELAY(15NS,24NS,35NS), + CLOCK_AB & TRN_LH, DELAY(10NS,20NS,30NS), + SEL_AB & A1=='1 & TRN_LH, DELAY(8NS,17NS,25NS), + SEL_AB & A1=='0 & TRN_HL, DELAY(6NS,13NS,20NS), + SEL_AB & A1=='1 & TRN_HL, DELAY(5NS,13NS,20NS), + CHANGED(A1,0) & TRN_LH, DELAY(5NS,11NS,18NS), + CLOCK_AB & TRN_HL, DELAY(5NS,11NS,17NS), + CHANGED(A1,0) & TRN_HL, DELAY(3NS,8NS,12NS), + TRN_ZH, DELAY(3NS,10NS,17NS), + TRN_ZL, DELAY(5NS,10NS,18NS), + TRN_HZ, DELAY(1NS,6NS,10NS), + TRN_LZ, DELAY(2NS,10NS,16NS), + DELAY(16NS,25NS,36NS) + ) + } + B2_B = { + CASE( + SEL_AB & A2=='0 & TRN_LH, DELAY(15NS,24NS,35NS), + CLOCK_AB & TRN_LH, DELAY(10NS,20NS,30NS), + SEL_AB & A2=='1 & TRN_LH, DELAY(8NS,17NS,25NS), + SEL_AB & A2=='0 & TRN_HL, DELAY(6NS,13NS,20NS), + SEL_AB & A2=='1 & TRN_HL, DELAY(5NS,13NS,20NS), + CHANGED(A2,0) & TRN_LH, DELAY(5NS,11NS,18NS), + CLOCK_AB & TRN_HL, DELAY(5NS,11NS,17NS), + CHANGED(A2,0) & TRN_HL, DELAY(3NS,8NS,12NS), + TRN_ZH, DELAY(3NS,10NS,17NS), + TRN_ZL, DELAY(5NS,10NS,18NS), + TRN_HZ, DELAY(1NS,6NS,10NS), + TRN_LZ, DELAY(2NS,10NS,16NS), + DELAY(16NS,25NS,36NS) + ) + } + B3_B = { + CASE( + SEL_AB & A3=='0 & TRN_LH, DELAY(15NS,24NS,35NS), + CLOCK_AB & TRN_LH, DELAY(10NS,20NS,30NS), + SEL_AB & A3=='1 & TRN_LH, DELAY(8NS,17NS,25NS), + SEL_AB & A3=='0 & TRN_HL, DELAY(6NS,13NS,20NS), + SEL_AB & A3=='1 & TRN_HL, DELAY(5NS,13NS,20NS), + CHANGED(A3,0) & TRN_LH, DELAY(5NS,11NS,18NS), + CLOCK_AB & TRN_HL, DELAY(5NS,11NS,17NS), + CHANGED(A3,0) & TRN_HL, DELAY(3NS,8NS,12NS), + TRN_ZH, DELAY(3NS,10NS,17NS), + TRN_ZL, DELAY(5NS,10NS,18NS), + TRN_HZ, DELAY(1NS,6NS,10NS), + TRN_LZ, DELAY(2NS,10NS,16NS), + DELAY(16NS,25NS,36NS) + ) + } + B4_B = { + CASE( + SEL_AB & A4=='0 & TRN_LH, DELAY(15NS,24NS,35NS), + CLOCK_AB & TRN_LH, DELAY(10NS,20NS,30NS), + SEL_AB & A4=='1 & TRN_LH, DELAY(8NS,17NS,25NS), + SEL_AB & A4=='0 & TRN_HL, DELAY(6NS,13NS,20NS), + SEL_AB & A4=='1 & TRN_HL, DELAY(5NS,13NS,20NS), + CHANGED(A4,0) & TRN_LH, DELAY(5NS,11NS,18NS), + CLOCK_AB & TRN_HL, DELAY(5NS,11NS,17NS), + CHANGED(A4,0) & TRN_HL, DELAY(3NS,8NS,12NS), + TRN_ZH, DELAY(3NS,10NS,17NS), + TRN_ZL, DELAY(5NS,10NS,18NS), + TRN_HZ, DELAY(1NS,6NS,10NS), + TRN_LZ, DELAY(2NS,10NS,16NS), + DELAY(16NS,25NS,36NS) + ) + } + B5_B = { + CASE( + SEL_AB & A5=='0 & TRN_LH, DELAY(15NS,24NS,35NS), + CLOCK_AB & TRN_LH, DELAY(10NS,20NS,30NS), + SEL_AB & A5=='1 & TRN_LH, DELAY(8NS,17NS,25NS), + SEL_AB & A5=='0 & TRN_HL, DELAY(6NS,13NS,20NS), + SEL_AB & A5=='1 & TRN_HL, DELAY(5NS,13NS,20NS), + CHANGED(A5,0) & TRN_LH, DELAY(5NS,11NS,18NS), + CLOCK_AB & TRN_HL, DELAY(5NS,11NS,17NS), + CHANGED(A5,0) & TRN_HL, DELAY(3NS,8NS,12NS), + TRN_ZH, DELAY(3NS,10NS,17NS), + TRN_ZL, DELAY(5NS,10NS,18NS), + TRN_HZ, DELAY(1NS,6NS,10NS), + TRN_LZ, DELAY(2NS,10NS,16NS), + DELAY(16NS,25NS,36NS) + ) + } + B6_B = { + CASE( + SEL_AB & A6=='0 & TRN_LH, DELAY(15NS,24NS,35NS), + CLOCK_AB & TRN_LH, DELAY(10NS,20NS,30NS), + SEL_AB & A6=='1 & TRN_LH, DELAY(8NS,17NS,25NS), + SEL_AB & A6=='0 & TRN_HL, DELAY(6NS,13NS,20NS), + SEL_AB & A6=='1 & TRN_HL, DELAY(5NS,13NS,20NS), + CHANGED(A6,0) & TRN_LH, DELAY(5NS,11NS,18NS), + CLOCK_AB & TRN_HL, DELAY(5NS,11NS,17NS), + CHANGED(A6,0) & TRN_HL, DELAY(3NS,8NS,12NS), + TRN_ZH, DELAY(3NS,10NS,17NS), + TRN_ZL, DELAY(5NS,10NS,18NS), + TRN_HZ, DELAY(1NS,6NS,10NS), + TRN_LZ, DELAY(2NS,10NS,16NS), + DELAY(16NS,25NS,36NS) + ) + } + B7_B = { + CASE( + SEL_AB & A7=='0 & TRN_LH, DELAY(15NS,24NS,35NS), + CLOCK_AB & TRN_LH, DELAY(10NS,20NS,30NS), + SEL_AB & A7=='1 & TRN_LH, DELAY(8NS,17NS,25NS), + SEL_AB & A7=='0 & TRN_HL, DELAY(6NS,13NS,20NS), + SEL_AB & A7=='1 & TRN_HL, DELAY(5NS,13NS,20NS), + CHANGED(A7,0) & TRN_LH, DELAY(5NS,11NS,18NS), + CLOCK_AB & TRN_HL, DELAY(5NS,11NS,17NS), + CHANGED(A7,0) & TRN_HL, DELAY(3NS,8NS,12NS), + TRN_ZH, DELAY(3NS,10NS,17NS), + TRN_ZL, DELAY(5NS,10NS,18NS), + TRN_HZ, DELAY(1NS,6NS,10NS), + TRN_LZ, DELAY(2NS,10NS,16NS), + DELAY(16NS,25NS,36NS) + ) + } + B8_B = { + CASE( + SEL_AB & A8=='0 & TRN_LH, DELAY(15NS,24NS,35NS), + CLOCK_AB & TRN_LH, DELAY(10NS,20NS,30NS), + SEL_AB & A8=='1 & TRN_LH, DELAY(8NS,17NS,25NS), + SEL_AB & A8=='0 & TRN_HL, DELAY(6NS,13NS,20NS), + SEL_AB & A8=='1 & TRN_HL, DELAY(5NS,13NS,20NS), + CHANGED(A8,0) & TRN_LH, DELAY(5NS,11NS,18NS), + CLOCK_AB & TRN_HL, DELAY(5NS,11NS,17NS), + CHANGED(A8,0) & TRN_HL, DELAY(3NS,8NS,12NS), + TRN_ZH, DELAY(3NS,10NS,17NS), + TRN_ZL, DELAY(5NS,10NS,18NS), + TRN_HZ, DELAY(1NS,6NS,10NS), + TRN_LZ, DELAY(2NS,10NS,16NS), + DELAY(16NS,25NS,36NS) + ) + } + FREQ: + NODE = CBA + MAXFREQ = 40MEG + FREQ: + NODE = CAB + MAXFREQ = 40MEG + WIDTH: + NODE = CBA + MIN_LO = 12.5NS + MIN_HI = 12.5NS + WIDTH: + NODE = CAB + MIN_LO = 12.5NS + MIN_HI = 12.5NS + SETUP_HOLD: + DATA(8) = A1 A2 A3 A4 A5 A6 A7 A8 + CLOCK LH = CAB + SETUPTIME = 10NS + SETUP_HOLD: + DATA(8) = B1 B2 B3 B4 B5 B6 B7 B8 + CLOCK LH = CBA + SETUPTIME = 10NS * .ENDS * *$ *------------------------------------------------------------------------- * 74ALS653 BUS TRANSCEIVERS AND REGISTERS OCTAL WITH OPEN-COLLECTOR OUTPUTS * * ALS/AS LOGIC DATA BOOK, 1986, TI * TC 09/07/92 REMODELED USING LOGICEXP, PINDLY, & CONSTRAINT DEVICES * * NOTE: ADDITIONAL LOGIC IS ADDED TO MODEL THE BIDIRECTIONAL PINS AND THE * FUNCTION OF GBABAR IN CONTROLLING THE OPEN-COLLECTOR A BUS. .SUBCKT 74ALS653 GBABAR_I GAB_I CBA_I SBA_I CAB_I SAB_I + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 U1 DFF(8) DPWR DGND $D_HI $D_HI CAB + A1_IO A2_IO A3_IO A4_IO A5_IO A6_IO A7_IO A8_IO + QB1 QB2 QB3 QB4 QB5 QB6 QB7 QB8 + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D0_EFF IO_ALS00 U2 DFF(8) DPWR DGND $D_HI $D_HI CBA + B1_IO B2_IO B3_IO B4_IO B5_IO B6_IO B7_IO B8_IO + QA1 QA2 QA3 QA4 QA5 QA6 QA7 QA8 + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D0_EFF IO_ALS00 U3 BUF3A(8) DPWR DGND + A1 A2 A3 A4 A5 A6 A7 A8 GBABAR + A1_IO A2_IO A3_IO A4_IO A5_IO A6_IO A7_IO A8_IO + D0_TGATE IO_ALS00 U4 BUF3A(8) DPWR DGND + A1_O A2_O A3_O A4_O A5_O A6_O A7_O A8_O IGBABAR + A1_IO A2_IO A3_IO A4_IO A5_IO A6_IO A7_IO A8_IO + D0_TGATE IO_ALS00 U5 BUF3A(8) DPWR DGND + B1_O B2_O B3_O B4_O B5_O B6_O B7_O B8_O GAB + B1_IO B2_IO B3_IO B4_IO B5_IO B6_IO B7_IO B8_IO + D0_TGATE IO_ALS00 U6 BUF3A(8) DPWR DGND + B1 B2 B3 B4 B5 B6 B7 B8 IGAB + B1_IO B2_IO B3_IO B4_IO B5_IO B6_IO B7_IO B8_IO + D0_TGATE IO_ALS00 UALS653LOG LOGICEXP(38,40) DPWR DGND + GBABAR_I GAB_I CBA_I SBA_I CAB_I SAB_I + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + QA1 QA2 QA3 QA4 QA5 QA6 QA7 QA8 QB1 QB2 QB3 QB4 QB5 QB6 QB7 QB8 + GBABAR GAB CBA SBA CAB SAB A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 + A1_O A2_O A3_O A4_O A5_O A6_O A7_O A8_O + B1_O B2_O B3_O B4_O B5_O B6_O B7_O B8_O IGAB IGBABAR + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} + LOGIC: + GBABAR = { GBABAR_I } + GAB = { GAB_I } + CBA = { CBA_I } + SBA = { SBA_I } + CAB = { CAB_I } + SAB = { SAB_I } + A1 = { A1_B } + A2 = { A2_B } + A3 = { A3_B } + A4 = { A4_B } + A5 = { A5_B } + A6 = { A6_B } + A7 = { A7_B } + A8 = { A8_B } + B1 = { B1_B } + B2 = { B2_B } + B3 = { B3_B } + B4 = { B4_B } + B5 = { B5_B } + B6 = { B6_B } + B7 = { B7_B } + B8 = { B8_B } + ISAB = { ~SAB } + ISBA = { ~SBA } + IGAB = { ~GAB } + IGBABAR = { ~GBABAR } + A1_O = { ~((SBA & QA1) | (ISBA & B1)) | GBABAR } + A2_O = { ~((SBA & QA2) | (ISBA & B2)) | GBABAR } + A3_O = { ~((SBA & QA3) | (ISBA & B3)) | GBABAR } + A4_O = { ~((SBA & QA4) | (ISBA & B4)) | GBABAR } + A5_O = { ~((SBA & QA5) | (ISBA & B5)) | GBABAR } + A6_O = { ~((SBA & QA6) | (ISBA & B6)) | GBABAR } + A7_O = { ~((SBA & QA7) | (ISBA & B7)) | GBABAR } + A8_O = { ~((SBA & QA8) | (ISBA & B8)) | GBABAR } + B1_O = { ~((SAB & QB1) | (ISAB & A1)) } + B2_O = { ~((SAB & QB2) | (ISAB & A2)) } + B3_O = { ~((SAB & QB3) | (ISAB & A3)) } + B4_O = { ~((SAB & QB4) | (ISAB & A4)) } + B5_O = { ~((SAB & QB5) | (ISAB & A5)) } + B6_O = { ~((SAB & QB6) | (ISAB & A6)) } + B7_O = { ~((SAB & QB7) | (ISAB & A7)) } + B8_O = { ~((SAB & QB8) | (ISAB & A8)) } UALS653DLY_1 PINDLY(8,0,11) DPWR DGND + A1_O A2_O A3_O A4_O A5_O A6_O A7_O A8_O + GBABAR CBA SBA B1 B2 B3 B4 B5 B6 B7 B8 + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + IO_ALS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + CLOCK_BA = { CHANGED_LH(CBA,0) } + ENABLE = { CHANGED(GBABAR,0) } + SEL_BA = { CHANGED(SBA,0) } + BUS_B = { CHANGED(B1,0) | CHANGED(B2,0) | CHANGED(B3,0) | CHANGED(B4,0) | + CHANGED(B5,0) | CHANGED(B6,0) | CHANGED(B7,0) | CHANGED(B8,0) } + PINDLY: + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B = { + CASE( + CLOCK_BA & TRN_LH, DELAY(16NS,30NS,64NS), + SEL_BA & TRN_LH, DELAY(19NS,35NS,62NS), + BUS_B & TRN_LH, DELAY(12NS,20NS,56NS), + ENABLE & TRN_LH, DELAY(6NS,17NS,30NS), + SEL_BA & TRN_HL, DELAY(5NS,15NS,25NS), + ENABLE & TRN_HL, DELAY(6NS,14NS,24NS), + CLOCK_BA & TRN_HL, DELAY(6NS,11NS,22NS), + BUS_B & TRN_HL, DELAY(2NS,10NS,15NS), + DELAY(17NS,31NS,65NS) + ) + } UALS653DLY_2 PINDLY(8,1,10) DPWR DGND + B1_IO B2_IO B3_IO B4_IO B5_IO B6_IO B7_IO B8_IO + GAB + CAB SAB A1 A2 A3 A4 A5 A6 A7 A8 + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + CLOCK_AB = { CHANGED_LH(CAB,0) } + SEL_AB = { CHANGED(SAB,0) } + TRISTATE: + ENABLE HI GAB + B1_B = { + CASE( + SEL_AB & A1=='0 & TRN_LH, DELAY(15NS,24NS,35NS), + CLOCK_AB & TRN_LH, DELAY(10NS,20NS,30NS), + CHANGED(A1,0) & TRN_LH, DELAY(5NS,11NS,18NS), + CLOCK_AB & TRN_HL, DELAY(5NS,11NS,17NS), + CHANGED(A1,0) & TRN_HL, DELAY(2NS,10NS,15NS), + SEL_AB & A1=='0 & TRN_HL, DELAY(6NS,13NS,22NS), + SEL_AB & A1=='1 & TRN_HL, DELAY(6NS,13NS,22NS), + SEL_AB & A1=='1 & TRN_LH, DELAY(8NS,18NS,25NS), + TRN_ZH, DELAY(8NS,15NS,22NS), + TRN_ZL, DELAY(6NS,13NS,22NS), + TRN_HZ, DELAY(1NS,8NS,14NS), + TRN_LZ, DELAY(2NS,10NS,16NS), + DELAY(16NS,25NS,36NS) + ) + } + B2_B = { + CASE( + SEL_AB & A2=='0 & TRN_LH, DELAY(15NS,24NS,35NS), + CLOCK_AB & TRN_LH, DELAY(10NS,20NS,30NS), + CHANGED(A2,0) & TRN_LH, DELAY(5NS,11NS,18NS), + CLOCK_AB & TRN_HL, DELAY(5NS,11NS,17NS), + CHANGED(A2,0) & TRN_HL, DELAY(2NS,10NS,15NS), + SEL_AB & A2=='0 & TRN_HL, DELAY(6NS,13NS,22NS), + SEL_AB & A2=='1 & TRN_HL, DELAY(6NS,13NS,22NS), + SEL_AB & A2=='1 & TRN_LH, DELAY(8NS,18NS,25NS), + TRN_ZH, DELAY(8NS,15NS,22NS), + TRN_ZL, DELAY(6NS,13NS,22NS), + TRN_HZ, DELAY(1NS,8NS,14NS), + TRN_LZ, DELAY(2NS,10NS,16NS), + DELAY(16NS,25NS,36NS) + ) + } + B3_B = { + CASE( + SEL_AB & A3=='0 & TRN_LH, DELAY(15NS,24NS,35NS), + CLOCK_AB & TRN_LH, DELAY(10NS,20NS,30NS), + CHANGED(A3,0) & TRN_LH, DELAY(5NS,11NS,18NS), + CLOCK_AB & TRN_HL, DELAY(5NS,11NS,17NS), + CHANGED(A3,0) & TRN_HL, DELAY(2NS,10NS,15NS), + SEL_AB & A3=='0 & TRN_HL, DELAY(6NS,13NS,22NS), + SEL_AB & A3=='1 & TRN_HL, DELAY(6NS,13NS,22NS), + SEL_AB & A3=='1 & TRN_LH, DELAY(8NS,18NS,25NS), + TRN_ZH, DELAY(8NS,15NS,22NS), + TRN_ZL, DELAY(6NS,13NS,22NS), + TRN_HZ, DELAY(1NS,8NS,14NS), + TRN_LZ, DELAY(2NS,10NS,16NS), + DELAY(16NS,25NS,36NS) + ) + } + B4_B = { + CASE( + SEL_AB & A4=='0 & TRN_LH, DELAY(15NS,24NS,35NS), + CLOCK_AB & TRN_LH, DELAY(10NS,20NS,30NS), + CHANGED(A4,0) & TRN_LH, DELAY(5NS,11NS,18NS), + CLOCK_AB & TRN_HL, DELAY(5NS,11NS,17NS), + CHANGED(A4,0) & TRN_HL, DELAY(2NS,10NS,15NS), + SEL_AB & A4=='0 & TRN_HL, DELAY(6NS,13NS,22NS), + SEL_AB & A4=='1 & TRN_HL, DELAY(6NS,13NS,22NS), + SEL_AB & A4=='1 & TRN_LH, DELAY(8NS,18NS,25NS), + TRN_ZH, DELAY(8NS,15NS,22NS), + TRN_ZL, DELAY(6NS,13NS,22NS), + TRN_HZ, DELAY(1NS,8NS,14NS), + TRN_LZ, DELAY(2NS,10NS,16NS), + DELAY(16NS,25NS,36NS) + ) + } + B5_B = { + CASE( + SEL_AB & A5=='0 & TRN_LH, DELAY(15NS,24NS,35NS), + CLOCK_AB & TRN_LH, DELAY(10NS,20NS,30NS), + CHANGED(A5,0) & TRN_LH, DELAY(5NS,11NS,18NS), + CLOCK_AB & TRN_HL, DELAY(5NS,11NS,17NS), + CHANGED(A5,0) & TRN_HL, DELAY(2NS,10NS,15NS), + SEL_AB & A5=='0 & TRN_HL, DELAY(6NS,13NS,22NS), + SEL_AB & A5=='1 & TRN_HL, DELAY(6NS,13NS,22NS), + SEL_AB & A5=='1 & TRN_LH, DELAY(8NS,18NS,25NS), + TRN_ZH, DELAY(8NS,15NS,22NS), + TRN_ZL, DELAY(6NS,13NS,22NS), + TRN_HZ, DELAY(1NS,8NS,14NS), + TRN_LZ, DELAY(2NS,10NS,16NS), + DELAY(16NS,25NS,36NS) + ) + } + B6_B = { + CASE( + SEL_AB & A6=='0 & TRN_LH, DELAY(15NS,24NS,35NS), + CLOCK_AB & TRN_LH, DELAY(10NS,20NS,30NS), + CHANGED(A6,0) & TRN_LH, DELAY(5NS,11NS,18NS), + CLOCK_AB & TRN_HL, DELAY(5NS,11NS,17NS), + CHANGED(A6,0) & TRN_HL, DELAY(2NS,10NS,15NS), + SEL_AB & A6=='0 & TRN_HL, DELAY(6NS,13NS,22NS), + SEL_AB & A6=='1 & TRN_HL, DELAY(6NS,13NS,22NS), + SEL_AB & A6=='1 & TRN_LH, DELAY(8NS,18NS,25NS), + TRN_ZH, DELAY(8NS,15NS,22NS), + TRN_ZL, DELAY(6NS,13NS,22NS), + TRN_HZ, DELAY(1NS,8NS,14NS), + TRN_LZ, DELAY(2NS,10NS,16NS), + DELAY(16NS,25NS,36NS) + ) + } + B7_B = { + CASE( + SEL_AB & A7=='0 & TRN_LH, DELAY(15NS,24NS,35NS), + CLOCK_AB & TRN_LH, DELAY(10NS,20NS,30NS), + CHANGED(A7,0) & TRN_LH, DELAY(5NS,11NS,18NS), + CLOCK_AB & TRN_HL, DELAY(5NS,11NS,17NS), + CHANGED(A7,0) & TRN_HL, DELAY(2NS,10NS,15NS), + SEL_AB & A7=='0 & TRN_HL, DELAY(6NS,13NS,22NS), + SEL_AB & A7=='1 & TRN_HL, DELAY(6NS,13NS,22NS), + SEL_AB & A7=='1 & TRN_LH, DELAY(8NS,18NS,25NS), + TRN_ZH, DELAY(8NS,15NS,22NS), + TRN_ZL, DELAY(6NS,13NS,22NS), + TRN_HZ, DELAY(1NS,8NS,14NS), + TRN_LZ, DELAY(2NS,10NS,16NS), + DELAY(16NS,25NS,36NS) + ) + } + B8_B = { + CASE( + SEL_AB & A8=='0 & TRN_LH, DELAY(15NS,24NS,35NS), + CLOCK_AB & TRN_LH, DELAY(10NS,20NS,30NS), + CHANGED(A8,0) & TRN_LH, DELAY(5NS,11NS,18NS), + CLOCK_AB & TRN_HL, DELAY(5NS,11NS,17NS), + CHANGED(A8,0) & TRN_HL, DELAY(2NS,10NS,15NS), + SEL_AB & A8=='0 & TRN_HL, DELAY(6NS,13NS,22NS), + SEL_AB & A8=='1 & TRN_HL, DELAY(6NS,13NS,22NS), + SEL_AB & A8=='1 & TRN_LH, DELAY(8NS,18NS,25NS), + TRN_ZH, DELAY(8NS,15NS,22NS), + TRN_ZL, DELAY(6NS,13NS,22NS), + TRN_HZ, DELAY(1NS,8NS,14NS), + TRN_LZ, DELAY(2NS,10NS,16NS), + DELAY(16NS,25NS,36NS) + ) + } UALS653CON CONSTRAINT(18) DPWR DGND + CAB CBA A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 + IO_ALS00 + FREQ: + NODE = CAB + MAXFREQ = 35MEG + FREQ: + NODE = CBA + MAXFREQ = 35MEG + WIDTH: + NODE = CAB + MIN_LO = 14.5NS + MIN_HI = 14.5NS + WIDTH: + NODE = CBA + MIN_LO = 14.5NS + MIN_HI = 14.5NS + SETUP_HOLD: + DATA(8) = A1 A2 A3 A4 A5 A6 A7 A8 + CLOCK LH = CAB + SETUPTIME = 10NS + SETUP_HOLD: + DATA(8) = B1 B2 B3 B4 B5 B6 B7 B8 + CLOCK LH = CBA + SETUPTIME = 10NS .ENDS *$ *------------------------------------------------------------------------- * 74ALS654 BUS TRANSCEIVERS AND REGISTERS OCTAL WITH OPEN-COLLECTOR OUTPUTS * * ALS/AS LOGIC DATA BOOK, 1986, TI * TC 09/10/92 REMODELED USING LOGICEXP, PINDLY, & CONSTRAINT DEVICES * * NOTE: ADDITIONAL LOGIC IS ADDED TO MODEL THE BIDIRECTIONAL PINS AND THE * FUNCTION OF GBABAR IN CONTROLLING THE OPEN-COLLECTOR A BUS. .SUBCKT 74ALS654 GBABAR_I GAB_I CBA_I SBA_I CAB_I SAB_I + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 U1 DFF(8) DPWR DGND $D_HI $D_HI CAB + A1_IO A2_IO A3_IO A4_IO A5_IO A6_IO A7_IO A8_IO + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + QB1BAR QB2BAR QB3BAR QB4BAR QB5BAR QB6BAR QB7BAR QB8BAR + D0_EFF IO_ALS00 U2 DFF(8) DPWR DGND $D_HI $D_HI CBA + B1_IO B2_IO B3_IO B4_IO B5_IO B6_IO B7_IO B8_IO + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + QA1BAR QA2BAR QA3BAR QA4BAR QA5BAR QA6BAR QA7BAR QA8BAR + D0_EFF IO_ALS00 U3 BUF3A(8) DPWR DGND + A1 A2 A3 A4 A5 A6 A7 A8 GBABAR + A1_IO A2_IO A3_IO A4_IO A5_IO A6_IO A7_IO A8_IO + D0_TGATE IO_ALS00 U4 BUF3A(8) DPWR DGND + A1_O A2_O A3_O A4_O A5_O A6_O A7_O A8_O IGBABAR + A1_IO A2_IO A3_IO A4_IO A5_IO A6_IO A7_IO A8_IO + D0_TGATE IO_ALS00 U5 BUF3A(8) DPWR DGND + B1_O B2_O B3_O B4_O B5_O B6_O B7_O B8_O GAB + B1_IO B2_IO B3_IO B4_IO B5_IO B6_IO B7_IO B8_IO + D0_TGATE IO_ALS00 U6 BUF3A(8) DPWR DGND + B1 B2 B3 B4 B5 B6 B7 B8 IGAB + B1_IO B2_IO B3_IO B4_IO B5_IO B6_IO B7_IO B8_IO + D0_TGATE IO_ALS00 UALS654LOG LOGICEXP(38,40) DPWR DGND + GBABAR_I GAB_I CBA_I SBA_I CAB_I SAB_I + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + QA1BAR QA2BAR QA3BAR QA4BAR QA5BAR QA6BAR QA7BAR QA8BAR + QB1BAR QB2BAR QB3BAR QB4BAR QB5BAR QB6BAR QB7BAR QB8BAR + GBABAR GAB CBA SBA CAB SAB A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 + A1_O A2_O A3_O A4_O A5_O A6_O A7_O A8_O + B1_O B2_O B3_O B4_O B5_O B6_O B7_O B8_O IGAB IGBABAR + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} + LOGIC: + GBABAR = { GBABAR_I } + GAB = { GAB_I } + CBA = { CBA_I } + SBA = { SBA_I } + CAB = { CAB_I } + SAB = { SAB_I } + A1 = { A1_B } + A2 = { A2_B } + A3 = { A3_B } + A4 = { A4_B } + A5 = { A5_B } + A6 = { A6_B } + A7 = { A7_B } + A8 = { A8_B } + B1 = { B1_B } + B2 = { B2_B } + B3 = { B3_B } + B4 = { B4_B } + B5 = { B5_B } + B6 = { B6_B } + B7 = { B7_B } + B8 = { B8_B } + ISAB = { ~SAB } + ISBA = { ~SBA } + IGAB = { ~GAB } + IGBABAR = { ~GBABAR } + A1_O = { ~((SBA & QA1BAR) | (ISBA & ~B1)) | GBABAR } + A2_O = { ~((SBA & QA2BAR) | (ISBA & ~B2)) | GBABAR } + A3_O = { ~((SBA & QA3BAR) | (ISBA & ~B3)) | GBABAR } + A4_O = { ~((SBA & QA4BAR) | (ISBA & ~B4)) | GBABAR } + A5_O = { ~((SBA & QA5BAR) | (ISBA & ~B5)) | GBABAR } + A6_O = { ~((SBA & QA6BAR) | (ISBA & ~B6)) | GBABAR } + A7_O = { ~((SBA & QA7BAR) | (ISBA & ~B7)) | GBABAR } + A8_O = { ~((SBA & QA8BAR) | (ISBA & ~B8)) | GBABAR } + B1_O = { ~((SAB & QB1BAR) | (ISAB & ~A1)) } + B2_O = { ~((SAB & QB2BAR) | (ISAB & ~A2)) } + B3_O = { ~((SAB & QB3BAR) | (ISAB & ~A3)) } + B4_O = { ~((SAB & QB4BAR) | (ISAB & ~A4)) } + B5_O = { ~((SAB & QB5BAR) | (ISAB & ~A5)) } + B6_O = { ~((SAB & QB6BAR) | (ISAB & ~A6)) } + B7_O = { ~((SAB & QB7BAR) | (ISAB & ~A7)) } + B8_O = { ~((SAB & QB8BAR) | (ISAB & ~A8)) } UALS654DLY_1 PINDLY(8,0,11) DPWR DGND + A1_O A2_O A3_O A4_O A5_O A6_O A7_O A8_O + GBABAR CBA SBA B1 B2 B3 B4 B5 B6 B7 B8 + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + IO_ALS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + CLOCK_BA = { CHANGED_LH(CBA,0) } + ENABLE = { CHANGED(GBABAR,0) } + SEL_BA = { CHANGED(SBA,0) } + BUS_B = { CHANGED(B1,0) | CHANGED(B2,0) | CHANGED(B3,0) | CHANGED(B4,0) | + CHANGED(B5,0) | CHANGED(B6,0) | CHANGED(B7,0) | CHANGED(B8,0) } + PINDLY: + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B = { + CASE( + CLOCK_BA & TRN_LH, DELAY(16NS,30NS,64NS), + SEL_BA & TRN_LH, DELAY(19NS,35NS,62NS), + BUS_B & TRN_LH, DELAY(12NS,20NS,56NS), + ENABLE & TRN_LH, DELAY(6NS,17NS,30NS), + SEL_BA & TRN_HL, DELAY(5NS,15NS,25NS), + ENABLE & TRN_HL, DELAY(6NS,14NS,24NS), + CLOCK_BA & TRN_HL, DELAY(6NS,11NS,22NS), + BUS_B & TRN_HL, DELAY(2NS,10NS,15NS), + DELAY(17NS,31NS,65NS) + ) + } UALS654DLY_2 PINDLY(8,1,10) DPWR DGND + B1_IO B2_IO B3_IO B4_IO B5_IO B6_IO B7_IO B8_IO + GAB + CAB SAB A1 A2 A3 A4 A5 A6 A7 A8 + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + CLOCK_AB = { CHANGED_LH(CAB,0) } + SEL_AB = { CHANGED(SAB,0) } + TRISTATE: + ENABLE HI GAB + B1_B = { + CASE( + SEL_AB & A1=='0 & TRN_LH, DELAY(15NS,24NS,35NS), + CLOCK_AB & TRN_LH, DELAY(10NS,20NS,30NS), + SEL_AB & A1=='1 & TRN_LH, DELAY(8NS,18NS,25NS), + SEL_AB & A1=='1 & TRN_HL, DELAY(6NS,13NS,22NS), + SEL_AB & A1=='0 & TRN_HL, DELAY(6NS,13NS,22NS), + CHANGED(A1,0) & TRN_LH, DELAY(5NS,11NS,18NS), + CLOCK_AB & TRN_HL, DELAY(5NS,11NS,17NS), + CHANGED(A1,0) & TRN_HL, DELAY(2NS,10NS,15NS), + TRN_ZH, DELAY(8NS,15NS,22NS), + TRN_ZL, DELAY(6NS,13NS,22NS), + TRN_HZ, DELAY(1NS,8NS,14NS), + TRN_LZ, DELAY(2NS,10NS,16NS), + DELAY(16NS,25NS,36NS) + ) + } + B2_B = { + CASE( + SEL_AB & A2=='0 & TRN_LH, DELAY(15NS,24NS,35NS), + CLOCK_AB & TRN_LH, DELAY(10NS,20NS,30NS), + SEL_AB & A2=='1 & TRN_LH, DELAY(8NS,18NS,25NS), + SEL_AB & A2=='1 & TRN_HL, DELAY(6NS,13NS,22NS), + SEL_AB & A2=='0 & TRN_HL, DELAY(6NS,13NS,22NS), + CHANGED(A2,0) & TRN_LH, DELAY(5NS,11NS,18NS), + CLOCK_AB & TRN_HL, DELAY(5NS,11NS,17NS), + CHANGED(A2,0) & TRN_HL, DELAY(2NS,10NS,15NS), + TRN_ZH, DELAY(8NS,15NS,22NS), + TRN_ZL, DELAY(6NS,13NS,22NS), + TRN_HZ, DELAY(1NS,8NS,14NS), + TRN_LZ, DELAY(2NS,10NS,16NS), + DELAY(16NS,25NS,36NS) + ) + } + B3_B = { + CASE( + SEL_AB & A3=='0 & TRN_LH, DELAY(15NS,24NS,35NS), + CLOCK_AB & TRN_LH, DELAY(10NS,20NS,30NS), + SEL_AB & A3=='1 & TRN_LH, DELAY(8NS,18NS,25NS), + SEL_AB & A3=='1 & TRN_HL, DELAY(6NS,13NS,22NS), + SEL_AB & A3=='0 & TRN_HL, DELAY(6NS,13NS,22NS), + CHANGED(A3,0) & TRN_LH, DELAY(5NS,11NS,18NS), + CLOCK_AB & TRN_HL, DELAY(5NS,11NS,17NS), + CHANGED(A3,0) & TRN_HL, DELAY(2NS,10NS,15NS), + TRN_ZH, DELAY(8NS,15NS,22NS), + TRN_ZL, DELAY(6NS,13NS,22NS), + TRN_HZ, DELAY(1NS,8NS,14NS), + TRN_LZ, DELAY(2NS,10NS,16NS), + DELAY(16NS,25NS,36NS) + ) + } + B4_B = { + CASE( + SEL_AB & A4=='0 & TRN_LH, DELAY(15NS,24NS,35NS), + CLOCK_AB & TRN_LH, DELAY(10NS,20NS,30NS), + SEL_AB & A4=='1 & TRN_LH, DELAY(8NS,18NS,25NS), + SEL_AB & A4=='1 & TRN_HL, DELAY(6NS,13NS,22NS), + SEL_AB & A4=='0 & TRN_HL, DELAY(6NS,13NS,22NS), + CHANGED(A4,0) & TRN_LH, DELAY(5NS,11NS,18NS), + CLOCK_AB & TRN_HL, DELAY(5NS,11NS,17NS), + CHANGED(A4,0) & TRN_HL, DELAY(2NS,10NS,15NS), + TRN_ZH, DELAY(8NS,15NS,22NS), + TRN_ZL, DELAY(6NS,13NS,22NS), + TRN_HZ, DELAY(1NS,8NS,14NS), + TRN_LZ, DELAY(2NS,10NS,16NS), + DELAY(16NS,25NS,36NS) + ) + } + B5_B = { + CASE( + SEL_AB & A5=='0 & TRN_LH, DELAY(15NS,24NS,35NS), + CLOCK_AB & TRN_LH, DELAY(10NS,20NS,30NS), + SEL_AB & A5=='1 & TRN_LH, DELAY(8NS,18NS,25NS), + SEL_AB & A5=='1 & TRN_HL, DELAY(6NS,13NS,22NS), + SEL_AB & A5=='0 & TRN_HL, DELAY(6NS,13NS,22NS), + CHANGED(A5,0) & TRN_LH, DELAY(5NS,11NS,18NS), + CLOCK_AB & TRN_HL, DELAY(5NS,11NS,17NS), + CHANGED(A5,0) & TRN_HL, DELAY(2NS,10NS,15NS), + TRN_ZH, DELAY(8NS,15NS,22NS), + TRN_ZL, DELAY(6NS,13NS,22NS), + TRN_HZ, DELAY(1NS,8NS,14NS), + TRN_LZ, DELAY(2NS,10NS,16NS), + DELAY(16NS,25NS,36NS) + ) + } + B6_B = { + CASE( + SEL_AB & A6=='0 & TRN_LH, DELAY(15NS,24NS,35NS), + CLOCK_AB & TRN_LH, DELAY(10NS,20NS,30NS), + SEL_AB & A6=='1 & TRN_LH, DELAY(8NS,18NS,25NS), + SEL_AB & A6=='1 & TRN_HL, DELAY(6NS,13NS,22NS), + SEL_AB & A6=='0 & TRN_HL, DELAY(6NS,13NS,22NS), + CHANGED(A6,0) & TRN_LH, DELAY(5NS,11NS,18NS), + CLOCK_AB & TRN_HL, DELAY(5NS,11NS,17NS), + CHANGED(A6,0) & TRN_HL, DELAY(2NS,10NS,15NS), + TRN_ZH, DELAY(8NS,15NS,22NS), + TRN_ZL, DELAY(6NS,13NS,22NS), + TRN_HZ, DELAY(1NS,8NS,14NS), + TRN_LZ, DELAY(2NS,10NS,16NS), + DELAY(16NS,25NS,36NS) + ) + } + B7_B = { + CASE( + SEL_AB & A7=='0 & TRN_LH, DELAY(15NS,24NS,35NS), + CLOCK_AB & TRN_LH, DELAY(10NS,20NS,30NS), + SEL_AB & A7=='1 & TRN_LH, DELAY(8NS,18NS,25NS), + SEL_AB & A7=='1 & TRN_HL, DELAY(6NS,13NS,22NS), + SEL_AB & A7=='0 & TRN_HL, DELAY(6NS,13NS,22NS), + CHANGED(A7,0) & TRN_LH, DELAY(5NS,11NS,18NS), + CLOCK_AB & TRN_HL, DELAY(5NS,11NS,17NS), + CHANGED(A7,0) & TRN_HL, DELAY(2NS,10NS,15NS), + TRN_ZH, DELAY(8NS,15NS,22NS), + TRN_ZL, DELAY(6NS,13NS,22NS), + TRN_HZ, DELAY(1NS,8NS,14NS), + TRN_LZ, DELAY(2NS,10NS,16NS), + DELAY(16NS,25NS,36NS) + ) + } + B8_B = { + CASE( + SEL_AB & A8=='0 & TRN_LH, DELAY(15NS,24NS,35NS), + CLOCK_AB & TRN_LH, DELAY(10NS,20NS,30NS), + SEL_AB & A8=='1 & TRN_LH, DELAY(8NS,18NS,25NS), + SEL_AB & A8=='1 & TRN_HL, DELAY(6NS,13NS,22NS), + SEL_AB & A8=='0 & TRN_HL, DELAY(6NS,13NS,22NS), + CHANGED(A8,0) & TRN_LH, DELAY(5NS,11NS,18NS), + CLOCK_AB & TRN_HL, DELAY(5NS,11NS,17NS), + CHANGED(A8,0) & TRN_HL, DELAY(2NS,10NS,15NS), + TRN_ZH, DELAY(8NS,15NS,22NS), + TRN_ZL, DELAY(6NS,13NS,22NS), + TRN_HZ, DELAY(1NS,8NS,14NS), + TRN_LZ, DELAY(2NS,10NS,16NS), + DELAY(16NS,25NS,36NS) + ) + } UALS654CON CONSTRAINT(18) DPWR DGND + CAB CBA A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 + IO_ALS00 + FREQ: + NODE = CAB + MAXFREQ = 35MEG + FREQ: + NODE = CBA + MAXFREQ = 35MEG + WIDTH: + NODE = CAB + MIN_LO = 14.5NS + MIN_HI = 14.5NS + WIDTH: + NODE = CBA + MIN_LO = 14.5NS + MIN_HI = 14.5NS + SETUP_HOLD: + DATA(8) = A1 A2 A3 A4 A5 A6 A7 A8 + CLOCK LH = CAB + SETUPTIME = 10NS + SETUP_HOLD: + DATA(8) = B1 B2 B3 B4 B5 B6 B7 B8 + CLOCK LH = CBA + SETUPTIME = 10NS .ENDS *$ *------------------------------------------------------------------------- * 74ALS666 8-bit D-TYPE Transparent Read-Back Latches with 3-STATE Outputs * * The ALS/AS Data Book, 1986, TI * atl 9/8/89 Update interface and model names * .subckt 74ALS666 OE1BAR OE2BAR OERBBAR PREBAR CLRBAR C 1D 2D 3D 4D 5D 6D 7D + 8D 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UOE nor(2) DPWR DGND + OE1BAR OE2BAR OE + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} UOERB inv DPWR DGND + OERBBAR OERB + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} UQI dltch(8) DPWR DGND + PREBAR CLRBAR C + 1D 2D 3D 4D 5D 6D 7D 8D + 1QI 2QI 3QI 4QI 5QI 6QI 7QI 8QI + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D_ALS666_1 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UQ buf3a(8) DPWR DGND + 1QI 2QI 3QI 4QI 5QI 6QI 7QI 8QI + OE + 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q + D_ALS666_2 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UD buf3a(8) DPWR DGND + 1QI 2QI 3QI 4QI 5QI 6QI 7QI 8QI + OERB + 1D 2D 3D 4D 5D 6D 7D 8D + D_ALS666_3 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS666_1 ugff ( + twghmn=10ns twpclmn=10ns + tsudgmn=10ns thdgmn=5ns + tppcqlhmn=4ns tppcqlhmx=8ns + tppcqhlmn=5ns tppcqhlmx=11ns + tpgqlhmn=3ns tpgqlhmx=7ns + tpgqhlmn=4ns tpgqhlmx=9ns + ) .model D_ALS666_2 utgate ( + tplhmn=3ns tplhmx=14ns + tphlmn=4ns tphlmx=18ns + tpzhmn=4ns tpzhmx=21ns + tpzlmn=4ns tpzlmx=21ns + tphzmn=1ns tphzmx=14ns + tplzmn=1ns tplzmx=14ns + ) .model D_ALS666_3 utgate ( + tplhmn=5ns tplhmx=20ns + tphlmn=6ns tphlmx=21ns + tpzhmn=4ns tpzhmx=21ns + tpzlmn=4ns tpzlmx=21ns + tphzmn=1ns tphzmx=14ns + tplzmn=1ns tplzmx=14ns + ) *$ *------------------------------------------------------------------------- * 74ALS667 8-bit D-TYPE Transparent Read-Back Latches with 3-STATE Outputs * * The ALS/AS Data Book, 1986, TI * atl 9/8/89 Update interface and model names * .subckt 74ALS667 OE1BAR OE2BAR OERBBAR PREBAR CLRBAR C 1D 2D 3D 4D 5D 6D 7D + 8D 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UOE nor(2) DPWR DGND + OE1BAR OE2BAR OE + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} UOERB inv DPWR DGND + OERBBAR OERB + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} UQI dltch(8) DPWR DGND + PREBAR CLRBAR C + 1D 2D 3D 4D 5D 6D 7D 8D + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + 1QI 2QI 3QI 4QI 5QI 6QI 7QI 8QI + D_ALS667_1 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UQ buf3a(8) DPWR DGND + 1QI 2QI 3QI 4QI 5QI 6QI 7QI 8QI + OE + 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q + D_ALS667_2 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UD inv3a(8) DPWR DGND + 1QI 2QI 3QI 4QI 5QI 6QI 7QI 8QI + OERB + 1D 2D 3D 4D 5D 6D 7D 8D + D_ALS667_3 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS667_1 ugff ( + twghmn=10ns twpclmn=10ns + tsudgmn=10ns thdgmn=5ns + tppcqlhmn=1ns tppcqlhmx=4ns + tppcqhlmn=4ns tppcqhlmx=10ns + tpgqlhmn=3ns tpgqlhmx=8ns + tpgqhlmn=3ns tpgqhlmx=7ns + ) .model D_ALS667_2 utgate ( + tplhmn=6ns tplhmx=20ns + tphlmn=4ns tphlmx=15ns + tpzhmn=4ns tpzhmx=21ns + tpzlmn=4ns tpzlmx=21ns + tphzmn=1ns tphzmx=14ns + tplzmn=1ns tplzmx=14ns + ) .model D_ALS667_3 utgate ( + tplhmn=5ns tplhmx=18ns + tphlmn=7ns tphlmx=22ns + tpzhmn=4ns tpzhmx=21ns + tpzlmn=4ns tpzlmx=21ns + tphzmn=1ns tphzmx=14ns + tplzmn=1ns tplzmx=14ns + ) * *$ *------------------------------------------------------------------------- * 74ALS677A 12-BIT ADDRESS COMPARATORS * * ALS/AS LOGIC CIRCUITS DATA BOOK, 1986, TI * NH 8/19/92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74ALS677A A1_I A2_I A3_I A4_I A5_I A6_I A7_I A8_I A9_I A10_I A11_I A12_I + A13_I A14_I A15_I A16_I GBAR_I P3_I P2_I P1_I P0_I Y_O + OPTIONAL: DPWR = $G_DPWR DGND = $G_DGND + PARAMS: MNTYMXDLY = 0 IO_LEVEL = 0 * UALS677ALOG LOGICEXP(21,22) DPWR DGND + A1_I A2_I A3_I A4_I A5_I A6_I A7_I A8_I A9_I A10_I A11_I A12_I A13_I A14_I + A15_I A16_I P0_I P1_I P2_I P3_I GBAR_I + A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 P0 P1 P2 P3 GBAR Y + D0_GATE IO_ALS00 IO_LEVEL = {IO_LEVEL} + + LOGIC: + A1 = { A1_I } + A2 = { A2_I } + A3 = { A3_I } + A4 = { A4_I } + A5 = { A5_I } + A6 = { A6_I } + A7 = { A7_I } + A8 = { A8_I } + A9 = { A9_I } + A10 = { A10_I } + A11 = { A11_I } + A12 = { A12_I } + A13 = { A13_I } + A14 = { A14_I } + A15 = { A15_I } + A16 = { A16_I } + P0 = { P0_I } + P1 = { P1_I } + P2 = { P2_I } + P3 = { P3_I } + GBAR = { GBAR_I } + * INTERMEDIATE TERMS + P0BAR = { ~P0 } + P1BAR = { ~P1 } + P2BAR = { ~P2 } + P3BAR = { ~P3 } + P2P3 = { P2BAR & P3BAR } + P1P2P3 = { P1BAR & P2P3 } + OUT1 = { ~(P0BAR & P1P2P3) ^ A1 } + OUT2 = { ~(P1BAR & P2P3) ^ A2 } + OUT3 = { ~((P0BAR & P2P3) | P1P2P3) ^ A3 } + OUT4 = { ~P2P3 ^ A4 } + OUT5 = { ~((P0BAR & P1BAR & P3BAR) | P2P3) ^ A5 } + OUT6 = { ~(P2P3 | (P1BAR & P3BAR)) ^ A6 } + OUT7 = { ~((P1BAR & P3BAR) | P2P3 | (P0BAR & P3BAR)) ^ A7 } + OUT8 = { ~P3BAR ^ A8 } + OUT9 = { ~((P0BAR & P1BAR & P2BAR) | P3BAR) ^ A9 } + OUT10 = { ~((P1BAR & P2BAR) | P3BAR) ^ A10 } + OUT11 = { ~((P0BAR & P2BAR) | (P1BAR & P2BAR) | P3BAR) ^ A11 } + OUT12 = { ~(P2BAR | P3BAR) ^ A12 } + OUT13 = { ~((P0BAR & P1BAR) | P2BAR | P3BAR) ^ A13 } + OUT14 = { ~(P1BAR | P2BAR | P3BAR) ^ A14 } + OUT15 = { ~(P0BAR | P1BAR | P2BAR | P3BAR) ^ A15 } + * OUTPUT + Y = { ~(OUT1 & OUT2 & OUT3 & OUT4 & OUT5 & OUT6 & OUT7 & OUT8 & OUT9 & + OUT10 & OUT11 & OUT12 & OUT13 & OUT14 & OUT15 & A16 & ~GBAR) } * UALS677ADLY PINDLY (1,0,21) DPWR DGND + Y + A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 P0 P1 P2 P3 GBAR + Y_O + IO_ALS00 + MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + + BOOLEAN: + ANY_CH_A = { CHANGED(A1,0) | CHANGED(A2,0) | CHANGED(A3,0) | + CHANGED(A4,0) | CHANGED(A5,0) | CHANGED(A6,0) | + CHANGED(A7,0) | CHANGED(A8,0) | CHANGED(A9,0) | + CHANGED(A10,0) | CHANGED(A11,0) | CHANGED(A12,0) | + CHANGED(A13,0) | CHANGED(A14,0) | CHANGED(A15,0) | + CHANGED(A16,0) } + ANY_CH_P = { CHANGED(P0,0) | CHANGED(P1,0) | CHANGED(P2,0) | CHANGED(P3,0) } + ENABLE = { GBAR!='1 } + + PINDLY: + Y_O = { + CASE ( + ANY_CH_P & ENABLE & TRN_HL, DELAY(8NS,22NS,38NS), + CHANGED(GBAR,0) & TRN_HL, DELAY(5NS,16NS,35NS), + ANY_CH_A & ENABLE & TRN_HL, DELAY(5NS,16NS,30NS), + ANY_CH_P & ENABLE & TRN_LH, DELAY(4NS,11NS,25NS), + ANY_CH_A & ENABLE & TRN_LH, DELAY(5NS,10NS,22NS), + CHANGED(GBAR,0) & TRN_LH, DELAY(3NS,6NS,13NS), + DELAY(9NS,23NS,39NS) ;DEFAULT + ) + } * .ENDS * *$ *------------------------------------------------------------------------- * 74ALS678 12-BIT ADDRESS COMPARATORS * * ALS/AS LOGIC CIRCUITS DATA BOOK, 1986, TI * NH 8/19/92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74ALS678 A1_I A2_I A3_I A4_I A5_I A6_I A7_I A8_I A9_I A10_I A11_I A12_I + A13_I A14_I A15_I A16_I C_I P3_I P2_I P1_I P0_I Y_O + OPTIONAL: DPWR = $G_DPWR DGND = $G_DGND + PARAMS: MNTYMXDLY = 0 IO_LEVEL = 0 * UALS678LOG LOGICEXP(21,22) DPWR DGND + A1_I A2_I A3_I A4_I A5_I A6_I A7_I A8_I A9_I A10_I A11_I A12_I A13_I A14_I + A15_I A16_I P0_I P1_I P2_I P3_I C_I + A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 P0 P1 P2 P3 C DY + D0_GATE IO_ALS00 IO_LEVEL = {IO_LEVEL} + + LOGIC: + A1 = { A1_I } + A2 = { A2_I } + A3 = { A3_I } + A4 = { A4_I } + A5 = { A5_I } + A6 = { A6_I } + A7 = { A7_I } + A8 = { A8_I } + A9 = { A9_I } + A10 = { A10_I } + A11 = { A11_I } + A12 = { A12_I } + A13 = { A13_I } + A14 = { A14_I } + A15 = { A15_I } + A16 = { A16_I } + P0 = { P0_I } + P1 = { P1_I } + P2 = { P2_I } + P3 = { P3_I } + C = { C_I } + * INTERMEDIATE TERMS + P0BAR = { ~P0 } + P1BAR = { ~P1 } + P2BAR = { ~P2 } + P3BAR = { ~P3 } + P2P3 = { P2BAR & P3BAR } + P1P2P3 = { P1BAR & P2P3 } + OUT1 = { ~(P0BAR & P1P2P3) ^ A1 } + OUT2 = { ~(P1BAR & P2P3) ^ A2 } + OUT3 = { ~((P0BAR & P2P3) | P1P2P3) ^ A3 } + OUT4 = { ~P2P3 ^ A4 } + OUT5 = { ~((P0BAR & P1BAR & P3BAR) | P2P3) ^ A5 } + OUT6 = { ~(P2P3 | (P1BAR & P3BAR)) ^ A6 } + OUT7 = { ~((P1BAR & P3BAR) | P2P3 | (P0BAR & P3BAR)) ^ A7 } + OUT8 = { ~P3BAR ^ A8 } + OUT9 = { ~((P0BAR & P1BAR & P2BAR) | P3BAR) ^ A9 } + OUT10 = { ~((P1BAR & P2BAR) | P3BAR) ^ A10 } + OUT11 = { ~((P0BAR & P2BAR) | (P1BAR & P2BAR) | P3BAR) ^ A11 } + OUT12 = { ~(P2BAR | P3BAR) ^ A12 } + OUT13 = { ~((P0BAR & P1BAR) | P2BAR | P3BAR) ^ A13 } + OUT14 = { ~(P1BAR | P2BAR | P3BAR) ^ A14 } + OUT15 = { ~(P0BAR | P1BAR | P2BAR | P3BAR) ^ A15 } + * OUTPUT + DY = { OUT1 & OUT2 & OUT3 & OUT4 & OUT5 & OUT6 & OUT7 & OUT8 & OUT9 & + OUT10 & OUT11 & OUT12 & OUT13 & OUT14 & OUT15 & A16 } * U1 DLTCH(1) DPWR DGND $D_HI $D_HI C DY $D_NC Y D0_GFF IO_ALS00 * UALS678DLY PINDLY (1,0,21) DPWR DGND + Y + A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 P0 P1 P2 P3 C + Y_O + IO_ALS00 + MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + + BOOLEAN: + ANY_CH_A = { CHANGED(A1,0) | CHANGED(A2,0) | CHANGED(A3,0) | + CHANGED(A4,0) | CHANGED(A5,0) | CHANGED(A6,0) | + CHANGED(A7,0) | CHANGED(A8,0) | CHANGED(A9,0) | + CHANGED(A10,0) | CHANGED(A11,0) | CHANGED(A12,0) | + CHANGED(A13,0) | CHANGED(A14,0) | CHANGED(A15,0) | + CHANGED(A16,0) } + ANY_CH_P = { CHANGED(P0,0) | CHANGED(P1,0) | CHANGED(P2,0) | CHANGED(P3,0) } + ENABLE = { C!='0 } + + PINDLY: + Y_O = { + CASE ( + CHANGED_LH(C,0) & TRN_HL, DELAY(15NS,-1,48NS), + ANY_CH_P & ENABLE & TRN_HL, DELAY(10NS,-1,43NS), + ANY_CH_A & ENABLE & TRN_HL, DELAY(5NS,-1,35NS), + ANY_CH_P & ENABLE & TRN_LH, DELAY(6NS,-1,22NS), + ANY_CH_A & ENABLE & TRN_LH, DELAY(5NS,-1,21NS), + CHANGED_LH(C,0) & TRN_LH, DELAY(3NS,-1,20NS), + DELAY(16NS,-1,49NS) ;DEFAULT + ) + } + + WIDTH: + NODE = C + MIN_HI = 40NS + + SETUP_HOLD: + DATA(20) P3 P2 P1 P0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 + CLOCK HL = C + SETUPTIME = 45NS + HOLDTIME = 5NS * .ENDS * *$ *------------------------------------------------------------------------------ * 74ALS679 12-BIT ADDRESS COMPARATORS * * ALS/AS LOGIC CIRCUITS DATA BOOK, 1986, TI * NH 8/11/92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74ALS679 A1_I A2_I A3_I A4_I A5_I A6_I A7_I A8_I A9_I A10_I A11_I A12_I + P0_I P1_I P2_I P3_I GBAR_I Y_O + OPTIONAL: DPWR = $G_DPWR DGND = $G_DGND + PARAMS: MNTYMXDLY = 0 IO_LEVEL = 0 * UALS679LOG LOGICEXP(17,18) DPWR DGND + A1_I A2_I A3_I A4_I A5_I A6_I A7_I A8_I A9_I A10_I A11_I A12_I P0_I P1_I + P2_I P3_I GBAR_I + A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 P0 P1 P2 P3 GBAR Y + D0_GATE IO_ALS00 IO_LEVEL = {IO_LEVEL} + + LOGIC: + A1 = { A1_I } + A2 = { A2_I } + A3 = { A3_I } + A4 = { A4_I } + A5 = { A5_I } + A6 = { A6_I } + A7 = { A7_I } + A8 = { A8_I } + A9 = { A9_I } + A10 = { A10_I } + A11 = { A11_I } + A12 = { A12_I } + P0 = { P0_I } + P1 = { P1_I } + P2 = { P2_I } + P3 = { P3_I } + GBAR = { GBAR_I } + * INTERMEDIATE TERMS + P0BAR = { ~P0 } + P1BAR = { ~P1 } + P2BAR = { ~P2 } + P3BAR = { ~P3 } + P2P3 = { P2BAR & P3BAR } + P1P2P3 = { P1BAR & P2P3 } + OUT1 = { ~(P0BAR & P1P2P3) ^ A1 } + OUT2 = { ~(P1BAR & P2P3) ^ A2 } + OUT3 = { ~((P0BAR & P2P3) | P1P2P3) ^ A3 } + OUT4 = { ~P2P3 ^ A4 } + OUT5 = { ~((P0BAR & P1BAR & P3BAR) | P2P3) ^ A5 } + OUT6 = { ~(P2P3 | (P1BAR & P3BAR)) ^ A6 } + OUT7 = { ~((P1BAR & P3BAR) | P2P3 | (P0BAR & P3BAR)) ^ A7 } + OUT8 = { ~P3BAR ^ A8 } + OUT9 = { ~((P0BAR & P1BAR) | P3BAR) ^ A9 } + OUT10 = { ~(P1BAR | P3BAR) ^ A10 } + OUT11 = { ~(P0BAR | P1BAR | P3BAR) ^ A11 } + OUT12 = { ~(P2BAR | P3BAR) ^ A12 } + * OUTPUT + Y = { ~(OUT1 & OUT2 & OUT3 & OUT4 & OUT5 & OUT6 & OUT7 & OUT8 & OUT9 & + OUT10 & OUT11 & OUT12 & ~GBAR) } * UALS679DLY PINDLY (1,0,17) DPWR DGND + Y + A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 P0 P1 P2 P3 GBAR + Y_O + IO_ALS00 + MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + + BOOLEAN: + ANY_CH_A = { CHANGED(A1,0) | CHANGED(A2,0) | CHANGED(A3,0) | CHANGED(A4,0) | + CHANGED(A5,0) | CHANGED(A6,0) | CHANGED(A7,0) | CHANGED(A8,0) | + CHANGED(A9,0) | CHANGED(A10,0)| CHANGED(A11,0)| CHANGED(A12,0)} + ANY_CH_P = { CHANGED(P0,0) | CHANGED(P1,0) | CHANGED(P2,0) | CHANGED(P3,0) } + ENABLE = { GBAR!='1 } + + PINDLY: + Y_O = { + CASE ( + ANY_CH_P & ENABLE & TRN_HL, DELAY(8NS,-1,35NS), + ANY_CH_A & ENABLE & TRN_HL, DELAY(5NS,-1,30NS), + ANY_CH_P & ENABLE & TRN_LH, DELAY(4NS,-1,25NS), + CHANGED(GBAR,0) & TRN_HL, DELAY(5NS,-1,25NS), + ANY_CH_A & ENABLE & TRN_LH, DELAY(5NS,-1,22NS), + CHANGED(GBAR,0) & TRN_LH, DELAY(3NS,-1,13NS), + DELAY(9NS,-1,36NS) ;DEFAULT + ) + } * .ENDS * *$ *------------------------------------------------------------------------- * 74ALS680 12-BIT ADDRESS COMPARATORS * * ALS/AS LOGIC CIRCUITS DATA BOOK, 1986, TI * NH 8/18/92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74ALS680 A1_I A2_I A3_I A4_I A5_I A6_I A7_I A8_I A9_I A10_I A11_I A12_I + P0_I P1_I P2_I P3_I C_I Y_O + OPTIONAL: DPWR = $G_DPWR DGND = $G_DGND + PARAMS: MNTYMXDLY = 0 IO_LEVEL = 0 * UALS680LOG LOGICEXP(17,18) DPWR DGND + A1_I A2_I A3_I A4_I A5_I A6_I A7_I A8_I A9_I A10_I A11_I A12_I P0_I P1_I + P2_I P3_I C_I + A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 P0 P1 P2 P3 C DY + D0_GATE IO_ALS00 IO_LEVEL = {IO_LEVEL} + + LOGIC: + A1 = { A1_I } + A2 = { A2_I } + A3 = { A3_I } + A4 = { A4_I } + A5 = { A5_I } + A6 = { A6_I } + A7 = { A7_I } + A8 = { A8_I } + A9 = { A9_I } + A10 = { A10_I } + A11 = { A11_I } + A12 = { A12_I } + P0 = { P0_I } + P1 = { P1_I } + P2 = { P2_I } + P3 = { P3_I } + C = { C_I } + * INTERMEDIATE TERMS + P0BAR = { ~P0 } + P1BAR = { ~P1 } + P2BAR = { ~P2 } + P3BAR = { ~P3 } + P2P3 = { P2BAR & P3BAR } + P1P2P3 = { P1BAR & P2P3 } + OUT1 = { ~(P0BAR & P1P2P3) ^ A1 } + OUT2 = { ~(P1BAR & P2P3) ^ A2 } + OUT3 = { ~((P0BAR & P2P3) | P1P2P3) ^ A3 } + OUT4 = { ~P2P3 ^ A4 } + OUT5 = { ~((P0BAR & P1BAR & P3BAR) | P2P3) ^ A5 } + OUT6 = { ~(P2P3 | (P1BAR & P3BAR)) ^ A6 } + OUT7 = { ~((P1BAR & P3BAR) | P2P3 | (P0BAR & P3BAR)) ^ A7 } + OUT8 = { ~P3BAR ^ A8 } + OUT9 = { ~((P0BAR & P1BAR) | P3BAR) ^ A9 } + OUT10 = { ~(P1BAR | P3BAR) ^ A10 } + OUT11 = { ~(P0BAR | P1BAR | P3BAR) ^ A11 } + OUT12 = { ~(P2BAR | P3BAR) ^ A12 } + * OUTPUT + DY = { (OUT1 & OUT2 & OUT3 & OUT4 & OUT5 & OUT6 & OUT7 & OUT8 & OUT9 & + OUT10 & OUT11 & OUT12) } * U1 DLTCH(1) DPWR DGND $D_HI $D_HI C DY $D_NC Y D0_GFF IO_ALS00 * UALS680DLY PINDLY (1,0,17) DPWR DGND + Y + A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 P0 P1 P2 P3 C + Y_O + IO_ALS00 + MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + + BOOLEAN: + ANY_CH_A = { CHANGED(A1,0) | CHANGED(A2,0) | CHANGED(A3,0) | CHANGED(A4,0) | + CHANGED(A5,0) | CHANGED(A6,0) | CHANGED(A7,0) | CHANGED(A8,0) | + CHANGED(A9,0) | CHANGED(A10,0)| CHANGED(A11,0)| CHANGED(A12,0)} + ANY_CH_P = { CHANGED(P0,0) | CHANGED(P1,0) | CHANGED(P2,0) | CHANGED(P3,0) } + ENABLE = { C!='0 } + + PINDLY: + Y_O = { + CASE ( + CHANGED_LH(C,0) & TRN_HL, DELAY(15NS,-1,42NS), + ANY_CH_P & ENABLE & TRN_HL, DELAY(10NS,-1,38NS), + ANY_CH_A & ENABLE & TRN_HL, DELAY(5NS,-1,25NS), + ANY_CH_P & ENABLE & TRN_LH, DELAY(6NS,-1,22NS), + ANY_CH_A & ENABLE & TRN_LH, DELAY(5NS,-1,21NS), + CHANGED_LH(C,0) & TRN_LH, DELAY(3NS,-1,20NS), + DELAY(11NS,-1,39NS) ;DEFAULT + ) + } + + WIDTH: + NODE = C + MIN_HI = 40NS + + SETUP_HOLD: + DATA(16) A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 P0 P1 P2 P3 + CLOCK HL = C + SETUPTIME = 45NS + HOLDTIME = 5NS * .ENDS * *$ *------------------------------------------------------------------------- * 74ALS688 8-BIT IDENTITY COMPARATORS * * ALS/AS LOGIC CIRCUITS DATA BOOK, 1986, TI * NH 8/21/92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74ALS688 P7_I P6_I P5_I P4_I P3_I P2_I P1_I P0_I Q7_I Q6_I Q5_I Q4_I + Q3_I Q2_I Q1_I Q0_I GBAR_I PEQBAR_O + OPTIONAL: DPWR = $G_DPWR DGND = $G_DGND + PARAMS: MNTYMXDLY = 0 IO_LEVEL = 0 * UALS688LOG LOGICEXP(17,18) DPWR DGND + P7_I P6_I P5_I P4_I P3_I P2_I P1_I P0_I + Q7_I Q6_I Q5_I Q4_I Q3_I Q2_I Q1_I Q0_I GBAR_I + P7 P6 P5 P4 P3 P2 P1 P0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 GBAR PEQBAR + D0_GATE IO_ALS00 IO_LEVEL = {IO_LEVEL} + + LOGIC: + P7 = { P7_I } + P6 = { P6_I } + P5 = { P5_I } + P4 = { P4_I } + P3 = { P3_I } + P2 = { P2_I } + P1 = { P1_I } + P0 = { P0_I } + Q7 = { Q7_I } + Q6 = { Q6_I } + Q5 = { Q5_I } + Q4 = { Q4_I } + Q3 = { Q3_I } + Q2 = { Q2_I } + Q1 = { Q1_I } + Q0 = { Q0_I } + GBAR = { GBAR_I } + + PEQ7 = { ~(~P7 ^ ~Q7) } + PEQ6 = { ~(~P6 ^ ~Q6) } + PEQ5 = { ~(~P5 ^ ~Q5) } + PEQ4 = { ~(~P4 ^ ~Q4) } + PEQ3 = { ~(~P3 ^ ~Q3) } + PEQ2 = { ~(~P2 ^ ~Q2) } + PEQ1 = { ~(~P1 ^ ~Q1) } + PEQ0 = { ~(~P0 ^ ~Q0) } + + PEQBAR = { ~(PEQ7 & PEQ6 & PEQ5 & PEQ4 & PEQ3 & PEQ2 & PEQ1 & PEQ0 & ~GBAR) } * UALS688DLY PINDLY (1,0,17) DPWR DGND + PEQBAR + GBAR P7 P6 P5 P4 P3 P2 P1 P0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 + PEQBAR_O + IO_ALS00 MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + + BOOLEAN: + ANY_CH_P = { CHANGED(P7,0) | CHANGED(P6,0) | CHANGED(P5,0) | CHANGED(P4,0) | + CHANGED(P3,0) | CHANGED(P2,0) | CHANGED(P1,0) | CHANGED(P0,0) } + ANY_CH_Q = { CHANGED(Q7,0) | CHANGED(Q6,0) | CHANGED(Q5,0) | CHANGED(Q4,0) | + CHANGED(Q3,0) | CHANGED(Q2,0) | CHANGED(Q1,0) | CHANGED(Q0,0) } + ENABLE = { GBAR!='1 } + + PINDLY: + PEQBAR_O = { + CASE( + CHANGED(GBAR,0) & TRN_HL, DELAY(5NS,-1,22NS), + (ANY_CH_P | ANY_CH_Q) & ENABLE & TRN_HL, DELAY(5NS,-1,20NS), + TRN_LH, DELAY(3NS,-1,12NS), + DELAY(6NS,-1,23NS) + ) + } * .ENDS * *$ *------------------------------------------------------------------------- * 74ALS689 8-BIT IDENTITY COMPARATORS WITH OPEN-COLLECTOR OUTPUTS * * ALS/AS LOGIC CIRCUITS DATA BOOK, 1986, TI * NH 8/21/92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74ALS689 P7_I P6_I P5_I P4_I P3_I P2_I P1_I P0_I Q7_I Q6_I Q5_I Q4_I + Q3_I Q2_I Q1_I Q0_I GBAR_I PEQBAR_O + OPTIONAL: DPWR = $G_DPWR DGND = $G_DGND + PARAMS: MNTYMXDLY = 0 IO_LEVEL = 0 * UALS689LOG LOGICEXP(17,18) DPWR DGND + P7_I P6_I P5_I P4_I P3_I P2_I P1_I P0_I + Q7_I Q6_I Q5_I Q4_I Q3_I Q2_I Q1_I Q0_I GBAR_I + P7 P6 P5 P4 P3 P2 P1 P0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 GBAR PEQBAR + D0_GATE IO_ALS00 IO_LEVEL = {IO_LEVEL} + + LOGIC: + P7 = { P7_I } + P6 = { P6_I } + P5 = { P5_I } + P4 = { P4_I } + P3 = { P3_I } + P2 = { P2_I } + P1 = { P1_I } + P0 = { P0_I } + Q7 = { Q7_I } + Q6 = { Q6_I } + Q5 = { Q5_I } + Q4 = { Q4_I } + Q3 = { Q3_I } + Q2 = { Q2_I } + Q1 = { Q1_I } + Q0 = { Q0_I } + GBAR = { GBAR_I } + + PEQ7 = { ~(~P7 ^ ~Q7) } + PEQ6 = { ~(~P6 ^ ~Q6) } + PEQ5 = { ~(~P5 ^ ~Q5) } + PEQ4 = { ~(~P4 ^ ~Q4) } + PEQ3 = { ~(~P3 ^ ~Q3) } + PEQ2 = { ~(~P2 ^ ~Q2) } + PEQ1 = { ~(~P1 ^ ~Q1) } + PEQ0 = { ~(~P0 ^ ~Q0) } + + PEQBAR = { ~(PEQ7 & PEQ6 & PEQ5 & PEQ4 & PEQ3 & PEQ2 & PEQ1 & PEQ0 & ~GBAR) } * UALS689DLY PINDLY (1,0,17) DPWR DGND + PEQBAR + GBAR P7 P6 P5 P4 P3 P2 P1 P0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 + PEQBAR_O + IO_ALS00_OC MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + + BOOLEAN: + ANY_CH_P = { CHANGED(P7,0) | CHANGED(P6,0) | CHANGED(P5,0) | CHANGED(P4,0) | + CHANGED(P3,0) | CHANGED(P2,0) | CHANGED(P1,0) | CHANGED(P0,0) } + ANY_CH_Q = { CHANGED(Q7,0) | CHANGED(Q6,0) | CHANGED(Q5,0) | CHANGED(Q4,0) | + CHANGED(Q3,0) | CHANGED(Q2,0) | CHANGED(Q1,0) | CHANGED(Q0,0) } + ENABLE = { GBAR!='1 } + + PINDLY: + PEQBAR_O = { + CASE( + CHANGED(GBAR,0), DELAY(8NS,-1,25NS), + (ANY_CH_P | ANY_CH_Q) & ENABLE & TRN_HL, DELAY(5NS,-1,23NS), + (ANY_CH_P | ANY_CH_Q) & ENABLE & TRN_LH, DELAY(10NS,-1,25NS), + DELAY(11NS,-1,26NS) + ) + } * .ENDS * *$ *------------------------------------------------------------------------- * 74ALS746 Octal Buffers and Line Drivers with Input Pull-up Registers * * The ALS/AS Data Book, 1986, TI * atl 7/27/89 Update interface and model names * .subckt 74ALS746 G1BAR G2BAR A1 A2 A3 A4 A5 A6 A7 A8 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nor(2) DPWR DGND + G1BAR G2BAR T + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} U2 pullup(8) DPWR DGND + A1 A2 A3 A4 A5 A6 A7 A8 + IO_20K IO_LEVEL={IO_LEVEL} U3 inv3a(8) DPWR DGND + A1 A2 A3 A4 A5 A6 A7 A8 + T + Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 + D_ALS746 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model IO_20K uio ( + DRVH=20K DRVL=1MEG + DtoA1=PULLUP_DTOA + ) * .model D_ALS746 utgate ( + tplhty=7.5ns tphlty=5.6ns + tplhmn=3ns tplhmx=12ns + tphlmn=2ns tphlmx=9ns + tpzhmn=5ns tpzhmx=15ns + tpzlmn=8ns tpzlmx=20ns + tphzmn=1ns tphzmx=10ns + tplzmn=2ns tplzmx=12ns + tphzty=4ns tpzhty=9ns + tplzty=7ns tpzlty=12.5ns + ) *$ *------------------------------------------------------------------------- * 74ALS747 Octal Buffers and Line Drviers with Input Pull-up Registers * * The ALS/AS Data Book, 1986, TI * atl 7/27/89 Update interface and model names * .subckt 74ALS747 G1BAR G2BAR A1 A2 A3 A4 A5 A6 A7 A8 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nor(2) DPWR DGND + G1BAR G2BAR T + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} U2 pullup(8) DPWR DGND + A1 A2 A3 A4 A5 A6 A7 A8 + IO_20K IO_LEVEL={IO_LEVEL} U3 buf3a(8) DPWR DGND + A1 A2 A3 A4 A5 A6 A7 A8 + T + Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 + D_ALS747 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS747 utgate ( + tplhty=8.7ns tphlty=7.4ns + tplhmn=4ns tplhmx=14ns + tphlmn=2ns tphlmx=10ns + tpzhmn=5ns tpzhmx=15ns + tpzlmn=8ns tpzlmx=20ns + tphzmn=1ns tphzmx=10ns + tplzmn=2ns tplzmx=12ns + tpzhty=9ns tpzlty=12.5ns + tphzty=4ns tplzty=7ns + ) *$ *------------------------------------------------------------------------- * 74ALS756 Octal Buffers and Line Drivers with Open-Collector Outputs * * The ALS/AS Data Book, 1986, TI * atl 7/27/89 Update interface and model names * .subckt 74ALS756 GBAR A1 A2 A3 A4 Y1 Y2 Y3 Y4 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 inv DPWR DGND + GBAR G + D_ALS756_1 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 nanda(2,4) DPWR DGND + A1 G + A2 G + A3 G + A4 G + Y1 Y2 Y3 Y4 + D_ALS756_2 IO_ALS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS756_1 ugate ( + tplhty=7ns tplhmx=1ps + tphlty=2ns tphlmx=1ps + tplhmn=4ns tplhmx=10ns + ) .model D_ALS756_2 ugate ( + tplhty=14ns tphlty=5ns + tplhmn=8ns tplhmx=24ns + tphlmn=2ns tphlmx=10ns + ) *$ *------------------------------------------------------------------------- * 74ALS758 QUADRUPLE BUS TRANSCEIVERS WITH OPEN-COLLECTOR OUTPUTS * * ALS/AS LOGIC CIRCUITS DATA BOOK, 1986, TI * NH 9/1/92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT * .SUBCKT 74ALS758 A1_B A2_B A3_B A4_B GABBAR_I GBA_I B1_B B2_B B3_B B4_B + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UALS758LOG LOGICEXP(10,10) DPWR DGND + A1_B A2_B A3_B A4_B GABBAR_I GBA_I B1_B B2_B B3_B B4_B + A1 A2 A3 A4 GABBAR GBA B1 B2 B3 B4 + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} + + LOGIC: * * BUFFER: + GABBAR = { GABBAR_I } + GBA = { GBA_I } + GAB = { ~GABBAR } + * OUTPUT ASSIGNMENTS + A1 = { ~(B1_B & GBA) } + A2 = { ~(B2_B & GBA) } + A3 = { ~(B3_B & GBA) } + A4 = { ~(B4_B & GBA) } + B1 = { ~(A1_B & GAB) } + B2 = { ~(A2_B & GAB) } + B3 = { ~(A3_B & GAB) } + B4 = { ~(A4_B & GAB) } * UALS758DLY PINDLY (8,0,2) DPWR DGND + A1 A2 A3 A4 B1 B2 B3 B4 + GABBAR GBA + A1_B A2_B A3_B A4_B B1_B B2_B B3_B B4_B + IO_ALS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + PINDLY: + A1_B A2_B A3_B A4_B = { + CASE( + TRN_LH, DELAY(10NS,-1,28NS), + CHANGED(GBA,0) & TRN_HL, DELAY(6NS,-1,21NS), + DELAY(2NS,-1,12NS) + ) + } + B1_B B2_B B3_B B4_B = { + CASE( + TRN_LH, DELAY(10NS,-1,28NS), + CHANGED(GABBAR,0) & TRN_HL, DELAY(6NS,-1,21NS), + DELAY(2NS,-1,12NS) + ) + } * .ENDS * *$ *------------------------------------------------------------------------- * 74ALS760 Octal Buffers and Line Drivers with Open-Collector Outputs * * The ALS/AS Data Book, 1986, TI * atl 10/23/89 Update interface and model names * .subckt 74ALS760 GBAR A1 A2 A3 A4 Y1 Y2 Y3 Y4 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UG buf DPWR DGND + GBAR GBAF + D_ALS760_1 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UCTRL ora(2,4) DPWR DGND + A1 GBAF + A2 GBAF + A3 GBAF + A4 GBAF + Y1 Y2 Y3 Y4 + D_ALS760_2 IO_ALS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS760_1 ugate ( + tplhty=3ns tphlty=11ns + ) .model D_ALS760_2 ugate ( + tplhty=22ns tphlty=13ns + ) *$ *------------------------------------------------------------------------- * 74ALS762 Octal Buffers and Line Drivers with Open-Collector Outputs * * The ALS/AS Data Book, 1986, TI * atl 10/24/89 Update interface and model names * .subckt 74ALS762 GBAR A1 A2 A3 A4 Y1 Y2 Y3 Y4 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UG inv DPWR DGND + GBAR G + D_ALS762_1 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UIN bufa(4) DPWR DGND + A1 A2 A3 A4 I1 I2 I3 I4 + D_ALS762_2 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UY nanda(2,4) DPWR DGND + I1 G + I2 G + I3 G + I4 G + Y1 Y2 Y3 Y4 + D_ALS762_3 IO_ALS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS762_1 ugate ( + tplhty=12ns + ) .model D_ALS762_2 ugate ( + tphlty=3ns + ) .model D_ALS762_3 ugate ( + tplhty=14ns tphlty=6ns + ) *$ *------------------------------------------------------------------------- * 74ALS763 Octal Buffers and Line Drivers with Open-Collector Outputs * * The ALS/AS Data Book, 1986, TI * atl 7/27/89 Update interface and model names * .subckt 74ALS763 1GBAR 1A1 1A2 1A3 1A4 1Y1 1Y2 1Y3 1Y4 2G 2A1 2A2 2A3 2A4 2Y1 + 2Y2 2Y3 2Y4 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1G inv DPWR DGND + 1GBAR 1G + D_ALS763_1 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UCTRL1 nanda(2,4) DPWR DGND + 1A1 1G + 1A2 1G + 1A3 1G + 1A4 1G + 1Y1 1Y2 1Y3 1Y4 + D_ALS763_3 IO_ALS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2G buf DPWR DGND + 2G 2G_BUF + D_ALS763_2 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UCTRL2 nanda(2,4) DPWR DGND + 2A1 2G_BUF + 2A2 2G_BUF + 2A3 2G_BUF + 2A4 2G_BUF + 2Y1 2Y2 2Y3 2Y4 + D_ALS763_3 IO_ALS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS763_1 ugate ( + tplhmn=3ns tplhmx=12ns + tphlmn=2ns tphlmx=1ps + ) .model D_ALS763_2 ugate ( + tplhmn=3ns tplhmx=12ns + tphlmn=2ns tphlmx=1ps + ) .model D_ALS763_3 ugate ( + tplhmn=7ns tplhmx=25ns + tphlmn=2ns tphlmx=9ns + ) *$ *------------------------------------------------------------------------- * 74ALS804A Hex 2-Input NAND Drivers * * The ALS/AS Data Book, 1986, TI * atl 7/27/89 Update interface and model names * .subckt 74ALS804A A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(2) DPWR DGND + A B Y + D_ALS804A IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS804A ugate ( + tplhty=4ns tphlty=4ns + tplhmn=2ns tplhmx=7ns + tphlmn=2ns tphlmx=8ns + ) *$ *------------------------------------------------------------------------- * 74ALS805A Hex 2-Input NOR Drivers * * The ALS/AS Data Book, 1986, TI * atl 7/27/89 Update interface and model names * .subckt 74ALS805A A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nor(2) DPWR DGND + A B Y + D_ALS805A IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS805A ugate ( + tplhty=4ns tphlty=4ns + tplhmn=2ns tplhmx=7ns + tphlmn=2ns tphlmx=8ns + ) *$ *------------------------------------------------------------------------- * 74ALS808A Hex 2-Input AND Drivers * * The ALS/AS Data Book, 1986, TI * atl 7/27/89 Update interface and model names * .subckt 74ALS808A A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 and(2) DPWR DGND + A B Y + D_ALS808A IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS808A ugate ( + tplhty=6ns tphlty=4ns + tplhmn=2ns tplhmx=9ns + tphlmn=1ns tphlmx=8ns + ) *$ *------------------------------------------------------------------------- * 74ALS810 Quadruple 2-Input Exclusive-NOR Gates * * The ALS/AS Data Book, 1986, TI * atl 7/27/89 Update interface and model names * .subckt 74ALS810 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UBUF bufa(2) DPWR DGND + A B ABUF BBUF + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} U1 and(2) DPWR DGND + ABUF BBUF C + D0_GATE IO_ALS00 U2 nor(2) DPWR DGND + ABUF BBUF D + D_ALS810_1 IO_ALS00 MNTYMXDLY={MNTYMXDLY} U3 or(2) DPWR DGND + C D Y + D_ALS810_2 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS810_1 ugate ( + tplhmx=2ns + ) .model D_ALS810_2 ugate ( + tplhmn=5ns tplhmx=18ns + tphlmn=3ns tphlmx=14ns + ) *$ *------------------------------------------------------------------------- * 74ALS811 Quadruple 2-Input Exclusive-NOR Gates With Open-Collector Outputs * * The ALS/AS Data Book, 1986, TI * atl 7/27/89 Update interface and model names * .subckt 74ALS811 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UBUF bufa(2) DPWR DGND + A B ABUF BBUF + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} U1 and(2) DPWR DGND + ABUF BBUF C + D0_GATE IO_ALS00 U2 nor(2) DPWR DGND + ABUF BBUF D + D_ALS811_1 IO_ALS00 MNTYMXDLY={MNTYMXDLY} U3 or(2) DPWR DGND + C D Y + D_ALS811_2 IO_ALS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS811_1 ugate ( + tplhmn=5ns tphlmx=5ns + ) .model D_ALS811_2 ugate ( + tplhmn=20ns tplhmx=50ns + tphlmn=5ns tphlmx=23ns + ) *$ *------------------------------------------------------------------------- * 74ALS832A Hex 2-Input OR Drivers * * The ALS/AS Data Book, 1986, TI * atl 7/28/89 Update interface and model names * .subckt 74ALS832A A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 or(2) DPWR DGND + A B Y + D_ALS832A IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS832A ugate ( + tplhty=6ns tphlty=4ns + tplhmn=2ns tplhmx=9ns + tphlmn=1ns tphlmx=8ns + ) *$ *---------- * 74ALS841 10-bit Bus Interface D-Type Latches with 3-State Outputs * * The ALS/AS Data Book, 1986, TI * atl 10/24/89 Update interface and model names * .subckt 74ALS841 OCBAR C 1D 2D 3D 4D 5D 6D 7D 8D 9D 10D 1Q 2Q 3Q 4Q 5Q 6Q 7Q + 8Q 9Q 10Q + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UOC inv DPWR DGND + OCBAR OC + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} UQI dltch(10) DPWR DGND + $D_HI $D_HI C + 1D 2D 3D 4D 5D + 6D 7D 8D 9D 10D + Q1 Q2 Q3 Q4 Q5 + Q6 Q7 Q8 Q9 Q10 + $D_NC $D_NC $D_NC $D_NC $D_NC + $D_NC $D_NC $D_NC $D_NC $D_NC + D_ALS841_1 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UQ buf3a(10) DPWR DGND + Q1 Q2 Q3 Q4 Q5 + Q6 Q7 Q8 Q9 Q10 + OC + 1Q 2Q 3Q 4Q 5Q + 6Q 7Q 8Q 9Q 10Q + D_ALS841_2 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS841_1 ugff ( + twghmn=20ns tsudgmn=10ns + thdgmn=5ns tpgqlhmn=5ns + tpgqlhmx=8ns tpgqhlmn=6ns + tpgqhlmx=13ns + ) .model D_ALS841_2 utgate ( + tplhmn=2ns tplhmx=13ns + tphlmn=2ns tphlmx=13ns + tpzhmn=2ns tpzhmx=12ns + tpzlmn=2ns tpzlmx=12ns + tphzmn=2ns tphzmx=10ns + tplzmn=2ns tplzmx=12ns + ) *$ *---------- * 74ALS842 10-bit Bus Interface D-Type Latches with 3-STATE Outputs * * The ALS/AS Data Book, 1986, TI * atl 10/25/89 Update interface and model names * .subckt 74ALS842 OCBAR C 1DBAR 2DBAR 3DBAR 4DBAR 5DBAR 6DBAR 7DBAR 8DBAR 9DBAR + 10DBAR 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q 10Q + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UOC inv DPWR DGND + OCBAR OC + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} UQI dltch(10) DPWR DGND + $D_HI $D_HI C + 1DBAR 2DBAR 3DBAR 4DBAR 5DBAR + 6DBAR 7DBAR 8DBAR 9DBAR 10DBAR + $D_NC $D_NC $D_NC $D_NC $D_NC + $D_NC $D_NC $D_NC $D_NC $D_NC + Q1 Q2 Q3 Q4 Q5 + Q6 Q7 Q8 Q9 Q10 + D_ALS842_1 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UQ buf3a(10) DPWR DGND + Q1 Q2 Q3 Q4 Q5 + Q6 Q7 Q8 Q9 Q10 + OC + 1Q 2Q 3Q 4Q 5Q + 6Q 7Q 8Q 9Q 10Q + D_ALS842_2 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS842_1 ugff ( + twghmn=20ns tsudgmn=10ns + thdgmn=5ns tpgqlhmn=4ns + tpgqlhmx=9ns tpgqhlmn=3ns + tpgqhlmx=7ns + ) .model D_ALS842_2 utgate ( + tplhmn=4ns tplhmx=18ns + tphlmn=3ns tphlmx=13ns + tpzhmn=2ns tpzhmx=12ns + tpzlmn=2ns tpzlmx=12ns + tphzmn=1ns tphzmx=10ns + tplzmn=2ns tplzmx=12ns + ) *$ *---------- * 74ALS843 9-bit Bus Interface D-TYPE Latches with 3-STATE Outputs * * The ALS/AS Data Book, 1986, TI * atl 10/25/89 Update interface and model names * .subckt 74ALS843 OCBAR C PREBAR CLRBAR 1D 2D 3D 4D 5D 6D 7D 8D 9D 1Q 2Q 3Q + 4Q 5Q 6Q 7Q 8Q 9Q + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UOC inv DPWR DGND + OCBAR OC + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} UQI dltch(9) DPWR DGND + PREBAR CLRBAR C + 1D 2D 3D 4D 5D 6D 7D 8D 9D + Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D_ALS843_1 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UQ buf3a(9) DPWR DGND + Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 + OC + 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q + D_ALS843_2 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS843_1 ugff ( + twghmn=20ns twpclmn=35ns + tsudgmn=10ns thdgmn=5ns + tppcqlhmn=3ns tppcqlhmx=9ns + tppcqhlmn=2ns tppcqhlmx=5ns + tpgqlhmn=3ns tpgqlhmx=8ns + tpgqhlmn=4ns tpgqhlmx=8ns + ) .model D_ALS843_2 utgate ( + tplhmn=2ns tplhmx=13ns + tphlmn=4ns tphlmx=18ns + tpzhmn=2ns tpzhmx=12ns + tpzlmn=4ns tpzlmx=14ns + tphzmn=2ns tphzmx=10ns + tplzmn=2ns tplzmx=12ns + ) *$ *---------- * 74ALS844 9-bit Bus Interface D-TYPE Latches with 3-STATE Outputs * * The ALS/AS Data Book, 1986, TI * atl 10/26/89 Update interface and model names * .subckt 74ALS844 OCBAR C PREBAR CLRBAR 1DBAR 2DBAR 3DBAR 4DBAR 5DBAR 6DBAR + 7DBAR 8DBAR 9DBAR 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UOC inv DPWR DGND + OCBAR OC + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} UQI dltch(9) DPWR DGND + CLRBAR PREBAR C + 1DBAR 2DBAR 3DBAR 4DBAR 5DBAR 6DBAR 7DBAR 8DBAR 9DBAR + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 + D_ALS844_1 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UQ buf3a(9) DPWR DGND + Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 + OC + 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q + D_ALS844_2 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS844_1 ugff ( + twghmn=20ns twpclmn=35ns + tsudgmn=10ns thdgmn=5ns + tppcqlhmn=1ns tppcqlhmx=2ns + tppcqhlmn=5ns tppcqhlmx=10ns + tpgqlhmn=4ns tpgqlhmx=9ns + tpgqhlmn=3ns tpgqhlmx=7ns + ) .model D_ALS844_2 utgate ( + tplhmn=4ns tplhmx=20ns + tphlmn=3ns tphlmx=15ns + tpzhmn=4ns tpzhmx=17ns + tpzlmn=5ns tpzlmx=20ns + tphzmn=1ns tphzmx=11ns + tplzmn=1ns tplzmx=12ns + ) *$ *---------- * 74ALS845 8-bit Bus Interface D-TYPE Latches with 3-STATE Outputs * * The ALS/AS Data Book, 1986, TI * atl 10/27/89 Update interface and model names * .subckt 74ALS845 OCBAR1 OCBAR2 OCBAR3 C PREBAR CLRBAR 1D 2D 3D 4D 5D 6D 7D + 8D 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UOC nor(3) DPWR DGND + OCBAR1 OCBAR2 OCBAR3 OC + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} UQI dltch(8) DPWR DGND + PREBAR CLRBAR C + 1D 2D 3D 4D 5D 6D 7D 8D + Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D_ALS845_1 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UQ buf3a(8) DPWR DGND + Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 + OC + 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q + D_ALS845_2 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS845_1 ugff ( + twghmn=20ns twpclmn=35ns + tsudgmn=10ns thdgmn=5ns + tppcqlhmn=4ns tppcqlhmx=9ns + tppcqhlmn=2ns tppcqhlmx=8ns + tpgqlhmn=3ns tpgqlhmx=8ns + tpgqhlmn=4ns tpgqhlmx=8ns + ) .model D_ALS845_2 utgate ( + tplhmn=2ns tplhmx=13ns + tphlmn=4ns tphlmx=18ns + tpzhmn=3ns tpzhmx=16ns + tpzlmn=5ns tpzlmx=18ns + tphzmn=1ns tphzmx=11ns + tplzmn=2ns tplzmx=12ns + ) *$ *------------------------------------------------------------------------- * 74ALS846 8-bit Bus Interface D-TYPE Latches with 3-STATE Outputs * * The ALS/AS Data Book, 1986, TI * atl 10/27/89 Update interface and model names * .subckt 74ALS846 OCBAR1 OCBAR2 OCBAR3 C PREBAR CLRBAR 1DBAR 2DBAR 3DBAR 4DBAR + 5DBAR 6DBAR 7DBAR 8DBAR 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UOC nor(3) DPWR DGND + OCBAR1 OCBAR2 OCBAR3 OC + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} UQI dltch(8) DPWR DGND + CLRBAR PREBAR C + 1DBAR 2DBAR 3DBAR 4DBAR 5DBAR 6DBAR 7DBAR 8DBAR + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 + D_ALS846_1 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UQ buf3a(8) DPWR DGND + Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 + OC + 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q + D_ALS846_2 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS846_1 ugff ( + twghmn=20ns twpclmn=35ns + tsudgmn=10ns thdgmn=5ns + tppcqlhmn=1ns tppcqlhmx=1ps + tppcqhlmn=6ns tppcqhlmx=8ns + tpgqlhmn=4ns tpgqlhmx=7ns + tpgqhlmn=3ns tpgqhlmx=7ns + ) .model D_ALS846_2 utgate ( + tplhmn=4ns tplhmx=20ns + tphlmn=3ns tphlmx=15ns + tpzhmn=3ns tpzhmx=15ns + tpzlmn=5ns tpzlmx=18ns + tphzmn=1ns tphzmx=11ns + tplzmn=2ns tplzmx=12ns + ) *$ *------------------------------------------------------------------------- * 74ALS857 MULTIPLEXERS UNIVERSAL 2-1 LINE HEX WITH 3-STATE OUTPUTS * * ALS/AS LOGIC DATA BOOK, 1986, TI * TC 08/27/92 REMODELED USING LOGICEXP, PINDLY, & CONSTRAINT DEVICES * .SUBCKT 74ALS857 S0_I S1_I COMP_I 1A_I 1B_I 2A_I 2B_I 3A_I 3B_I 4A_I 4B_I + 5A_I 5B_I 6A_I 6B_I 1Y_O 2Y_O 3Y_O 4Y_O 5Y_O 6Y_O OPER_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UALS857LOG LOGICEXP(15,24) DPWR DGND + S0_I S1_I COMP_I 1A_I 1B_I 2A_I 2B_I 3A_I 3B_I 4A_I 4B_I 5A_I 5B_I + 6A_I 6B_I + S0 S1 COMP 1A 1B 2A 2B 3A 3B 4A 4B 5A 5B 6A 6B 1Y 2Y 3Y 4Y 5Y 6Y + OPER OEN1 OEN2 + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} + LOGIC: + S0 = { S0_I } + S1 = { S1_I } + COMP = { COMP_I } + 1A = { 1A_I } + 1B = { 1B_I } + 2A = { 2A_I } + 2B = { 2B_I } + 3A = { 3A_I } + 3B = { 3B_I } + 4A = { 4A_I } + 4B = { 4B_I } + 5A = { 5A_I } + 5B = { 5B_I } + 6A = { 6A_I } + 6B = { 6B_I } + IS0 = { ~S0 } + IS1 = { ~S1 } + IOP1 = { ~(1A | 2A | 3A | 4A | 5A | 6A) } + IOP2 = { ~(1B | 2B | 3B | 4B | 5B | 6B) } + 1Y = { ((1A & IS0 & IS1) | (S0 & IS1 & 1B) | (1A & 1B & IS0)) ^ COMP } + 2Y = { ((2A & IS0 & IS1) | (S0 & IS1 & 2B) | (2A & 2B & IS0)) ^ COMP } + 3Y = { ((3A & IS0 & IS1) | (S0 & IS1 & 3B) | (3A & 3B & IS0)) ^ COMP } + 4Y = { ((4A & IS0 & IS1) | (S0 & IS1 & 4B) | (4A & 4B & IS0)) ^ COMP } + 5Y = { ((5A & IS0 & IS1) | (S0 & IS1 & 5B) | (5A & 5B & IS0)) ^ COMP } + 6Y = { ((6A & IS0 & IS1) | (S0 & IS1 & 6B) | (6A & 6B & IS0)) ^ COMP } + OPER = { (IS0 & IS1 & IOP1) | (IS1 & S0 & IOP2) } + OEN1 = { ~(S0 & S1 & COMP) } + OEN2 = { ~((IS0 & S1) | (S1 & COMP)) } * UALS857DLY PINDLY (7,2,15) DPWR DGND + 1Y 2Y 3Y 4Y 5Y 6Y OPER + OEN1 OEN2 + S0 S1 COMP 1A 1B 2A 2B 3A 3B 4A 4B 5A 5B 6A 6B + 1Y_O 2Y_O 3Y_O 4Y_O 5Y_O 6Y_O OPER_O + IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + SELECT = { CHANGED(S0,0) | CHANGED(S1,0) } + DATA = { CHANGED(1A,0) | CHANGED(1B,0) | CHANGED(2A,0) | CHANGED(2B,0) | + CHANGED(3A,0) | CHANGED(3B,0) | CHANGED(4A,0) | CHANGED(4B,0) | + CHANGED(5A,0) | CHANGED(5B,0) | CHANGED(6A,0) | CHANGED(6B,0) } + COMPLEMENT = { CHANGED(COMP,0) } + TRISTATE: + ENABLE HI OEN1 + 1Y_O 2Y_O 3Y_O 4Y_O 5Y_O 6Y_O = { + CASE( + SELECT & TRN_Z$, DELAY(7NS,-1,35NS), + SELECT & (TRN_LH | TRN_HL), DELAY(7NS,-1,33NS), + DATA & COMP!='0 & (TRN_LH | TRN_HL), DELAY(4NS,-1,25NS), + COMPLEMENT & TRN_Z$, DELAY(8NS,-1,24NS), + SELECT & TRN_$Z, DELAY(2NS,-1,23NS), + COMPLEMENT & TRN_$Z, DELAY(6NS,-1,21NS), + DATA & COMP!='1 & (TRN_LH | TRN_HL), DELAY(4NS,-1,18NS), + COMPLEMENT & (TRN_LH | TRN_HL), DELAY(6NS,-1,18NS), + DELAY(8NS,-1,36NS) + ) + } + TRISTATE: + ENABLE HI OEN2 + OPER_O = { + CASE( + DATA & (TRN_LH | TRN_HL), DELAY(5NS,-1,37NS), + CHANGED(S0,0) & TRN_$Z, DELAY(11NS,-1,27NS), + CHANGED(S1,0) & TRN_Z$, DELAY(6NS,-1,25NS), + COMPLEMENT & TRN_Z$, DELAY(9NS,-1,25NS), + SELECT & (TRN_LH | TRN_HL), DELAY(5NS,-1,23NS), + COMPLEMENT & TRN_$Z, DELAY(6NS,-1,20NS), + CHANGED(S0,0) & TRN_Z$, DELAY(6NS,-1,20NS), + CHANGED(S1,0) & TRN_$Z, DELAY(3NS,-1,19NS), + DELAY(6NS,-1,38NS) + ) + } * .ENDS * *$ *------------------------------------------------------------------------- * 74ALS874B Dual 4-bit D-TYPE Edge-Triggered Flip-Flops * * The ALS/AS Data Book, 1986, TI * atl 7/28/89 Update interface and model names * * Note: Minimum clock width is less than propagation delay, so the width * might not be checked. * .subckt 74ALS874B OCBAR CLK CLRBAR D1 D2 D3 D4 Q1 Q2 Q3 Q4 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UOC inv DPWR DGND + OCBAR OC + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} UDFF dff(4) DPWR DGND + $D_HI CLRBAR CLK + D1 D2 D3 D4 + 1QQ 2QQ 3QQ 4QQ $D_NC $D_NC $D_NC $D_NC + D_ALS874B_1 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UOCQ buf3a(4) DPWR DGND + 1QQ 2QQ 3QQ 4QQ OC Q1 Q2 Q3 Q4 + D_ALS874B_2 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS874B_1 ueff ( + twclklmn=16.5ns twclkhmn=16.5ns + twpclmn=10ns tsudclkmn=15ns + tsupcclkhmn=10ns tppcqhlmn=1ns + tppcqhlmx=3ns + ) .model D_ALS874B_2 utgate ( + tplhmn=4ns tplhmx=14ns + tphlmn=4ns tphlmx=14ns + tpzhmn=4ns tpzhmx=18ns + tpzlmn=4ns tpzlmx=18ns + tphzmn=2ns tphzmx=10ns + tplzmn=3ns tplzmx=13ns + ) *$ *------------------------------------------------------------------------ * 74ALS990 8-bit D-TYPE Transparent Read-Back Latches * * The ALS/AS Data Book, 1986, TI * atl 7/28/89 Update interface and model names * .subckt 74ALS990 OERBBAR C 1D 2D 3D 4D 5D 6D 7D 8D 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 inv DPWR DGND + OERBBAR OERB + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} U2 dltch(8) DPWR DGND + $D_HI $D_HI C + 1D 2D 3D 4D 5D 6D 7D 8D + 1QT 2QT 3QT 4QT 5QT 6QT 7QT 8QT + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D_ALS990_1 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UOUT bufa(8) DPWR DGND + 1QT 2QT 3QT 4QT 5QT 6QT 7QT 8QT + 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q + D_ALS990_2 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U3 buf3a(8) DPWR DGND + 1QT 2QT 3QT 4QT 5QT 6QT 7QT 8QT + OERB + 1D 2D 3D 4D 5D 6D 7D 8D + D_ALS990_3 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS990_1 ugff ( + twghmn=10ns tsudgmn=10ns + thdgmn=5ns tpgqlhmn=2ns + tpgqlhmx=9ns tpgqhlmn=3ns + tpgqhlmx=2ns + ) .model D_ALS990_2 ugate ( + tplhmn=4ns tplhmx=17ns + tphlmn=5ns tphlmx=24ns + ) .model D_ALS990_3 utgate ( + tplhmn=4ns tplhmx=17ns + tphlmn=5ns tphlmx=24ns + tpzhmn=4ns tpzhmx=21ns + tpzlmn=4ns tpzlmx=21ns + tphzmn=4ns tphzmx=19ns + tplzmn=4ns tplzmx=19ns + ) *$ *------------------------------------------------------------------------- * 74ALS991 8-bit D-TYPE Transparent Read-Back Latches * * The ALS/AS Data Book, 1986, TI * atl 7/28/89 Update interface and model names * .subckt 74ALS991 OERBBAR C 1D 2D 3D 4D 5D 6D 7D 8D 1QBAR 2QBAR 3QBAR 4QBAR + 5QBAR 6QBAR 7QBAR 8QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 inv DPWR DGND + OERBBAR OERB + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} U2 dltch(8) DPWR DGND + $D_HI $D_HI C + 1D 2D 3D 4D 5D 6D 7D 8D + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + 1QBART 2QBART 3QBART 4QBART 5QBART 6QBART 7QBART 8QBART + D_ALS991_1 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UBUF bufa(8) DPWR DGND + 1QBART 2QBART 3QBART 4QBART 5QBART 6QBART 7QBART 8QBART + 1QBAR 2QBAR 3QBAR 4QBAR 5QBAR 6QBAR 7QBAR 8QBAR + D_ALS991_2 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U3 inv3a(8) DPWR DGND + 1QBART 2QBART 3QBART 4QBART 5QBART 6QBART 7QBART 8QBART + OERB + 1D 2D 3D 4D 5D 6D 7D 8D + D_ALS991_3 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS991_1 ugff ( + twghmn=10ns tsudgmn=10ns + thdgmn=5ns tpgqlhmn=5ns + tpgqlhmx=8ns tpgqhlmn=3ns + tpgqhlmx=8ns + ) .model D_ALS991_2 ugate ( + tplhmn=4ns tplhmx=20ns + tphlmn=4ns tphlmx=15ns + ) .model D_ALS991_3 utgate ( + tplhmn=4ns tplhmx=15ns + tphlmn=4ns tphlmx=20ns + tpzhmn=4ns tpzhmx=22ns + tpzlmn=4ns tpzlmx=22ns + tphzmn=4ns tphzmx=17ns + tplzmn=4ns tplzmx=17ns + ) *$ *------------------------------------------------------------------------- * 74ALS992 9-bit D-TYPE Transparent Read-Back Latches with 3-STATE Outputs * * The ALS/AS Logic Data Book, 1986, TI * tvh 10/26/89 Update interface and model names * .subckt 74ALS992 OEQBAR OERBBAR CLRBAR C 1D 2D 3D 4D 5D 6D 7D 8D 9D 1Q 2Q 3Q + 4Q 5Q 6Q 7Q 8Q 9Q + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 inva(2) DPWR DGND + OEQBAR OERBBAR OEQ OERB + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} U2 buf3a(9) DPWR DGND + Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 + OERB + 1D 2D 3D 4D 5D 6D 7D 8D 9D + D_ALS992_1 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U3 buf3a(9) DPWR DGND + Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 + OEQ + 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q + D_ALS992_2 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U4 dltch(9) DPWR DGND + $D_HI CLRBAR C + 1D 2D 3D 4D 5D 6D 7D 8D 9D + Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D_ALS992_3 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS992_1 utgate ( + tphlmn=5.9ns tphlty=11.9ns + tphlmx=21.9ns tplhmn=5.9ns + tplhty=11.9ns tplhmx=21.9ns + tpzlmn=4ns tpzlty=11ns + tpzlmx=21ns tpzhmn=4ns + tpzhty=11ns tpzhmx=21ns + tplzmn=2ns tplzty=6ns + tplzmx=14ns tphzmn=2ns + tphzty=6ns tphzmx=14ns + ) .model D_ALS992_2 utgate ( + tplhmn=2.9ns tplhty=6.9ns + tplhmx=13.9ns tphlmn=3.9ns + tphlty=8.9ns tphlmx=15.9ns + tpzlmn=4ns tpzlty=11ns + tpzlmx=18ns tpzhmn=4ns + tpzhty=11ns tpzhmx=18ns + tplzmn=1ns tplzty=6ns + tplzmx=14ns tphzmn=1ns + tphzty=6ns tphzmx=14ns + ) .model D_ALS992_3 ugff ( + twghmn=10ns twpclmn=10ns + tsudgmn=10ns thdgmn=5ns + tpdqlhmn=0.1ns tpdqhlmn=0.1ns + tpgqlhmn=3.1ns tpgqlhty=5.1ns + tpgqlhmx=6.1ns tpgqhlmn=4.1ns + tpgqhlty=6.1ns tpgqhlmx=9.1ns + tppcqhlmn=2.1ns tppcqhlty=3.1ns + tppcqhlmx=4.1ns + ) *$ *------------------------------------------------------------------------- * 74ALS993 9-bit D-TYPE Transparent Read-Back Latches with 3-STATE Outputs * * The ALS/AS Logic Data Book, 1986, TI * tvh 10/26/89 Update interface and model names * .subckt 74ALS993 OEQBAR OERBBAR CLRBAR C 1D 2D 3D 4D 5D 6D 7D 8D 9D 1QB 2QB + 3QB 4QB 5QB 6QB 7QB 8QB 9QB + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 inva(2) DPWR DGND + OEQBAR OERBBAR OEQ OERB + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} U2 buf3a(9) DPWR DGND + Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 + OERB + 1D 2D 3D 4D 5D 6D 7D 8D 9D + D_ALS993_1 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U3 inv3a(9) DPWR DGND + Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 + OEQ + 1QB 2QB 3QB 4QB 5QB 6QB 7QB 8QB 9QB + D_ALS993_2 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U4 dltch(9) DPWR DGND + $D_HI CLRBAR C + 1D 2D 3D 4D 5D 6D 7D 8D 9D + Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D_ALS993_3 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS993_1 utgate ( + tphlmn=7.9ns tphlty=14.9ns + tphlmx=25.9ns tplhmn=7.9ns + tplhty=14.9ns tplhmx=25.9ns + tpzlmn=4ns tpzlty=11ns + tpzlmx=21ns tpzhmn=4ns + tpzhty=11ns tpzhmx=21ns + tplzmn=2ns tplzty=6ns + tplzmx=14ns tphzmn=2ns + tphzty=6ns tphzmx=14ns + ) .model D_ALS993_2 utgate ( + tplhmn=4.9ns tplhty=9.9ns + tplhmx=16.9ns tphlmn=3.9ns + tphlty=7.9ns tphlmx=14.9ns + tpzlmn=4ns tpzlty=11ns + tpzlmx=20ns tpzhmn=4ns + tpzhty=11ns tpzhmx=20ns + tplzmn=1ns tplzty=6ns + tplzmx=12ns tphzmn=1ns + tphzty=6ns tphzmx=12ns + ) .model D_ALS993_3 ugff ( + twghmn=10ns twpclmn=10ns + tsudgmn=10ns thdgmn=5ns + tpdqlhmn=0.1ns tpdqlhty=0.1ns + tpdqlhmx=0.1ns tpdqhlmn=1.1ns + tpdqhlty=1.1ns tpdqhlmx=3.1ns + tpgqlhmn=3.1ns tpgqlhty=5.1ns + tpgqlhmx=7.1ns tpgqhlmn=4.1ns + tpgqhlty=6.1ns tpgqhlmx=11.1ns + tppcqhlmn=0.1ns tppcqhlty=0.1ns + tppcqhlmx=0.1ns + ) *$ *------------------------------------------------------------------------- * 74ALS994 10-bit D-TYPE Transparent Read-back Latches * * The ALS/AS Logic Data Book, 1986, TI * tvh 10/27/89 Update interface and model names * .subckt 74ALS994 OERBBAR C 1D 2D 3D 4D 5D 6D 7D 8D 9D 10D 1Q 2Q 3Q 4Q 5Q 6Q + 7Q 8Q 9Q 10Q + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 inv DPWR DGND + OERBBAR OERB + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} U2 dltch(10) DPWR DGND + $D_HI $D_HI C + 1D 2D 3D 4D 5D + 6D 7D 8D 9D 10D + Q1 Q2 Q3 Q4 Q5 + Q6 Q7 Q8 Q9 Q10 + $D_NC $D_NC $D_NC $D_NC $D_NC + $D_NC $D_NC $D_NC $D_NC $D_NC + D_ALS994_1 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U3 buf3a(10) DPWR DGND + Q1 Q2 Q3 Q4 Q5 + Q6 Q7 Q8 Q9 Q10 + OERB + 1D 2D 3D 4D 5D + 6D 7D 8D 9D 10D + D_ALS994_2 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U4 bufa(10) DPWR DGND + Q1 Q2 Q3 Q4 Q5 + Q6 Q7 Q8 Q9 Q10 + 1Q 2Q 3Q 4Q 5Q + 6Q 7Q 8Q 9Q 10Q + D_ALS994_3 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS994_1 ugff ( + twghmn=10ns tsudgmn=10ns + thdgmn=5ns tpdqlhmn=0.1ns + tpdqlhty=0.1ns tpdqlhmx=0.1ns + tpdqhlmn=0.1ns tpdqhlty=0.1ns + tpdqhlmx=0.1ns tpgqlhmn=3.1ns + tpgqlhty=5.1ns tpgqlhmx=7.1ns + tpgqhlmn=4.1ns tpgqhlty=5.1ns + tpgqhlmx=9.1ns + ) .model D_ALS994_2 utgate ( + tplzmn=2ns tplzty=9ns + tplzmx=16ns tphzmn=2ns + tphzty=9ns tphzmx=16ns + tpzlmn=4ns tpzlty=11ns + tpzlmx=21ns tpzhmn=4ns + tpzhty=11ns tpzhmx=21ns + ) .model D_ALS994_3 ugate ( + tplhmn=2.9ns tplhty=6.9ns + tplhmx=13.9ns tphlmn=3.9ns + tphlty=10.9ns tphlmx=17.9ns + ) *$ *------------------------------------------------------------------------- * 74ALS995 10-bit D-TYPE Transparent Read-back Latches * * The ALS/AS Logic Data Book, 1986, TI * tvh 10/27/89 Update interface and model names * .subckt 74ALS995 OERBBAR C 1D 2D 3D 4D 5D 6D 7D 8D 9D 10D 1Q 2Q 3Q 4Q 5Q 6Q + 7Q 8Q 9Q 10Q + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 inv DPWR DGND + OERBBAR OERB + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} U2 dltch(10) DPWR DGND + $D_HI $D_HI C + 1D 2D 3D 4D 5D + 6D 7D 8D 9D 10D + Q1 Q2 Q3 Q4 Q5 + Q6 Q7 Q8 Q9 Q10 + $D_NC $D_NC $D_NC $D_NC $D_NC + $D_NC $D_NC $D_NC $D_NC $D_NC + D_ALS995_1 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U3 buf3a(10) DPWR DGND + Q1 Q2 Q3 Q4 Q5 + Q6 Q7 Q8 Q9 Q10 + OERB + 1D 2D 3D 4D 5D + 6D 7D 8D 9D 10D + D_ALS995_2 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U4 inva(10) DPWR DGND + Q1 Q2 Q3 Q4 Q5 + Q6 Q7 Q8 Q9 Q10 + 1Q 2Q 3Q 4Q 5Q + 6Q 7Q 8Q 9Q 10Q + D_ALS995_3 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS995_1 ugff ( + twghmn=10ns tsudgmn=10ns + thdgmn=5ns tpdqlhmn=0.1ns + tpdqlhty=0.1ns tpdqlhmx=0.1ns + tpdqhlmn=0.1ns tpdqhlty=0.1ns + tpdqhlmx=0.1ns tpgqlhmn=3.1ns + tpgqlhty=5.1ns tpgqlhmx=8.1ns + tpgqhlmn=3.1ns tpgqhlty=5.1ns + tpgqhlmx=7.1ns + ) .model D_ALS995_2 utgate ( + tplzmn=2ns tplzty=8ns + tplzmx=15ns tphzmn=2ns + tphzty=8ns tphzmx=15ns + tpzlmn=4ns tpzlty=12ns + tpzlmx=21ns tpzhmn=4ns + tpzhty=12ns tpzhmx=21ns + ) .model D_ALS995_3 ugate ( + tplhmn=5.9ns tplhty=11.9ns + tplhmx=19.9ns tphlmn=3.9ns + tphlty=8.9ns tphlmx=14.9ns + ) *$ *------------------------------------------------------------------------- * 74ALS1000A Quadruple 2-Input Positive-NAND Buffers * * The ALS/AS Data Book, 1986, TI * atl 7/28/89 Update interface and model names * .subckt 74ALS1000A A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(2) DPWR DGND + A B Y + D_ALS1000A IO_ALS000 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS1000A ugate ( + tplhty=4ns tphlty=5ns + tplhmn=2ns tplhmx=8ns + tphlmn=2ns tphlmx=7ns + ) *$ *------------------------------------------------------------------------- * 74ALS1002A Quadruple 2-Input Positive-NOR Buffers * * The ALS/AS Data Book, 1986, TI * atl 7/28/89 Update interface and model names * .subckt 74ALS1002A A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nor(2) DPWR DGND + A B Y + D_ALS1002A IO_ALS000 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS1002A ugate ( + tplhty=4ns tphlty=4ns + tplhmn=2ns tplhmx=8ns + tphlmn=2ns tphlmx=7ns + ) *$ *------------------------------------------------------------------------- * 74ALS1003A Quadruple 2-Input Positive-NAND Buffers W/ Open-Collector Outputs * * The ALS/AS Data Book, 1986, TI * atl 7/28/89 Update interface and model names * .subckt 74ALS1003A A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(2) DPWR DGND + A B Y + D_ALS1003A IO_ALS000_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS1003A ugate ( + tplhty=18ns tphlty=7ns + tplhmn=10ns tplhmx=33ns + tphlmn=2ns tphlmx=12ns + ) *$ *------------------------------------------------------------------------- * 74ALS1004 Hex Inverting Drivers * * The ALS/AS Data Book, 1986, TI * atl 7/28/89 Update interface and model names * .subckt 74ALS1004 A Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 inv DPWR DGND + A Y + D_ALS1004 IO_ALS000 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS1004 ugate ( + tplhmn=1ns tplhmx=7ns + tphlmn=1ns tphlmx=6ns + ) *$ *------------------------------------------------------------------------- * 74ALS1005 Hex Inverting Buffers with Open-Collector Outputs * * The ALS/AS Data Book, 1986, TI * atl 7/28/89 Update interface and model names * .subckt 74ALS1005 A Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 inv DPWR DGND + A Y + D_ALS1005 IO_ALS000_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS1005 ugate ( + tplhmn=5ns tplhmx=30ns + tphlmn=2ns tphlmx=10ns + ) *$ *------------------------------------------------------------------------ * 74ALS1008A Quadruple 2-Input Positive-AND Buffers/Drivers * * The ALS/AS Data Book, 1986, TI * atl 7/28/89 Update interface and model names * .subckt 74ALS1008A A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 and(2) DPWR DGND + A B Y + D_ALS1008A IO_ALS000 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS1008A ugate ( + tplhmn=2ns tplhmx=9ns + tphlmn=3ns tphlmx=9ns + ) *$ *------------------------------------------------------------------------- * 74ALS1010A Triple 3-Input Positive-NAND Buffers * * The ALS/AS Data Book, 1986, TI * atl 7/28/89 Update interface and model names * .subckt 74ALS1010A A B C Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(3) DPWR DGND + A B C Y + D_ALS1010A IO_ALS000 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS1010A ugate ( + tplhty=5ns tphlty=5ns + tplhmn=2ns tplhmx=8ns + tphlmn=2ns tphlmx=8ns + ) *$ *------------------------------------------------------------------------- * 74ALS1011A Triple 3-Input Positive-AND Buffers * * The ALS/AS Data Book, 1986, TI * atl 7/28/89 Update interface and model names * .subckt 74ALS1011A A B C Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 and(3) DPWR DGND + A B C Y + D_ALS1011A IO_ALS000 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS1011A ugate ( + tplhmn=2ns tplhmx=10ns + tphlmn=3ns tphlmx=9ns + ) *$ *------------------------------------------------------------------------- * 74ALS1020A Dual 4-Input Positive-NAND Buffers * * The ALS/AS Data Book, 1986, TI * atl 7/28/89 Update interface and model names * .subckt 74ALS1020A A B C D Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(4) DPWR DGND + A B C D Y + D_ALS1020A IO_ALS000 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS1020A ugate ( + tplhty=5ns tphlty=5ns + tplhmn=2ns tplhmx=8ns + tphlmn=2ns tphlmx=7ns + ) *$ *------------------------------------------------------------------------- * 74ALS1032A Quadruple 2-Input Positive-OR Buffers * * The ALS/AS Data Book, 1986, TI * atl 7/28/89 Update interface and model names * .subckt 74ALS1032A A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 or(2) DPWR DGND + A B Y + D_ALS1032A IO_ALS000 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS1032A ugate ( + tplhty=6ns tphlty=7ns + tplhmn=2ns tplhmx=9ns + tphlmn=3ns tphlmx=12ns + ) *$ *------------------------------------------------------------------------- * 74ALS1034 Hex Drivers * * The ALS/AS Data Book, 1986, TI * atl 7/28/89 Update interface and model names * .subckt 74ALS1034 A Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 buf DPWR DGND + A Y + D_ALS1034 IO_ALS000 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS1034 ugate ( + tplhmn=1ns tplhmx=8ns + tphlmn=1ns tphlmx=8ns + ) *$ *------------------------------------------------------------------------- * 74ALS1035 Hex Noninverting Buffers With Open-Collector Outputs * * The ALS/AS Data Book, 1986, TI * atl 7/28/89 Update interface and model names * .subckt 74ALS1035 A Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 buf DPWR DGND + A Y + D_ALS1035 IO_ALS000_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS1035 ugate ( + tplhmn=5ns tplhmx=30ns + tphlmn=2ns tphlmx=12ns + ) *$ *------------------------------------------------------------------------- * 74ALS1240 Octal Buffers and Line Drivers with 3-STATE Outputs * * The ALS/AS Data Book, 1986, TI * atl 7/28/89 Update interface and model names * .subckt 74ALS1240 A1 A2 A3 A4 GBAR Y1 Y2 Y3 Y4 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UA inv DPWR DGND + GBAR G + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} UB inv3a(4) DPWR DGND + A1 A2 A3 A4 G Y1 Y2 Y3 Y4 + D_ALS1240 IO_ALS000 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS1240 utgate ( + tplhmn=2ns tplhmx=13ns + tplhty=7.5ns tphlmn=2ns + tphlmx=13ns tphlty=6.5ns + tpzhmn=4ns tpzhmx=20ns + tpzhty=11.5ns tpzlmn=6ns + tpzlmx=22ns tpzlty=14ns + tphzmn=2ns tphzmx=10ns + tphzty=7.5ns tplzmn=3ns + tplzmx=13ns tplzty=8ns + ) *$ *------------------------------------------------------------------------- * 74ALS1242A Octal Bus Transceivers with 3-STATE Outputs * * The ALS/AS Data Book, 1986, TI * atl 07/06/89 Update interface and model names * .subckt 74ALS1242A A1 A2 A3 A4 GABBAR GBA B1 B2 B3 B4 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UA inv DPWR DGND + GABBAR GAB + D0_GATE IO_ALS00 UB inv3a(4) DPWR DGND + A1 A2 A3 A4 GAB B1 B2 B3 B4 + D_ALS1242A_1 IO_ALS000 MNTYMXDLY={MNTYMXDLY} UC inv3a(4) DPWR DGND + B1 B2 B3 B4 GBA A1 A2 A3 A4 + D_ALS1242A_2 IO_ALS000 MNTYMXDLY={MNTYMXDLY} .ends * .model D_ALS1242A_1 utgate ( + tplhmn=2ns tplhmx=12ns + tplhty=6ns tphlmn=2ns + tphlmx=10ns tphlty=5ns + tpzhmn=4ns tpzhmx=17ns + tpzhty=10ns tpzlmn=5ns + tpzlmx=21ns tpzlty=13ns + tphzmn=2ns tphzmx=10ns + tphzty=6ns tplzmn=2ns + tplzmx=10ns tplzty=5ns + ) .model D_ALS1242A_2 utgate ( + tplhmn=2ns tplhmx=12ns + tplhty=6ns tphlmn=2ns + tphlmx=10ns tphlty=5ns + tpzhmn=5ns tpzhmx=20ns + tpzhty=12ns tpzlmn=6ns + tpzlmx=23ns tpzlty=14ns + tphzmn=2ns tphzmx=10ns + tphzty=6ns tplzmn=2ns + tplzmx=12ns tplzty=6ns + ) *$ *------------------------------------------------------------------------- * 74ALS1244A Octal Buffers and Line Drivers with 3-STATE Outputs * * The ALS/AS Data Book, 1986, TI * atl 7/28/89 Update interface and model names * .subckt 74ALS1244A A1 A2 A3 A4 GBAR Y1 Y2 Y3 Y4 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UA inv DPWR DGND + GBAR G + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} UB buf3a(4) DPWR DGND + A1 A2 A3 A4 G Y1 Y2 Y3 Y4 + D_ALS1244A IO_ALS000 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS1244A utgate ( + tplhmn=3ns tplhmx=14ns + tphlmn=3ns tphlmx=14ns + tpzhmn=6ns tpzhmx=22ns + tpzlmn=6ns tpzlmx=22ns + tphzmn=2ns tphzmx=10ns + tplzmn=3ns tplzmx=13ns + ) *$ *------------------------------------------------------------------------- * 74ALS1245A Octal Bus Transceivers with 3-STATE Outputs * * The ALS/AS Data Book, 1986, TI * atl 7/28/89 Update interface and model names * .subckt 74ALS1245A A1 A2 A3 A4 A5 A6 A7 A8 DIR GBAR B1 B2 B3 B4 B5 B6 B7 B8 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UBUFF bufa(2) DPWR DGND + GBAR DIR GBAR_BUF DIR_BUF + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} UA nor(2) DPWR DGND + GBAR_BUF DIR_BUF EB + D0_GATE IO_ALS00 UB inv DPWR DGND + GBAR_BUF G + D0_GATE IO_ALS00 UC and(2) DPWR DGND + DIR_BUF G EA + D0_GATE IO_ALS00 UD buf3a(8) DPWR DGND + A1 A2 A3 A4 A5 A6 A7 A8 + EA + B1 B2 B3 B4 B5 B6 B7 B8 + D_ALS1245A IO_ALS000 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UE buf3a(8) DPWR DGND + B1 B2 B3 B4 B5 B6 B7 B8 + EB + A1 A2 A3 A4 A5 A6 A7 A8 + D_ALS1245A IO_ALS000 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS1245A utgate ( + tplhmn=2ns tplhmx=13ns + tphlmn=2ns tphlmx=13ns + tpzhmn=8ns tpzhmx=25ns + tpzlmn=8ns tpzlmx=25ns + tphzmn=2ns tphzmx=12ns + tplzmn=3ns tplzmx=18ns + ) *$ *------------------------------------------------------------------------- * 74ALS2540 Octal Line Drivers/MOS with 3-STATE Outputs * * The ALS/AS Data Book, 1986, TI * atl 7/28/89 Update interface and model names * .subckt 74ALS2540 G1BAR G2BAR A1 A2 A3 A4 A5 A6 A7 A8 Y1 Y2 Y3 Y4 Y5 Y6 Y7 + Y8 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nor(2) DPWR DGND + G1BAR G2BAR T + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} U2 inv3a(8) DPWR DGND + A1 A2 A3 A4 A5 A6 A7 A8 + T + Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 + D_ALS2540 IO_ALS_25 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS2540 utgate ( + tplhmn=2ns tplhmx=12ns + tplhty=7.5ns tphlmn=2ns + tphlmx=11ns tphlty=5.6ns + tpzhmn=5ns tpzhmx=15ns + tpzhty=9ns tpzlmn=8ns + tpzlmx=20ns tpzlty=12.6ns + tphzmn=1ns tphzmx=10ns + tphzty=4ns tplzmn=2ns + tplzmx=12ns tplzty=7ns + ) *$ *------------------------------------------------------------------------- * 74ALS2541 Octal Buffers and Line Drivers with Input Pull-Up Resistors * * The ALS/AS Data Book, 1986, TI * atl 7/28/89 Update interface and model names * .subckt 74ALS2541 G1BAR G2BAR A1 A2 A3 A4 A5 A6 A7 A8 Y1 Y2 Y3 Y4 Y5 Y6 Y7 + Y8 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nor(2) DPWR DGND + G1BAR G2BAR T + D0_GATE IO_ALS00 IO_LEVEL={IO_LEVEL} U2 pullup(8) DPWR DGND + A1 A2 A3 A4 A5 A6 A7 A8 + IO_20K U3 buf3a(8) DPWR DGND + A1 A2 A3 A4 A5 A6 A7 A8 + T + Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 + D_ALS2541 IO_ALS_25 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS2541 utgate ( + tplhmn=2ns tplhmx=15ns + tplhty=8.7ns tphlmn=2ns + tphlmx=12ns tphlty=7ns + tpzhmn=5ns tpzhmx=15ns + tpzhty=9ns tpzlmn=8ns + tpzlmx=20ns tpzlty=12.6ns + tphzmn=1ns tphzmx=10ns + tphzty=4ns tplzmn=2ns + tplzmx=12ns tplzty=7ns + ) *$ *------------------------------------------------------------------------- * 74ALS8003 Dual 2-Input Positive-NAND Gates * * The ALS/AS Data Book, 1986, TI * atl 7/28/89 Update interface and model names * .subckt 74ALS8003 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(2) DPWR DGND + A B Y + D_ALS8003 IO_ALS000 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS8003 ugate ( + tplhmn=3ns tplhmx=11ns + tphlmn=2ns tphlmx=8ns + ) *$ *------------------------------------------------------------------------- * 74ALS29821 10-bit Bus Interface Flip-Flops with 3-state Outputs * * The ALS/AS Data Book, 1986, TI * tdn 10/26/89 Update interface and model names * .subckt 74ALS29821 CLK OCBAR 1D 2D 3D 4D 5D 6D 7D 8D 9D 10D 1Q 2Q 3Q 4Q 5Q + 6Q 7Q 8Q 9Q 10Q + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 dff(10) DPWR DGND + $D_HI $D_HI CLK + 1D 2D 3D 4D 5D + 6D 7D 8D 9D 10D + 1Q1 2Q1 3Q1 4Q1 5Q1 + 6Q1 7Q1 8Q1 9Q1 10Q1 + $D_NC $D_NC $D_NC $D_NC $D_NC + $D_NC $D_NC $D_NC $D_NC $D_NC + D_ALS29821_1 IO_ALS000 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 inv DPWR DGND + OCBAR OC + D0_GATE IO_ALS000 IO_LEVEL={IO_LEVEL} U3 buf3a(10) DPWR DGND + 1Q1 2Q1 3Q1 4Q1 5Q1 + 6Q1 7Q1 8Q1 9Q1 10Q1 + OC + 1Q 2Q 3Q 4Q 5Q + 6Q 7Q 8Q 9Q 10Q + D_ALS29821_2 IO_ALS000 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS29821_1 ueff ( + tpclkqhlty=1ns tpclkqlhty=1ns + ) .model D_ALS29821_2 utgate ( + tphzty=5ns tplzty=6ns + tpzhty=12ns tpzlty=11ns + tphlty=6ns tplhty=5ns + ) *$ *------------------------------------------------------------------------- * 74ALS29822 10-bit Bus Interface Flip-Flops with 3-state Outputs * * The ALS/AS Data Book, 1986, TI * tdn 10/26/89 Update interface and model names * .subckt 74ALS29822 CLK OCBAR 1DB 2DB 3DB 4DB 5DB 6DB 7DB 8DB 9DB 10DB 1Q 2Q + 3Q 4Q 5Q 6Q 7Q 8Q 9Q 10Q + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 dff(10) DPWR DGND + $D_HI $D_HI CLK + 1DB 2DB 3DB 4DB 5DB + 6DB 7DB 8DB 9DB 10DB + $D_NC $D_NC $D_NC $D_NC $D_NC + $D_NC $D_NC $D_NC $D_NC $D_NC + 1Q1 2Q1 3Q1 4Q1 5Q1 + 6Q1 7Q1 8Q1 9Q1 10Q1 + D_ALS29822_1 IO_ALS000 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 inv DPWR DGND + OCBAR OC + D0_GATE IO_ALS000 IO_LEVEL={IO_LEVEL} U3 buf3a(10) DPWR DGND + 1Q1 2Q1 3Q1 4Q1 5Q1 + 6Q1 7Q1 8Q1 9Q1 10Q1 + OC + 1Q 2Q 3Q 4Q 5Q + 6Q 7Q 8Q 9Q 10Q + D_ALS29822_2 IO_ALS000 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS29822_1 ueff ( + tpclkqhlty=1ns tpclkqlhty=1ns + ) .model D_ALS29822_2 utgate ( + tphzty=5ns tplzty=6ns + tpzhty=12ns tpzlty=11ns + tphlty=6ns tplhty=5ns + ) *$ *------------------------------------------------------------------------- * 74ALS29823 9-bit Bus Interface Flip-Flops with 3-state Outputs * * The ALS/AS Data Book, 1986, TI * tdn 10/26/89 Update interface and model names * .subckt 74ALS29823 CLRBAR CLK CLKENBAR OCBAR 1D 2D 3D 4D 5D 6D 7D 8D 9D 1Q + 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 inva(2) DPWR DGND + CLKENBAR OCBAR CLKEN OC + D0_GATE IO_ALS000 IO_LEVEL={IO_LEVEL} U2 and(2) DPWR DGND + CLKEN CLK CK + D0_GATE IO_ALS000 IO_LEVEL={IO_LEVEL} U3 dff(9) DPWR DGND + $D_HI CLRBAR CK + 1D 2D 3D 4D 5D 6D 7D 8D 9D + 1Q1 2Q1 3Q1 4Q1 5Q1 6Q1 7Q1 8Q1 9Q1 + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D_ALS29823_1 IO_ALS000 MNTYMXDLY={MNTYMXDLY} U4 buf3a(9) DPWR DGND + 1Q1 2Q1 3Q1 4Q1 5Q1 6Q1 7Q1 8Q1 9Q1 + OC + 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q + D_ALS29823_2 IO_ALS000 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS29823_1 ueff ( + tpclkqhlty=1ns tpclkqlhty=1ns + tppcqhlty=7.5ns tppcqlhty=8.5ns + ) .model D_ALS29823_2 utgate ( + tphzty=5ns tplzty=5.5ns + tpzhty=12ns tpzlty=11ns + tplhty=4.5ns tphlty=5.5ns + ) *$ *------------------------------------------------------------------------- * 74ALS29824 9-bit Bus Interface Flip-Flops with 3-state Outputs * * The ALS/AS Data Book, 1986, TI * tdn 10/26/89 Update interface and model names * .subckt 74ALS29824 CLRBAR CLK CLKENBAR OCBAR 1DB 2DB 3DB 4DB 5DB 6DB 7DB 8DB + 9DB 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 inva(2) DPWR DGND + CLKENBAR OCBAR CLKEN OC + D0_GATE IO_ALS000 IO_LEVEL={IO_LEVEL} U2 and(2) DPWR DGND + CLKEN CLK CK + D0_GATE IO_ALS000 IO_LEVEL={IO_LEVEL} U3 dff(9) DPWR DGND + $D_HI CLRBAR CK + 1DB 2DB 3DB 4DB 5DB 6DB 7DB 8DB 9DB + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + 1Q1 2Q1 3Q1 4Q1 5Q1 6Q1 7Q1 8Q1 9Q1 + D_ALS29824_1 IO_ALS000 MNTYMXDLY={MNTYMXDLY} U4 buf3a(9) DPWR DGND + 1Q1 2Q1 3Q1 4Q1 5Q1 6Q1 7Q1 8Q1 9Q1 + OC + 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q + D_ALS29824_2 IO_ALS000 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS29824_1 ueff ( + tpclkqhlty=1ns tpclkqlhty=1ns + tppcqlhty=8.5ns tppcqhlty=7.5ns + ) .model D_ALS29824_2 utgate ( + tphzty=5ns tplzty=5.5ns + tpzhty=12ns tpzlty=11ns + tplhty=4.5ns tphlty=5.5ns + ) *$ *------------------------------------------------------------------------- * 74ALS29825 8-bit Bus Interface Flip-Flops with 3-state Outputs * * The ALS/AS Data Book, 1986, TI * tdn 10/27/89 Update interface and model names * .subckt 74ALS29825 CLRBAR CLKENBAR CLK OCBAR1 OCBAR2 OCBAR3 1D 2D 3D 4D 5D + 6D 7D 8D 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 buf DPWR DGND + CLK CKI + D0_GATE IO_ALS000 IO_LEVEL={IO_LEVEL} U2 nora(2,2) DPWR DGND + CLKENBAR RESET $D_LO CKE CKE CKEB + D0_GATE IO_ALS000 IO_LEVEL={IO_LEVEL} U3 anda(2,2) DPWR DGND + CKI CKE CKI CKEB CK1 RESET + D0_GATE IO_ALS000 U4 dff(8) DPWR DGND + $D_HI CLRBAR CK1 + 1D 2D 3D 4D 5D 6D 7D 8D + 1Q1 2Q1 3Q1 4Q1 5Q1 6Q1 7Q1 8Q1 + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D_ALS29826_1 IO_ALS000 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U5 nor(3) DPWR DGND + OCBAR1 OCBAR2 OCBAR3 OC + D0_GATE IO_ALS000 IO_LEVEL={IO_LEVEL} U6 buf3a(8) DPWR DGND + 1Q1 2Q1 3Q1 4Q1 5Q1 6Q1 7Q1 8Q1 + OC + 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q + D_ALS29825_2 IO_ALS000 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS29825_1 ueff ( + tpclkqhlty=1ns tpclkqlhty=1ns + tppcqhlty=7ns tppcqlhty=8ns + ) .model D_ALS29825_2 utgate ( + tpzhty=12ns tpzlty=11ns + tphzty=5ns tplzty=6ns + tphlty=6ns tplhty=5ns + ) *$ *------------------------------------------------------------------------- * 74ALS29826 8-bit Bus Interface Flip-Flops with 3-state Outputs * * The ALS/AS Data Book, 1986, TI * tdn 10/27/89 Update interface and model names * .subckt 74ALS29826 CLRBAR CLKENBAR CLK OCBAR1 OCBAR2 OCBAR3 1DB 2DB 3DB 4DB + 5DB 6DB 7DB 8DB 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 buf DPWR DGND + CLK CKI + D0_GATE IO_ALS000 IO_LEVEL={IO_LEVEL} U2 nora(2,2) DPWR DGND + CLKENBAR RESET $D_LO CKE CKE CKEB + D0_GATE IO_ALS000 IO_LEVEL={IO_LEVEL} U3 anda(2,2) DPWR DGND + CKI CKE CKI CKEB CK1 RESET + D0_GATE IO_ALS000 U4 dff(8) DPWR DGND + $D_HI CLRBAR CK1 + 1DB 2DB 3DB 4DB 5DB 6DB 7DB 8DB + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + 1Q1 2Q1 3Q1 4Q1 5Q1 6Q1 7Q1 8Q1 + D_ALS29826_1 IO_ALS000 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U5 nor(3) DPWR DGND + OCBAR1 OCBAR2 OCBAR3 OC + D0_GATE IO_ALS000 IO_LEVEL={IO_LEVEL} U6 buf3a(8) DPWR DGND + 1Q1 2Q1 3Q1 4Q1 5Q1 6Q1 7Q1 8Q1 + OC + 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q + D_ALS29826_2 IO_ALS000 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS29826_1 ueff ( + tpclkqhlty=1ns tpclkqlhty=1ns + tppcqhlty=7ns tppcqlhty=8ns + ) .model D_ALS29826_2 utgate ( + tpzhty=12ns tpzlty=11ns + tphzty=5ns tplzty=6ns + tphlty=6ns tplhty=5ns + ) *$ *------------------------------------------------------------------------- * 74ALS29827 10-bit Buffers and Bus Drivers with 3-state Outputs * * The ALS/AS Data Book, 1986, TI * tdn 10/27/89 Update interface and model names * .subckt 74ALS29827 G1BAR G2BAR A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 Y1 Y2 Y3 Y4 Y5 + Y6 Y7 Y8 Y9 Y10 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nor(2) DPWR DGND + G1BAR G2BAR OC + D0_GATE IO_ALS000 IO_LEVEL={IO_LEVEL} U2 buf3a(10) DPWR DGND + A1 A2 A3 A4 A5 + A6 A7 A8 A9 A10 + OC + Y1 Y2 Y3 Y4 Y5 + Y6 Y7 Y8 Y9 Y10 + D_ALS29827 IO_ALS000 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS29827 utgate ( + tplhty=3.5ns tplhmx=6ns + tphlty=6.5ns tphlmx=8ns + tpzhty=6.5ns tpzhmx=12ns + tpzlty=9.5ns tpzlmx=12ns + tphzty=10ns tphzmx=16ns + tplzty=4ns tplzmx=9ns + ) *$ *------------------------------------------------------------------------- * 74ALS29828 10-bit Buffers and Bus Drivers with 3-state Outputs * * The ALS/AS Data Book, 1986, TI * tdn 10/27/89 Update interface and model names * .subckt 74ALS29828 G1BAR G2BAR A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 Y1 Y2 Y3 Y4 Y5 + Y6 Y7 Y8 Y9 Y10 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nor(2) DPWR DGND + G1BAR G2BAR OC + D0_GATE IO_ALS000 IO_LEVEL={IO_LEVEL} U2 inv3a(10) DPWR DGND + A1 A2 A3 A4 A5 + A6 A7 A8 A9 A10 + OC + Y1 Y2 Y3 Y4 Y5 + Y6 Y7 Y8 Y9 Y10 + D_ALS29828 IO_ALS000 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_ALS29828 utgate ( + tplhty=4ns tplhmx=5.2ns + tphlty=3ns tphlmx=5.9ns + tpzhty=6.5ns tpzhmx=12ns + tpzlty=9.5ns tpzlmx=12ns + tphzty=10ns tphzmx=16ns + tplzty=4ns tplzmx=9ns + ) *$